ZL30301GAG

ZL30301GAG Datasheet

ZL30301

Part	Datasheet
ZL30301GAG	ZL30301GAG (pdf)

PDF Datasheet Preview
ZL30301 Timing over Packet ToP Technology Data Sheet • Recovers and transmits network synchronization over Ethernet, IP and MPLS Networks • Output clocks meet ITU-T G.823 and G.824 traffic interface specifications, and ANSI T1.403 timing requirements • Fully configurable, enabling performance to be tailored to application and network requirements • Generates outgoing packet reference locked to the TS_CLKi electrical reference clock • Recovers up to 4 independent clock frequencies from packet streams, in the frequency range MHz to 10 MHz • Average frequency accuracy better than ± 15 ppb • Supports Master, Slave and Repeater modes of operation • Supports user defined timing recovery algorithms • Dual configurable packet interface • Two MII interfaces • One MII and one GMII/TBI • Flexible 32 bit host CPU interface Motorola PowerQUICCTM 1 and 2 compatible September 2005 Ordering Information ZL30301GAG 324 PBGA -40°C to +85°C Trays • Flexible classification of incoming packets at layers 2, 3, 4 and 5 • Flexible, multi-protocol packet encapsulation, with support for Ethernet, VLAN, IPv4/6, MPLS, L2TPv3, UDP and RTP • JTAG IEEE 1149 boundary-scan interface • GSM, UMTS air interface synchronization over a packet network • Circuit Emulation Service over Packets CESoP , TDM over IP TDMoIP • IP-PBX • VoIP Gateways • Video Conferencing • Broadband Video Distribution ZZLL3300330011 Host Processor running Zarlink Timing Recovery Algorithm Host Processor Interface Host Processor Interface GMII/PCS or MII Packet Engine Tim estam p Engine Clock Synthesis JTAG CLKo[0] CLKo[1] CLKo[2] CLKo[3] CLKi[0] CLKi[1] CLKi[2] CLKi[3] EXT_CLKo_REF TS_CLKi TCK TDI TDO TMS TRST Figure 1 - ZL30301 Functional Block Diagram Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved. ZL30301 Data Sheet Zarlink Semiconductor Inc. ZL30301 Data Sheet Table of Contents Description 6 Physical Specification 6 External Interface Description 11 Clock Interface. 11 Packet Interfaces. 12 CPU Interface 17 System Function Interface. 19 Test Facilities. 20 Administration, Control and Test Interface. 20 JTAG Interface 20 Miscellaneous Inputs 21 Power and Ground Connections 21 Internal Connections 22 No Connections 22 Device ID 22 Typical Applications 23 Edge of the PSN 23 Wireless Access Applications 24 Functional Description 25 Modes of Operation 25 Master Mode of Operation 25 Slave Mode of Operation 26 Timing Repeater Mode of Operation 27 Timing Redundancy. 28 Clock Recovery 28 Adaptive Clock Recovery 28 Differential Clock Recovery 30 Combination of Adaptive and Differential Clock Recovery. 31 Handling of Non-Timing Packets 33 Snoop Mode. 33 Pass-through Mode 33 Standalone Mode 34 Contribution of the Network and Local Oscillator on the Performance 34 CPU Interface 35 Management and Clock Quality Statistics 36 Statistics on Received Timing Packets Slave mode 36 Statistics on Transmitted Timing Packets Master mode 37 Status Information on Recovered Clocks. 37 Processing of Incoming Packets 38 System Features 39 Loopback Modes 39 Host Packet Generation 39 Power Up Sequence 39 JTAG Interface and Board Level Test Features 40 External Component Requirements 40 Miscellaneous Features. 40 Test Modes Operation 41 Overview 41 System Normal Mode 41 System Tri-State Mode. 41 Test Mode Control 41 Zarlink Semiconductor Inc. ZL30301

PDF Datasheet Preview

ZL30301

Timing over Packet ToP Technology

Data Sheet
• Recovers and transmits network synchronization over Ethernet, IP and MPLS Networks
• Output clocks meet ITU-T G.823 and G.824 traffic interface specifications, and ANSI T1.403 timing requirements
• Fully configurable, enabling performance to be tailored to application and network requirements
• Generates outgoing packet reference locked to the TS_CLKi electrical reference clock
• Recovers up to 4 independent clock frequencies from packet streams, in the frequency range MHz to 10 MHz
• Average frequency accuracy better than ± 15 ppb
• Supports Master, Slave and Repeater modes of operation
• Supports user defined timing recovery algorithms
• Dual configurable packet interface
• Two MII interfaces
• One MII and one GMII/TBI
• Flexible 32 bit host CPU interface Motorola PowerQUICCTM 1 and 2 compatible

September 2005
Ordering Information ZL30301GAG 324 PBGA
-40°C to +85°C

Trays
• Flexible classification of incoming packets at layers 2, 3, 4 and 5
• Flexible, multi-protocol packet encapsulation, with support for Ethernet, VLAN, IPv4/6, MPLS, L2TPv3, UDP and RTP
• JTAG IEEE 1149 boundary-scan interface
• GSM, UMTS air interface synchronization over a packet network
• Circuit Emulation Service over Packets CESoP , TDM over IP TDMoIP
• IP-PBX
• VoIP Gateways
• Video Conferencing
• Broadband Video Distribution

ZZLL3300330011

Host Processor running Zarlink Timing Recovery Algorithm

Host Processor Interface

Host Processor Interface

GMII/PCS or MII

Packet Engine

Tim estam p Engine

Clock Synthesis

JTAG

CLKo[0] CLKo[1] CLKo[2] CLKo[3]

CLKi[0] CLKi[1] CLKi[2] CLKi[3]

EXT_CLKo_REF

TS_CLKi

TCK TDI TDO TMS TRST

Figure 1 - ZL30301 Functional Block Diagram

Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved.

ZL30301

Data Sheet

Zarlink Semiconductor Inc.

ZL30301

Data Sheet

Table of Contents

Description 6

Physical Specification 6

External Interface Description 11 Clock Interface. 11 Packet Interfaces. 12 CPU Interface 17 System Function Interface. 19 Test Facilities. 20 Administration, Control and Test Interface. 20 JTAG Interface 20 Miscellaneous Inputs 21 Power and Ground Connections 21 Internal Connections 22 No Connections 22 Device ID 22

Typical Applications 23 Edge of the PSN 23 Wireless Access Applications 24

Functional Description 25 Modes of Operation 25 Master Mode of Operation 25 Slave Mode of Operation 26 Timing Repeater Mode of Operation 27 Timing Redundancy. 28 Clock Recovery 28 Adaptive Clock Recovery 28 Differential Clock Recovery 30 Combination of Adaptive and Differential Clock Recovery. 31 Handling of Non-Timing Packets 33 Snoop Mode. 33 Pass-through Mode 33 Standalone Mode 34 Contribution of the Network and Local Oscillator on the Performance 34 CPU Interface 35 Management and Clock Quality Statistics 36 Statistics on Received Timing Packets Slave mode 36 Statistics on Transmitted Timing Packets Master mode 37 Status Information on Recovered Clocks. 37 Processing of Incoming Packets 38

System Features 39 Loopback Modes 39 Host Packet Generation 39 Power Up Sequence 39 JTAG Interface and Board Level Test Features 40 External Component Requirements 40 Miscellaneous Features. 40 Test Modes Operation 41 Overview 41 System Normal Mode 41 System Tri-State Mode. 41 Test Mode Control 41

Zarlink Semiconductor Inc.

ZL30301

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ZL30301GAG Datasheet file may be downloaded here without warranties.

Datasheet ID: ZL30301GAG 649219