ZL30241LDG1
ZL30241LDG1 Datasheet
ZL30241 Single Channel Precision Universal Clock Generator and NCO
| Part | Datasheet |
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ZL30241LDG1 |
ZL30241LDG1 (pdf) |
| Related Parts | Information |
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ZL30241LDF1 |
ZL30241LDF1 |
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| Data Sheet ZL30241 Single Channel Precision Universal Clock Generator and NCO Ordering Information ZL30241LDG1 48 Pin QFN Tray ZL30241LDF1 48 Pin QFN Tape/Reel Matte Tin -40oC to +85oC Package size 7 x 7 mm PLL • One PLL with ultra low jitter • Supports integer, fractional and ratio modes Ratio mode for flexible FEC rate support Inputs • Crystals, crystal oscillator or reference singled ended or differential inputs Crystal Input range from 22 MHz to 54 MHz Crystal oscillator or single-ended reference input from 22 MHz to 180 MHz Differential reference input from 22 to 864 MHz Configuration • Generates clock signals at power-up per user defined custom configuration factory programmable • Dynamically configurable via SPI and volatile configuration registers Outputs • Synthesizes two different frequencies from the PLL Up to 275 fs RMS jitter for integer mode Up to 400 fs RMS jitter for fractional mode • Each output is independently configurable to support LVDS, LVPECL, HCSL, LVCMOS • Generates any output frequency from 12 MHz to 914 MHz • Generates output from crystal, a crystal oscillator or reference • NCO accuracy less than ppb in fractional mode • Clocks for NPUs, FPGAs, 10G CDRs, high-speed ADC, PCIe interface devices, Ethernet switches and PHYs • Timing for optical, storage, networking and broadcast video applications In_p Single Ended/ Input In_n Differential Divider XO1 Crystal Input 1 Figure 1 • Block Diagram November 2012 Microsemi Corporation PLL1 Single Ended/ Differential Divider 1 Single Ended/ Differential Divider 2 Single Ended/ Differential RefOut Enable RefOut_p RefOut_n Output Enable1 Out1_p Out1_n Output Enable2 Out2_p Out2_n Configuration and Status External Filters Filter 1 ZL30241 Data Sheet Table of Contents Pin Diagram 5 Pin Description. 5 Description 8 Input Configuration 8 Output Configuration 11 Output Control Pins 12 Output Electrical Format - LVCMOS, LVDS, LVPECL, or HCSL . 12 Reference Input 12 Crystal Oscillator 13 PLLs 13 Integer Mode 14 Fractional Mode 14 Ratio Mode. 14 Output Dividers 14 Status Indicators 15 Resets 15 |
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