ZL30240LDF1

ZL30240LDF1 Datasheet

ZL30240 Dual Channel Precision Universal Clock Generator and NCO

Part	Datasheet
ZL30240LDF1	ZL30240LDF1 (pdf)

Related Parts	Information
ZL30240LDG1	ZL30240LDG1

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Data Sheet ZL30240 Dual Channel Precision Universal Clock Generator and NCO Ordering Information ZL30240LDG1 48 Pin QFN Tray ZL30240LDF1 48 Pin QFN Tape/Reel Matte Tin -40oC to +85oC Package size 7 x 7 mm PLL • Two independently programmable PLLs with ultra low jitter • Supports integer, fractional and ratio modes Ratio mode for flexible FEC rate support Inputs • Crystals, crystal oscillator or reference singled ended or differential inputs Crystal Input range from 22 MHz to 54 MHz Crystal oscillator or single-ended reference input from 22 MHz to 180 MHz Differential reference input from 22 to 864 MHz Configuration • Generates clock signals at power-up per user defined custom configuration factory programmable • Dynamically configurable via SPI and volatile configuration registers Outputs • Synthesizes four different frequencies simultaneously from two different PLLs Up to 275 fs RMS jitter for integer mode Up to 400 fs RMS jitter for fractional mode • Each output is independently configurable to support LVDS, LVPECL, HCSL, LVCMOS • Generates any output frequency from 12 MHz 914 MHz • Generates output from either crystals, a crystal oscillator or reference • NCO accuracy less than ppb in fractional mode • Clocks for NPUs, FPGAs, 10G CDRs, high-speed ADC, PCIe interface devices, Ethernet switches and PHYs • Timing for optical, storage, networking and broadcast video applications In_p Single Ended/ Input In_n Differential Divider XO1 Crystal Input 1 XO3 Crystal Input 2 Configuration and Status Figure 1 - Block Diagram November 2012 Microsemi Corporation PLL1 PLL2 Single Ended/ Differential Divider 1 Single Ended/ Differential Divider 2 Single Ended/ Differential Divider 3 Single Ended/ Differential Divider 4 Single Ended/ Differential External Filters RefOut Enable RefOut_p RefOut_n Output Enable1 Out1_p Out1_n Output Enable2 Out2_p Out2_n Output Enable3 Out3_p Out3_n

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Data Sheet

ZL30240 Dual Channel Precision Universal Clock Generator and NCO
Ordering Information ZL30240LDG1 48 Pin QFN Tray ZL30240LDF1 48 Pin QFN Tape/Reel

Matte Tin -40oC to +85oC

Package size 7 x 7 mm

PLL
• Two independently programmable PLLs with ultra low jitter
• Supports integer, fractional and ratio modes

Ratio mode for flexible FEC rate support

Inputs
• Crystals, crystal oscillator or reference singled ended or differential inputs

Crystal Input range from 22 MHz to 54 MHz

Crystal oscillator or single-ended reference input from 22 MHz to 180 MHz

Differential reference input from 22 to 864 MHz

Configuration
• Generates clock signals at power-up per user defined custom configuration factory programmable
• Dynamically configurable via SPI and volatile configuration registers

Outputs
• Synthesizes four different frequencies simultaneously from two different PLLs Up to 275 fs RMS jitter for integer mode Up to 400 fs RMS jitter for fractional mode
• Each output is independently configurable to support LVDS, LVPECL, HCSL, LVCMOS
• Generates any output frequency from 12 MHz 914 MHz
• Generates output from either crystals, a crystal oscillator or reference
• NCO accuracy less than ppb in fractional mode
• Clocks for NPUs, FPGAs, 10G CDRs, high-speed ADC, PCIe interface devices, Ethernet switches and PHYs
• Timing for optical, storage, networking and broadcast video applications

In_p

Single Ended/

Input

In_n

Differential Divider

XO1 Crystal Input 1

XO3 Crystal Input 2

Configuration and Status

Figure 1 - Block Diagram

November 2012 Microsemi Corporation

PLL1

PLL2

Single Ended/ Differential

Divider 1

Single Ended/ Differential

Divider 2

Single Ended/ Differential

Divider 3

Single Ended/ Differential

Divider 4

Single Ended/ Differential

External Filters

RefOut Enable RefOut_p RefOut_n

Output Enable1 Out1_p Out1_n

Output Enable2 Out2_p Out2_n

Output Enable3 Out3_p Out3_n

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Datasheet ID: ZL30240LDF1 649216