ZL30230GGG20038

ZL30230GGG20038 Datasheet

ZL30230 Four Channel Universal

Part	Datasheet
ZL30230GGG20038	ZL30230GGG20038 (pdf)

PDF Datasheet Preview
• Generates clock signals at power-up per user defined custom OTP One Time Programmable configuration • Dynamically configurable via SPI/I2C interface and volatile configuration registers • Four independently programmable clock generators output any clock rate from 1 kHz to 750 MHz precision / 350 MHz general purpose • Precision clock generators output clocks with jitter below ps RMS for 10 G PHYs • General purpose clock generators output a wide range of digital bus clocks • Operates from a single crystal resonator, clock oscillator or voltage controlled oscillator • Supports programmable frequency offsets for clock margining or for use as a digitally controlled oscillator • Eight LVPECL outputs max rate 750 MHz • Four LVCMOS outputs max rate MHz ZL30230 Four Channel Universal Clock Generator Data Sheet March 2015 Ordering Information ZL30230GGG2 100 Pin LBGA* 11mmx11mm Trays Pb Free Tin/Silver/Copper -40oC to +85oC • Eight outputs configurable as LVCMOS at or V, max rate160 MHz or LVDS/LVPECL/HCSL, max rate 350 MHz • Timing for NPUs, FPGAs, Ethernet switches and PCIe switches • Timing for 10 Gigabit CDRs, Rapid-IO, PCIe, Serial MII, Star Fabric, Fibre Channel, XAUI • Processor clock, Processor bus clock, SDRAM clock, DDR clock Figure 1 - Functional Block Diagram Copyright 2015, Microsemi Corporation. All Rights Reserved. ZL30230 Data Sheet Table of Contents Pin Diagram 8 Pin Description. 9 Application Example 13 Functional Description 14 Frequency Synthesis Engine. 14 Dividers and Skew Management. 14 Output Multiplexer 15 Output Drivers 16 Programmable Single Ended Driver - Slew Rate Control 18 Master Clock Interface. 19 Clock Oscillator and Crystal Circuit 19 Power Up/Down Sequence 20 Power Supply Filtering. 20 Power on Reset and Initialization Circuit 21 Ultra Low Jitter Synthesizer Filter Components and Recommended Layout 22 Configuration and Control 23 Configuration Registers 23 Default Configuration 23 Custom OTP Configuration 23 SPI/I2C Configuration 23 Output Multiplexer Configuration and Programmability 23 Synthesizers Configuration and Programmability 23 Output Dividers and Skew Management Configuration and Programmability. 23 Output Drivers configuration and Programmability 23 GPIO Configuration and Programmability 24 Host Interface 27 Serial Peripheral Interface 27 Least Significant Bit LSB First Transmission Mode 28 Most Significant Bit MSB First Transmission Mode 28 SPI Burst Mode Operation 29 I2C Interface. 29 Register Map 31 Detailed Register Map 39 AC and DC Electrical Characteristics 105 Performance Characterization 115 Output Clocks RMS Jitter Generation 115 Output Clocks Cycle-to-Cycle Jitter Generation 116 Thermal Characteristics 116 Mechanical Drawing 117 Package Markings 118 100-pin BGA. Package Top Mark Format 118 Microsemi Corporation ZL30230 Data Sheet List of Figures Figure 1 - Functional Block Diagram 1 Figure 2 - Package Description 8 Figure 3 - Application Diagram. 13 Figure 4 - Output Clock Muxing Configuration 15 Figure 5 - Terminating LVPECL Outputs 16 Figure 6 - Terminating AC coupled LVPECL Outputs 17 Figure 7 - Terminating LVCMOS Outputs 17 Figure 8 - Terminating LVDS Outputs 18 Figure 9 - Terminating HCSL Outputs 18 Figure 10 - Clock Oscillator Circuit. 19 Figure 11 - Typical Power-Up Reset and Configuration Circuit 21 Figure 12 - APLL Filter Component Values 22 Figure 13 - Recommended Layout for Loop Filters 22 Figure 14 - Serial Interface Configuration 27 Figure 15 - Serial Peripheral Interface Functional Waveforms - LSB First Mode 28 Figure 16 - Serial Peripheral Interface Functional Waveforms - MSB First Mode 28 Figure 17 - Example of a Burst Mode Operation 29 Figure 18 - I2C Data Write Protocol 29 Figure 19 - I2C Data Read Protocol. 29 Figure 20 - I2C 7-bit Slave Address 30 Figure 21 - I2C Data Write Burst Mode 30 Figure 22 - I2C Data Read Burst Mode 30 Figure 23 - Accessing Multi-byte Register Values 31 Figure 24 - Timing Parameter Measurement Voltage Levels. 110 Figure 25 - Output Timing Referenced To hpclkout0/clkout0. 111 Figure 26 - Serial Peripheral Interface Timing - LSB First Mode 112 Figure 27 - Serial Peripheral Interface Timing - MSB First Mode 113 Figure 28 - I2C Serial Microport Timing 114 Figure 29 - Non-customized Device Top Mark. 118 Figure 30 - Custom Factory Programmed Device Top Mark 118 Microsemi Corporation ZL30230 Data Sheet List of Tables Table 1 - Pin Description 9 Table 2 - Slew Rate Control Limits Versus Output Clock Rise/Fall Times. 19 Table 3 - Master Clock Frequency Selection 20 Table 4 - Serial Interface Selection 27 Table 5 - Register Map 33 Table 6 - Serial Peripheral Interface Timing. 112 Table 7 - I2C Serial Microport Timing 114 Table 8 - Jitter Generation Specifications - HPDIFF Outputs 115 Table 9 - Jitter Generation Specifications - HPOUT Outputs. 115 Table 10 - Jitter Generation Specifications - Configurable Outputs driven from High Performance Synthesizers - Differential Mode 115 Table 11 - Jitter Generation Specifications - Configurable Outputs driven from General Purpose Synthesizers - Differential Mode 115 Table 12 - Jitter Generation Specifications - HPDIFF Outputs 116 Table 13 - Thermal Data 116 Table 14 - Package Marking Legend 118 Microsemi Corporation ZL30230 Data Sheet Change Summary Below are the changes from the June 2012 issue to the March 2015 issue. Page Item 1 Ordering Information 23 Custom OTP Configuration 118 “Package Markings“ Change Removed ZL30230GGG leaded version from the ordering information Removed reference to ZLAN-301 Added section 13 for package markings Below are the changes from the January 2012 issue to the June 2012 issue. 36 and 91 Item Register 0xC6 - Chip_revision_2 Output to output alignment Change Updated chip_revision to 0x03 Updated limits for tOUT2OUTD to +/- 1 ns Below are the changes from the December 2011 issue to the January 2012 issue. Page 31 32 39 36, 91 Item Procedure for writing registers Reading from Sticky Read registers Time between two write accesses to the same register 0x00 - id_reg Register 0x0D - Sticky_r_lock Register 0xC6 - Chip_revision_2 Change Added a new procedure to update registers Updated Sticky read Procedure Changed wait time from 200ms to 8ms, added 0x0D as register not requiring wait time Updated chip_revision bits Updated Description Added register 0xC6 Below are the changes from the July 2011 issue to the December 2011 issue. Page 32 39 87 Item Reading from Sticky Read registers Register 0x00 - id_reg Register 0x0D - sticky_r_lock Register 0xB7 - synth2_stop_clock 103 Register 0xF7 - spurs_suppression 117 Mechanical Drawing Change Updated Sticky read Procedure updated ready_indication description added register Bits[3:2] - changed outclk2 to outclk1 Bits[5:4] - changed outclk3 to outclk2 updated spurs_suppression description repalced drawing to reflect correct package description Microsemi Corporation ZL30230 Data Sheet Below are the changes from the June 2011 issue to the July 2011 issue. Page 1, 9,14, 16, 23, 23, 111 9, 10, 20, 21, 27, 39 14 23 56 58 61 63 105 Item Feature All items related the maximum rate of differential output clocks All items related waiting time after pwr_b pin goes high during reset procedure Section Section Table-5 Section Detailed Register Map Register synth0_post_div_C Register synth0_post_div_D Register synth1_post_div_C Register synth1_post_div_D DC Electrical Characteristics -Power Core DC Electrical Characteristics - High Performance Outputs Change OTP feature is added The maximum rate is updated from 720 MHz to 750MHz Waiting time after pwr_b pin goes high is changed from 30 ms to 50 ms Updated for OTP feature • Section and are updated for three configuration methods:Default configuration, OTP configuration, and SPI/I2C configuration • Original section and are changed to section and For page_register at address 0x7F, there is no waiting time required between two write accesses. • Table description is updated for OTP feature • Register 0x01, 0x0E and 0x0F are added • Heading of first column is changed from “Page_Addr” to “Reg_Addr" Detailed description for new register 0x01, 0x0E, and 0x0F are added "Page_Address" is changed to "Register_Address" for registers which addresses are from 0x80 to 0x91 Bit[15:0] note added for odd post divider Bit[15:0] note added for odd post divider Bit[15:0] note added for odd post divider Bit[15:0] note added for odd post divider • "Power for Each Synthesis Engine” is changed to “Current for Each Synthesis Engine” • “PSYN” is changed to “ISYN” Note added for differential output voltage when differential frequency is higher than 720MHz Microsemi Corporation Page 105 115 Item DC Electrical Characteristics Output Clocks Jitter Generation 116 Section ZL30230 Data Sheet Page Item 1 Ordering Information 115 Section 116 Section 110 Section Change Corrected package description in ordering information to LBGA. Section name was renamed to "Output Clocks RMS Jitter Generation". Table 12 was created for cycle-to-cycle jitter generation. Replaced drawing to reflect correct package description. Below are the changes from the November 2010 issue to the January 2011 issue. Page 6 10 25 27 98 104 Item Figure 2 Table 1 Serial Peripheral Interface Figure 17 Table - Recommended Operating Conditions Table - AC Electrical Characteristics - Outputs Table - AC Electrical Characteristics* - Outputs Change Names of pin B5, B6, H5, and H6 are changed from AVcore to Vcore Names of pin B5, B6, H5, and H6 are changed from AVcore to Vcore, and they are merged to the same entry with pin D5, G5, and G6. Layout application note is referred SPI burst mode operation description is added Example of a Burst Mode Operation is added Row 2, AVcore is removed from the "Sym" column Row 3, clock duty cycle is changed from "43%-57%" to "45%-55%" Row 4, note "From 0.2AVDD-IO to 0.8AVDD-IO" is removed Microsemi Corporation Pin Diagram ZL30230 Data Sheet A hpdiff3_p avss filter1 avss hpdiff3_n avss filter1_ref avdd C hpdiff2_p hpdiff2_n avss gpio5 osco osci avss filter2 avss hpdiff7_p vcore vcore

PDF Datasheet Preview

• Generates clock signals at power-up per user defined custom OTP One Time Programmable configuration
• Dynamically configurable via SPI/I2C interface and volatile configuration registers
• Four independently programmable clock generators output any clock rate from 1 kHz to 750 MHz precision / 350 MHz general purpose
• Precision clock generators output clocks with jitter below ps RMS for 10 G PHYs
• General purpose clock generators output a wide range of digital bus clocks
• Operates from a single crystal resonator, clock oscillator or voltage controlled oscillator
• Supports programmable frequency offsets for clock margining or for use as a digitally controlled oscillator
• Eight LVPECL outputs max rate 750 MHz
• Four LVCMOS outputs max rate MHz

ZL30230 Four Channel Universal

Clock Generator

Data Sheet

March 2015
Ordering Information ZL30230GGG2 100 Pin LBGA* 11mmx11mm Trays
*Pb Free Tin/Silver/Copper -40oC to +85oC
• Eight outputs configurable as LVCMOS at or V, max rate160 MHz or LVDS/LVPECL/HCSL, max rate 350 MHz
• Timing for NPUs, FPGAs, Ethernet switches and PCIe switches
• Timing for 10 Gigabit CDRs, Rapid-IO, PCIe, Serial MII, Star Fabric, Fibre Channel, XAUI
• Processor clock, Processor bus clock, SDRAM clock, DDR clock

Figure 1 - Functional Block Diagram

Copyright 2015, Microsemi Corporation. All Rights Reserved.

ZL30230

Data Sheet

Table of Contents

Pin Diagram 8

Pin Description. 9

Application Example 13

Functional Description 14 Frequency Synthesis Engine. 14 Dividers and Skew Management. 14 Output Multiplexer 15 Output Drivers 16 Programmable Single Ended Driver - Slew Rate Control 18 Master Clock Interface. 19 Clock Oscillator and Crystal Circuit 19 Power Up/Down Sequence 20 Power Supply Filtering. 20 Power on Reset and Initialization Circuit 21 Ultra Low Jitter Synthesizer Filter Components and Recommended Layout 22

Configuration and Control 23 Configuration Registers 23 Default Configuration 23 Custom OTP Configuration 23 SPI/I2C Configuration 23 Output Multiplexer Configuration and Programmability 23 Synthesizers Configuration and Programmability 23 Output Dividers and Skew Management Configuration and Programmability. 23 Output Drivers configuration and Programmability 23 GPIO Configuration and Programmability 24

Host Interface 27 Serial Peripheral Interface 27 Least Significant Bit LSB First Transmission Mode 28 Most Significant Bit MSB First Transmission Mode 28 SPI Burst Mode Operation 29 I2C Interface. 29

Register Map 31

Detailed Register Map 39

AC and DC Electrical Characteristics 105

Performance Characterization 115 Output Clocks RMS Jitter Generation 115 Output Clocks Cycle-to-Cycle Jitter Generation 116

Thermal Characteristics 116

Mechanical Drawing 117

Package Markings 118 100-pin BGA. Package Top Mark Format 118

Microsemi Corporation

ZL30230

Data Sheet

List of Figures

Figure 1 - Functional Block Diagram 1 Figure 2 - Package Description 8 Figure 3 - Application Diagram. 13 Figure 4 - Output Clock Muxing Configuration 15 Figure 5 - Terminating LVPECL Outputs 16 Figure 6 - Terminating AC coupled LVPECL Outputs 17 Figure 7 - Terminating LVCMOS Outputs 17 Figure 8 - Terminating LVDS Outputs 18 Figure 9 - Terminating HCSL Outputs 18 Figure 10 - Clock Oscillator Circuit. 19 Figure 11 - Typical Power-Up Reset and Configuration Circuit 21 Figure 12 - APLL Filter Component Values 22 Figure 13 - Recommended Layout for Loop Filters 22 Figure 14 - Serial Interface Configuration 27 Figure 15 - Serial Peripheral Interface Functional Waveforms - LSB First Mode 28 Figure 16 - Serial Peripheral Interface Functional Waveforms - MSB First Mode 28 Figure 17 - Example of a Burst Mode Operation 29 Figure 18 - I2C Data Write Protocol 29 Figure 19 - I2C Data Read Protocol. 29 Figure 20 - I2C 7-bit Slave Address 30 Figure 21 - I2C Data Write Burst Mode 30 Figure 22 - I2C Data Read Burst Mode 30 Figure 23 - Accessing Multi-byte Register Values 31 Figure 24 - Timing Parameter Measurement Voltage Levels. 110 Figure 25 - Output Timing Referenced To hpclkout0/clkout0. 111 Figure 26 - Serial Peripheral Interface Timing - LSB First Mode 112 Figure 27 - Serial Peripheral Interface Timing - MSB First Mode 113 Figure 28 - I2C Serial Microport Timing 114 Figure 29 - Non-customized Device Top Mark. 118 Figure 30 - Custom Factory Programmed Device Top Mark 118

Microsemi Corporation

ZL30230

Data Sheet

List of Tables

Table 1 - Pin Description 9 Table 2 - Slew Rate Control Limits Versus Output Clock Rise/Fall Times. 19 Table 3 - Master Clock Frequency Selection 20 Table 4 - Serial Interface Selection 27 Table 5 - Register Map 33 Table 6 - Serial Peripheral Interface Timing. 112 Table 7 - I2C Serial Microport Timing 114 Table 8 - Jitter Generation Specifications - HPDIFF Outputs 115 Table 9 - Jitter Generation Specifications - HPOUT Outputs. 115 Table 10 - Jitter Generation Specifications - Configurable Outputs driven from High Performance Synthesizers -

Differential Mode 115 Table 11 - Jitter Generation Specifications - Configurable Outputs driven from General Purpose Synthesizers -

Differential Mode 115 Table 12 - Jitter Generation Specifications - HPDIFF Outputs 116 Table 13 - Thermal Data 116 Table 14 - Package Marking Legend 118

Microsemi Corporation

ZL30230

Data Sheet

Change Summary

Below are the changes from the June 2012 issue to the March 2015 issue.
Page Item 1 Ordering Information
23 Custom OTP Configuration 118 “Package Markings“
Change Removed ZL30230GGG leaded version from the ordering information Removed reference to ZLAN-301

Added section 13 for package markings

Below are the changes from the January 2012 issue to the June 2012 issue.
36 and 91

Item Register 0xC6 - Chip_revision_2

Output to output alignment

Change Updated chip_revision to 0x03

Updated limits for tOUT2OUTD to +/- 1 ns

Below are the changes from the December 2011 issue to the January 2012 issue.

Page 31 32
39 36, 91

Item

Procedure for writing registers Reading from Sticky Read registers Time between two write accesses to the same register 0x00 - id_reg Register 0x0D - Sticky_r_lock Register 0xC6 - Chip_revision_2

Change Added a new procedure to update registers Updated Sticky read Procedure Changed wait time from 200ms to 8ms, added 0x0D as register not requiring wait time Updated chip_revision bits Updated Description Added register 0xC6

Below are the changes from the July 2011 issue to the December 2011 issue.

Page 32 39 87

Item Reading from Sticky Read registers Register 0x00 - id_reg Register 0x0D - sticky_r_lock Register 0xB7 - synth2_stop_clock
103 Register 0xF7 - spurs_suppression 117 Mechanical Drawing

Change Updated Sticky read Procedure updated ready_indication description added register Bits[3:2] - changed outclk2 to outclk1 Bits[5:4] - changed outclk3 to outclk2 updated spurs_suppression description repalced drawing to reflect correct package description

Microsemi Corporation

ZL30230

Data Sheet

Below are the changes from the June 2011 issue to the July 2011 issue.

Page 1,
9,14, 16, 23, 23, 111 9, 10, 20, 21, 27, 39 14 23
56 58 61 63 105

Item Feature All items related the maximum rate of differential output clocks

All items related waiting time after pwr_b pin goes high during reset procedure

Section

Section Table-5

Section Detailed Register Map Register synth0_post_div_C Register synth0_post_div_D Register synth1_post_div_C Register synth1_post_div_D DC Electrical Characteristics -Power Core DC Electrical Characteristics - High Performance Outputs

Change OTP feature is added The maximum rate is updated from 720 MHz to 750MHz

Waiting time after pwr_b pin goes high is changed from 30 ms to 50 ms

Updated for OTP feature
• Section and are
updated for three configuration methods:Default configuration, OTP configuration, and SPI/I2C configuration
• Original section and are changed to section and For page_register at address 0x7F, there is no waiting time required between two write accesses.
• Table description is updated for OTP feature
• Register 0x01, 0x0E and 0x0F are added
• Heading of first column is changed from “Page_Addr” to “Reg_Addr" Detailed description for new register 0x01, 0x0E, and 0x0F are added "Page_Address" is changed to "Register_Address" for registers which addresses are from 0x80 to 0x91 Bit[15:0] note added for odd post divider Bit[15:0] note added for odd post divider Bit[15:0] note added for odd post divider Bit[15:0] note added for odd post divider
• "Power for Each Synthesis Engine” is changed to “Current for Each Synthesis Engine”
• “PSYN” is changed to “ISYN” Note added for differential output voltage when differential frequency is higher than 720MHz

Microsemi Corporation

Page 105 115

Item DC Electrical Characteristics Output Clocks Jitter Generation
116 Section

ZL30230

Data Sheet
Page Item 1 Ordering Information
115 Section 116 Section 110 Section

Change
Corrected package description in ordering information to LBGA.

Section name was renamed to "Output Clocks RMS Jitter Generation".

Table 12 was created for cycle-to-cycle jitter generation.

Replaced drawing to reflect correct package description.

Below are the changes from the November 2010 issue to the January 2011 issue.

Page 6 10
25 27 98 104

Item Figure 2

Table 1

Serial Peripheral Interface Figure 17 Table - Recommended Operating Conditions Table - AC Electrical Characteristics* - Outputs Table - AC Electrical Characteristics* - Outputs

Change

Names of pin B5, B6, H5, and H6 are changed from AVcore to Vcore

Names of pin B5, B6, H5, and H6 are changed from AVcore to Vcore, and they are merged to the same entry with pin D5, G5, and G6. Layout application note is referred

SPI burst mode operation description is added

Example of a Burst Mode Operation is added

Row 2, AVcore is removed from the "Sym" column

Row 3, clock duty cycle is changed from "43%-57%" to "45%-55%"

Row 4, note "From 0.2AVDD-IO to 0.8AVDD-IO" is removed

Microsemi Corporation

Pin Diagram

ZL30230

Data Sheet

A hpdiff3_p
avss
filter1
avss
hpdiff3_n
avss
filter1_ref
avdd

C hpdiff2_p hpdiff2_n
avss
gpio5
osco
osci
avss
filter2
avss
hpdiff7_p
vcore
vcore

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Datasheet ID: ZL30230GGG20038 649214