ZL30159GGG20037
ZL30159GGG20037 Datasheet
ZL30159 General Purpose Clock Rate Converter
| Part | Datasheet |
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ZL30159GGG20037 |
ZL30159GGG20037 (pdf) |
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| ZL30159 General Purpose Clock Rate Converter Data Sheet • Precision synthesizer generates any clock-rate from 1 Hz to MHz with jitter below 1ps • Programmable digital PLL synchronize to any clock rate from 1 Hz 1 pps to 750 MHz • Input reference configurable as single ended LVCMOS up to MHz or differential LVPECL up to 750 MHz • Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates • Programmable Digital PLL loop filter 30 mHz, 14 Hz, 28 Hz, 56 Hz, 112 Hz, 224 Hz, 448 Hz or 896 Hz • Two LVCMOS outputs 1 Hz 1 pps to MHz • Operates from a single crystal resonator or clock oscillator March 2015 Ordering Information ZL30159GGG2 64 Pin LBGA* Trays *Pb Free Tin/Silver/Copper -40oC to +85oC • Customer defined default device configuration, including input/output frequencies, is available via OTP One Time Programmable memory • Dynamically configurable via SPI/I2C interface and volatile configuration registers • General purpose clock rate translator • GPS receiver clock synthesizer Figure 1 - Functional Block Diagram Copyright 2015, Microsemi Corporation. All Rights Reserved. ZL30159 Data Sheet Table of Contents Pin Diagram 6 Pin Description. 7 Application Example 11 Functional Description 12 Input Sources 12 Input Reference Monitoring 12 DPLL General Characteristics 14 DPLL States 15 DPLL Rate Conversion Function and FEC Support. 16 DPLL Input to Output And Output to Output Phase Alignment 16 Frequency Synthesis Engine. 17 Dividers and Skew Management. 17 Output Multiplexer 18 Output Drivers 18 Input Buffers 18 Master Clock Interface. 21 Clock Oscillator 21 Power Up/Down Sequence 22 Power Supply Filtering. 22 Reset and Configuration Circuit. 22 Ultra Low Jitter Synthesizer Filter Components and Recommended Layout 23 Configuration and Control 24 Custom OTP Configuration 24 GPIO Configuration and Programmability 24 Configuration Registers 26 Input Reference Configuration and Programmability 27 DPLL Configuration and Programmability 27 Synthesis Macro Configuration and Programmability 27 Output Dividers and Skew Management Configuration and Programmability 27 Output Drivers configuration and Programmability 27 State Control 27 Un-managed Mode 28 Managed Mode 28 Host Interface 29 Serial Peripheral Interface 29 Least Significant Bit LSB First Transmission Mode 30 Most Significant Bit MSB First Transmission Mode 30 SPI Burst Mode Operation 31 I2C Interface. 31 Register Map 33 Detailed Register Map 38 AC and DC Electrical Characteristics 73 Performance Characterization 80 Output Clocks Jitter Generation 80 DPLL Performance Characteristics 81 Thermal Characteristics 81 Package Markings 83 64-pin BGA. Package Top Mark Format 83 Microsemi Corporation ZL30159 Data Sheet List of Figures Figure 1 - Functional Block Diagram 1 Figure 2 - Application Diagram. 11 Figure 3 - Output Clocks Muxing Configuration 18 Figure 4 - Terminating HP LVCMOS Outputs 18 Figure 5 - Differential DC Coupled LVPECL Termination 19 Figure 6 - Differential AC Coupled LVPECL Termination 19 Figure 7 - Differential DC Coupled LVDS Termination. 20 Figure 8 - Differential AC Coupled LVDS Termination. 20 Figure 9 - Single Ended CMOS Termination 20 Figure 10 - Clock Oscillator Circuit. 21 Figure 11 - Typical Power-Up Reset and Configuration Circuit with MHz XO 22 Figure 12 - APLL Filter Component Values 23 Figure 13 - Recommended Layout for Loop Filters 23 Figure 14 - Serial Interface Configuration 29 Figure 15 - Serial Peripheral Interface Functional Waveforms - LSB First Mode 30 Figure 16 - Serial Peripheral Interface Functional Waveforms - MSB First Mode 30 Figure 17 - Example of a Burst Mode Operation 31 Figure 18 - I2C Data Write Protocol 31 Figure 19 - I2C Data Read Protocol. 31 Figure 20 - I2C 7-bit Slave Address 32 Figure 21 - I2C Data Write Burst Mode 32 Figure 22 - I2C Data Read Burst Mode 32 Figure 23 - Accessing Multi-byte Register Values 33 Figure 24 - Timing Parameter Measurement Voltage Levels. 75 Figure 25 - Input To Output Timing for hpoutclk0 76 Figure 26 - Output Timing Referenced To hpclkout0 77 Figure 27 - Serial Peripheral Interface Timing - LSB First Mode 78 Figure 28 - Serial Peripheral Interface Timing - MSB First Mode 79 Figure 29 - I2C Serial Microport Timing 80 Figure 30 - Non-customized Device Top Mark. 83 Figure 31 - Custom Factory Programmed Device Top Mark 83 Microsemi Corporation ZL30159 Data Sheet List of Tables Table 1 - Pin Description 7 Table 2 - Guard Soak Time To Disqualify A Reference 13 Table 3 - Guard Soak Time To Qualify A Reference 13 Table 4 - Master Clock Frequency Selection 22 Table 5 - Serial Interface Selection 29 Table 6 - Register Map 34 Table 7 - Serial Peripheral Interface Timing. 78 Table 8 - I2C Serial Microport Timing 79 Table 9 - Jitter Generation Specifications - HPOUT Outputs. 80 Table 10 - DPLL Characteristics 81 Table 11 - Thermal Data 81 Table 12 - Package Marking Legend 83 Microsemi Corporation Change Summary ZL30159 Data Sheet Below are the changes made May 2014 issue to March 2015 issue. Item Added Features bullet 12, 24, 24 Item Zarlink logo and name reference , “Ordering Information“ Change Updated to logo and name. Removed GGG part number. Microsemi Corporation Pin Diagram ZL30159 avss filter avss osco avss avdd filter_ref avdd osci avdd avss avcore avss avss avss avdd avdd vdd_io pwr_b E hpoutclk1 hpoutclk0 gpio5 vcore gpio0 cs_b_asel0 sck_scl F avss avdd test_en vcore vcore gpio3 gpio2 gpio1 gpio6 so_asel1 trst_b avcore avss avdd |
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