ZL30112LDG1
ZL30112LDG1 Datasheet
ZL30112 SLIC/CODEC DPLL
| Part | Datasheet |
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ZL30112LDG1 |
ZL30112LDG1 (pdf) |
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| ZL30112 SLIC/CODEC DPLL Data Sheet November 2009 • Synchronizes to 8 kHz, MHz, MHz or MHz input • Provides MHz and MHz output clocks and an 8 kHz framing pulse • Automatic entry and exit from freerun mode on reference fail Ordering Information ZL30112LDG1 32 Pin QFN* Trays, Bake & Drypack *Pb Free Matte Tin -40°C to +85°C • Provides DPLL lock and reference fail indication • DPLL bandwidth of 29 Hz for all rates of input references • Less than nsecpp intrinsic jitter on all output clocks • 20 MHz external master clock source clock oscillator or crystal • Simple hardware control interface The ZL30112 SLIC/CODEC DPLL contains a digital phase-locked loop DPLL , which provides timing and synchronization for SLIC/CODEC devices. The ZL30112 generates TDM clock and framing signals that are phase locked to the input reference. It helps ensure system reliability by monitoring its reference for stability and by maintaining stable output clocks during short periods when the reference is unavailable. • Synchronizer for POTS SLIC/CODEC • Rate convert NTR 8 kHz or GPON physical interface clock to TDM clock RST OSCi OSCo Reference Monitor State Machine Master Clock REF_FAIL LOCK DPLL Mode Control C2o C8o F8ko Figure 1 - Functional Block Diagram Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2007-2009, Zarlink Semiconductor Inc. All Rights Reserved. ZL30112 Data Sheet Change Summary Changes from November 2007 Issue. Page, section, figure and table numbers refer to this current issue. Page Item Ordering Information Change Updates to Ordering Information and Package Drawing. Zarlink Semiconductor Inc. ZL30112 Data Sheet Table of Contents Change Summary 2 Physical Description 6 Pin Connections 6 Pin Description. 7 Functional Description 9 Reference Monitor 9 Time Interval Error TIE Corrector Circuit. 10 Digital Phase Lock Loop DPLL 10 Frequency Synthesizers 11 Master Clock 11 Modes of Operation 12 Measures of Performance 12 Jitter Generation Intrinsic Jitter 12 Jitter Tolerance 12 Jitter Transfer 13 Freerun Accuracy 13 Capture Range 13 Lock Range 13 Time Interval Error TIE 13 Maximum Time Interval Error MTIE 13 Phase Continuity 13 Phase Lock Time. 14 Applications 14 Power Supply Decoupling 14 Master Clock 14 Clock Oscillator 14 Crystal Oscillator 15 Power Up Sequence 16 Reset Circuit 16 Characteristics 17 AC and DC Electrical Characteristics 17 Performance Characteristics 21 Zarlink Semiconductor Inc. ZL30112 Data Sheet List of Figures Figure 1 - Functional Block Diagram 1 Figure 2 - Pin Connections 32 pin 5 mm X 5 mm QFN 6 Figure 3 - Reference Monitor Circuit 9 Figure 4 - DPLL Block Diagram 10 Figure 5 - Modes of Operation 12 Figure 6 - Clock Oscillator Circuit. 15 Figure 7 - Crystal Oscillator Circuit 16 Figure 8 - Power-Up Reset Circuit 16 Figure 9 - Timing Parameter Measurement Voltage Levels. 18 Figure 10 - Output Timing Referenced to F8o 19 Figure 11 - Input to Output Timing 20 Zarlink Semiconductor Inc. ZL30112 Data Sheet List of Tables Table 1 - Typical Clock Oscillator Specification 14 Table 2 - Typical Crystal Oscillator Specification 15 Zarlink Semiconductor Inc. Physical Description Pin Connections ZL30112 Data Sheet C2o AVDD AGND C8o IC AVDD AVCORE AGND AGND F8ko REF IC VDD IC ZL30112 16 28 12 33 IC E-pad GND AVDD VDD IC OSCi OSCo RST IC GND VCORE LOCK REF_FAIL IC VCORE AVCORE Figure 2 - Pin Connections 32 pin 5 mm X 5 mm QFN Zarlink Semiconductor Inc. ZL30112 Data Sheet Pin Description |
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