MT9072AV2

MT9072AV2 Datasheet

MT9072 Octal T1/E1/J1 Framer

Part	Datasheet
MT9072AV2	MT9072AV2 (pdf)

Related Parts	Information
MT9072AV	MT9072AV

PDF Datasheet Preview
MT9072 Octal T1/E1/J1 Framer Data Sheet • Eight fully independent, T1/E1/J1 framers • V supply with 5 V tolerant inputs • Selectable Mbit/s or Mbit/s serial buses for both data and signaling • Framing Modes: - T1 D4, ESF, T1DM - E1 Basic Framing, CRC4 multiframing and Signaling Multiframing • Supports Inverse Mux for ATM • Timeslot assignable HDLC • IEEE-1149.1 JTAG test port • T1/E1/J1 add/drop multiplexers • V5.1 and V5.2 access network interfaces • CO and PBX equipment interfaces • Primary rate IDSN nodes August 2011 Ordering Information MT9072AV 220 Pin PBGA Trays MT9072AV2 220 Pin PBGA Trays Pb Free Tin/Silver/Copper -40C to +85C • Digital Cross-connect Systems DCS • Wireless base stations The MT9072 is a multi-port T1/E1/J1 framing device that integrates eight fully independent, feature rich framers. The device is software selectable between T1, E1 or J1 modes and meets the latest relevant recommendations and standards from Telcordia, ANSI, ETSI and ITU-T. An extensive suite of features make the MT9072 very flexible and suitable for a wide variety of applications around the globe. DSTi [0] CSTi [0] TxDL[0] TxDLC[0] TxCL [0] ST-BUS Interface Transmit Framing, Error and Test Signal Generation TPOS[0] TNEG[0] CKi[0] FPi[0] ST-BUS Loopback Payload Loopback ST-BUS Circuit Timing Data Link National Bit Buffer CAS Buffer Remote Loopback Digital Loopback DSTo[0] CSTo[0] ST-BUS Interface Receive Framing, Performance Monitoring, Alarm Detection, 2 Frame Slip Buffer RPOS[0] RNEG[0] FRAMER 0 RxDLC[0] RxDL[0] FRAMER 1 FRAMER 2 FRAMER 3 FRAMER 4 FRAMER 5 FRAMER 6 FRAMER 7 RxMF[0] RxBF[0] EXCLi[0] Microprocessor Interface IEEE TAP Common Control and Power D15~D0 A11~A0 DS RW CS IRQ IM TDI TDO TMS TCK TRST RESET TAIS VDD VSS T1-3 TxMF Figure 1 - Block Diagram Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Page Item 1 Ordering Information Change Obsoleted 208L LQFP package. Changes from March 2004 Issue to October 2004 Issue. Page 242 Item “Recommended Operating Conditions” Table. Change Corrected Min. value to Data Sheet Zarlink Semiconductor Inc. MT9072 Data Sheet MT9072 Detailed Feature Summary Standards Compliance and Support T1/J1 Mode ANSI T1.102, T1.231 T1.403, T1.408 AT&T TR 62411, PUB43801 Telcordia GR-303-CORE ITU-T G.802 TTC JT-G703, JT-G704 JT-G706 ETSI: E1 Mode TBR4, TBR13 ETS 300 233, ETS 300 347 V5.2 ITU-T G.703, G.704, G.706, G.711, G.732 G.775, G.796, G.823, I.431 G.965 V5.2 Access and Control • A 16-bit parallel Motorola or Intel non-multiplexed microprocessor interface is used to access the control and status registers Backplane Interfaces • Mbit/s or Mbit/s ST-BUS • Mbit/s GCI bus • IMA Inverse Mux for ATM mode, Mbit/s T1 or Mbit/s E1 serial bus with asynchronous transmit and receive timing for Inverse MUX for ATM applications. • CSTo/CSTi pins can be used to access the receive/transmit signaling data • RxDL pin can be used to access the entire B8ZS/HDB3 decoded receive stream including framing bits • TxDL pin can be used to transmit data on the FDL T1 or the Sa bits E1 T1/J1 Mode • PCM24 channels 1-24 are mapped to ST-BUS channels 0-23 respectively • The framing-bit is mapped to ST-BUS channel 31 E1 Mode • PCM30 timeslots 0-31 are mapped to ST-BUS channels 0-31 respectively Zarlink Semiconductor Inc. MT9072 Data Sheet Data Link T1/J1 Mode • Three methods are provided to access the datalink: TxDL and RxDL pins support transmit and receive datalinks Bit Oriented Messages are supported via internal registers An internal HDLC can be assigned to transmit/receive over the FDL in ESF mode E1 Mode • Two methods are provided to access the datalink: TxDL and RxDL pins support transmit and receive datalinks over the Sa4~Sa8 bits An internal HDLC can be assigned to transmit/receive data via the Sa4~Sa8 bits

PDF Datasheet Preview

MT9072 Octal T1/E1/J1 Framer

Data Sheet
• Eight fully independent, T1/E1/J1 framers
• V supply with 5 V tolerant inputs
• Selectable Mbit/s or Mbit/s serial
buses for both data and signaling
• Framing Modes:
- T1 D4, ESF, T1DM - E1 Basic Framing, CRC4 multiframing and

Signaling Multiframing
• Supports Inverse Mux for ATM
• Timeslot assignable HDLC
• IEEE-1149.1 JTAG test port
• T1/E1/J1 add/drop multiplexers
• V5.1 and V5.2 access network interfaces
• CO and PBX equipment interfaces
• Primary rate IDSN nodes

August 2011
Ordering Information

MT9072AV 220 Pin PBGA Trays MT9072AV2 220 Pin PBGA** Trays
**Pb Free Tin/Silver/Copper -40C to +85C
• Digital Cross-connect Systems DCS
• Wireless base stations

The MT9072 is a multi-port T1/E1/J1 framing device that integrates eight fully independent, feature rich framers. The device is software selectable between T1, E1 or J1 modes and meets the latest relevant recommendations and standards from Telcordia, ANSI, ETSI and ITU-T. An extensive suite of features make the MT9072 very flexible and suitable for a wide variety of applications around the globe.

DSTi [0] CSTi [0]

TxDL[0] TxDLC[0]

TxCL [0]

ST-BUS Interface

Transmit Framing, Error and Test Signal Generation

TPOS[0] TNEG[0]

CKi[0] FPi[0]

ST-BUS Loopback

Payload Loopback

ST-BUS

Circuit Timing

Data Link

National Bit Buffer

CAS Buffer

Remote Loopback Digital Loopback

DSTo[0] CSTo[0]

ST-BUS Interface

Receive Framing, Performance Monitoring, Alarm Detection, 2 Frame Slip Buffer

RPOS[0] RNEG[0]

FRAMER 0

RxDLC[0] RxDL[0]

FRAMER 1

FRAMER 2

FRAMER 3

FRAMER 4

FRAMER 5

FRAMER 6

FRAMER 7

RxMF[0]

RxBF[0] EXCLi[0]

Microprocessor Interface

IEEE TAP

Common Control and Power

D15~D0 A11~A0 DS RW CS IRQ IM TDI TDO TMS TCK TRST RESET TAIS VDD VSS T1-3 TxMF

Figure 1 - Block Diagram

Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Page Item 1 Ordering Information

Change Obsoleted 208L LQFP package.

Changes from March 2004 Issue to October 2004 Issue.

Page 242

Item
“Recommended Operating Conditions” Table.

Change Corrected Min. value to

Data Sheet

Zarlink Semiconductor Inc.

MT9072

Data Sheet

MT9072 Detailed Feature Summary

Standards Compliance and Support T1/J1 Mode

ANSI T1.102, T1.231 T1.403, T1.408 AT&T TR 62411, PUB43801 Telcordia GR-303-CORE ITU-T G.802 TTC JT-G703, JT-G704 JT-G706

ETSI:

E1 Mode

TBR4, TBR13

ETS 300 233, ETS 300 347 V5.2

ITU-T G.703, G.704, G.706, G.711, G.732 G.775, G.796, G.823, I.431 G.965 V5.2

Access and Control
• A 16-bit parallel Motorola or Intel non-multiplexed microprocessor interface is used to access the control and
status registers

Backplane Interfaces
• Mbit/s or Mbit/s ST-BUS
• Mbit/s GCI bus
• IMA Inverse Mux for ATM mode, Mbit/s T1 or Mbit/s E1 serial bus with asynchronous
transmit and receive timing for Inverse MUX for ATM applications.
• CSTo/CSTi pins can be used to access the receive/transmit signaling data
• RxDL pin can be used to access the entire B8ZS/HDB3 decoded receive stream including framing bits
• TxDL pin can be used to transmit data on the FDL T1 or the Sa bits E1

T1/J1 Mode
• PCM24 channels 1-24 are mapped to ST-BUS channels 0-23 respectively
• The framing-bit is mapped to ST-BUS channel 31

E1 Mode
• PCM30 timeslots 0-31 are mapped to ST-BUS channels 0-31 respectively

Zarlink Semiconductor Inc.

MT9072

Data Sheet

Data Link

T1/J1 Mode
• Three methods are provided to access the datalink:

TxDL and RxDL pins support transmit and receive datalinks

Bit Oriented Messages are supported via internal registers

An internal HDLC can be assigned to transmit/receive over the FDL in ESF mode

E1 Mode
• Two methods are provided to access the datalink:

TxDL and RxDL pins support transmit and receive datalinks over the Sa4~Sa8 bits

An internal HDLC can be assigned to transmit/receive data via the Sa4~Sa8 bits

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MT9072AV2 Datasheet file may be downloaded here without warranties.

Datasheet ID: MT9072AV2 649084