MT093AE1

MT093AE1 Datasheet

ISO-CMOS MT093 8 x 12 Analog Switch Array

Part	Datasheet
MT093AE1	MT093AE1 (pdf)

Related Parts	Information
MT093APR1	MT093APR1
MT093AP1	MT093AP1

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• Internal control latches and address decoder • Short set-up and hold times • Wide operating voltage V to V • 3.5Vpp analog signal capability • RON 65 VDD=14V, 25C • 10 VDD=14V, 25C • Full CMOS switch for low distortion • Minimum feedthrough and crosstalk • Low power consumption ISO-CMOS technology • PBX systems • Mobile radio • Test equipment /instrumentation • Analog/digital multiplexers • Audio/Video switching ISO-CMOS MT093 8 x 12 Analog Switch Array Data Sheet September 2011 Ordering Information MT093AE1 MT093AP1 MT093APR1 40 Pin PDIP* 44 Pin PLCC* 44 Pin PLCC* Tubes *Pb Free Matte Tin 0C to +70C The Zarlink MT093 is fabricated in Zarlink’s ISOCMOS technology providing low power dissipation and high reliability. The device contains a 8x12 array of crosspoint switches along with a 7 to 96 line decoder and latch circuits. Any one of the 96 switches can be addressed by selecting the appropriate seven input bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input. STROBE DATA RESET 7 to 96 Decoder Latches 8 x 12 Switch Array Xi I/O i=0-11 Yi I/O i=0-7 Figure 1 - Functional Block Diagram Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved. MT093 Data Sheet NC AX0 AX3 RESET AY2 Y3 VDD Y2 DATA Y1 Y0 Y3 1 AY2 2 RESET 3 AX3 4 AX0 5 NC 6 NC 7 X6 8 X7 9 X8 10 X9 11 X10 12 X11 13 NC 14 Y7 15 NC 16 Y6 17 STROBE 18 Y5 19 VSS 20 40 VDD 39 Y2 38 DATA 37 Y1 36 NC 35 Y0 34 NC 33 X0 32 X1 31 X2 30 X3 29 X4 28 X5 27 NC 26 NC 25 AY1 24 AY0 23 AX2 22 AX1 21 Y4 40 PIN PLASTIC DIP 6 5 4 3 2 1 44 43 42 41 40 39 NC 38 NC 37 X0 XY 10 36 X1 X8 11 35 X2 X9 12 34 X3 X10 13 33 X4 X11 14 32 X5 Item Ordering Information Change Removed leaded packages as per PCN notice. Pin Description Pin # PDIP 1 PLCC 1 2 3 4,5 6,7 8-13 2 3 4,5 6-8 9-14 14 15-17 Name Y3 Analog Input/Output this is connected to the Y3 column of the switch array. AY2 Y2 Address Line Input . RESET Master RESET Input this is used to turn off all switches. Active High. AX3,AX0 X3 and X0 Address Lines Inputs . NC No Connection. X6-X11 X6-X11 Analog Inputs/Outputs these are connected to the X6-X11 rows of the switch array. NC No Connection. Y7 Analog Input/Output this is connected to the Y7 column of the switch array. NC No Connection. Y6 Analog Input/Output this is connected to the Y6 column of the switch array. Zarlink Semiconductor Inc. MT093 Data Sheet Pin Description Pin # PDIP 18 PLCC 20 22, 23 24, 25 26, 27 28 - 33 24,25 26,27 28-31 32-37 34 38,39 Name STROBE Input enables function selected by address and data. Address must be stable before STROBE goes high and DATA must be stable on the falling edge of the STROBE. Active High. Y5 Analog Input/Output this is connected to the Y5 column of the switch array. VSS Ground Reference. Y4 Analog Input/Output this is connected to the Y4 column of the switch array. AX1,AX2 X1 and X2 Address Lines Inputs . AY0,AY1 Y0 and Y1 Address Lines Inputs . NC No Connection. X5-X0 X5-X0 Analog Inputs/Outputs these are connected to the X5-X0 rows of the switch array. NC No Connection. Y0 Analog Input/Output this is connected to the Y0 column of the switch array. NC No Connection. Y1 Analog Input/Output this is connected to the Y1 column of the switch array. DATA Input a logic high input will turn on the selected switch and a logic low will turn off the selected switch. Active High. Y2 Analog Input/Output this is connected to the Y2 column of the switch array. VDD Positive Power Supply. Functional Description The MT093 is an analog switch matrix with an array size of 8 x The switch array is arranged such that there are 8 columns by 12 rows. The columns are referred to as the Y input/output lines and the rows are the X input/output lines. The crosspoint analog switch array will interconnect any X line with any Y line when turned on and provide a high degree of isolation when turned off. The control memory consists of a 96 bit write only RAM in which the bits are selected by the address input lines AY0-AY2, AX0-AX3 . Data is presented to the memory on the DATA input line. Data is asynchronously written into memory whenever the STROBE input is high and is latched on the falling edge of STROBE. A logical “1” written into a memory cell turns the corresponding crosspoint switch on and a logical “0” turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memory. The remaining switches retain their previous states. Any combination of X and Y lines can be interconnected by establishing appropriate patterns in the control memory. A logical “1” on the RESET input line will asynchronously return all memory locations to logical “0” turning off all crosspoint switches. Address Decode The seven address lines along with the STROBE input are logically ANDed to form an enable signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a location, RESET must be low while the address and data lines are set up. Then the STROBE input is set high and then low causing the data to be latched. The data can be changed while STROBE is high, however, the corresponding switch will turn on and off in accordance with the data. Data must be stable on the falling edge of STROBE in order for correct data to be written to the latch. Zarlink Semiconductor Inc. MT093 Data Sheet

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• Internal control latches and address decoder
• Short set-up and hold times
• Wide operating voltage V to V
• 3.5Vpp analog signal capability
• RON 65 VDD=14V, 25C
• 10 VDD=14V, 25C
• Full CMOS switch for low distortion
• Minimum feedthrough and crosstalk
• Low power consumption ISO-CMOS technology
• PBX systems
• Mobile radio
• Test equipment /instrumentation
• Analog/digital multiplexers
• Audio/Video switching

ISO-CMOS MT093 8 x 12 Analog Switch Array

Data Sheet

September 2011
Ordering Information

MT093AE1 MT093AP1 MT093APR1
40 Pin PDIP* 44 Pin PLCC* 44 Pin PLCC*

Tubes
*Pb Free Matte Tin 0C to +70C

The Zarlink MT093 is fabricated in Zarlink’s ISOCMOS technology providing low power dissipation and high reliability. The device contains a 8x12 array of crosspoint switches along with a 7 to 96 line decoder and latch circuits. Any one of the 96 switches can be addressed by selecting the appropriate seven input bits. The selected switch can be turned on or off by applying a logical one or zero to the DATA input.

STROBE

DATA RESET
7 to 96 Decoder

Latches
8 x 12 Switch Array

Xi I/O i=0-11

Yi I/O i=0-7

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved.

MT093

Data Sheet

NC AX0 AX3 RESET AY2 Y3 VDD Y2 DATA Y1 Y0

Y3 1 AY2 2 RESET 3 AX3 4 AX0 5

NC 6 NC 7 X6 8 X7 9 X8 10 X9 11 X10 12 X11 13 NC 14 Y7 15 NC 16 Y6 17 STROBE 18

Y5 19 VSS 20
40 VDD 39 Y2 38 DATA 37 Y1
36 NC
35 Y0 34 NC 33 X0 32 X1 31 X2 30 X3 29 X4 28 X5 27 NC 26 NC 25 AY1 24 AY0 23 AX2
22 AX1 21 Y4
40 PIN PLASTIC DIP
6 5 4 3 2 1 44 43 42 41 40
39 NC
38 NC
37 X0

XY 10
36 X1

X8 11
35 X2

X9 12
34 X3

X10 13
33 X4

X11 14
32 X5
Item Ordering Information

Change Removed leaded packages as per PCN notice.

Pin Description

Pin #

PDIP 1

PLCC 1
2 3 4,5 6,7 8-13
2 3 4,5 6-8 9-14
14 15-17

Name

Y3 Analog Input/Output this is connected to the Y3 column of the switch array.

AY2 Y2 Address Line Input . RESET Master RESET Input this is used to turn off all switches. Active High. AX3,AX0 X3 and X0 Address Lines Inputs .

NC No Connection. X6-X11 X6-X11 Analog Inputs/Outputs these are connected to the X6-X11 rows of the
switch array. NC No Connection. Y7 Analog Input/Output this is connected to the Y7 column of the switch
array. NC No Connection. Y6 Analog Input/Output this is connected to the Y6 column of the switch
array.

Zarlink Semiconductor Inc.

MT093

Data Sheet

Pin Description

Pin #

PDIP 18

PLCC 20
22, 23 24, 25 26, 27 28 - 33
24,25 26,27 28-31 32-37
34 38,39

Name

STROBE Input enables function selected by address and data. Address must be stable before STROBE goes high and DATA must be stable on the falling edge of the STROBE. Active High.

Y5 Analog Input/Output this is connected to the Y5 column of the switch array.

VSS Ground Reference. Y4 Analog Input/Output this is connected to the Y4 column of the switch
array. AX1,AX2 X1 and X2 Address Lines Inputs . AY0,AY1 Y0 and Y1 Address Lines Inputs .

NC No Connection. X5-X0 X5-X0 Analog Inputs/Outputs these are connected to the X5-X0 rows of the
switch array. NC No Connection. Y0 Analog Input/Output this is connected to the Y0 column of the switch array. NC No Connection. Y1 Analog Input/Output this is connected to the Y1 column of the switch array. DATA Input a logic high input will turn on the selected switch and a logic low will
turn off the selected switch. Active High. Y2 Analog Input/Output this is connected to the Y2 column of the switch array. VDD Positive Power Supply.

Functional Description

The MT093 is an analog switch matrix with an array size of 8 x The switch array is arranged such that there are 8 columns by 12 rows. The columns are referred to as the Y input/output lines and the rows are the X input/output lines. The crosspoint analog switch array will interconnect any X line with any Y line when turned on and provide a high degree of isolation when turned off. The control memory consists of a 96 bit write only RAM in which the bits are selected by the address input lines AY0-AY2, AX0-AX3 . Data is presented to the memory on the DATA input line. Data is asynchronously written into memory whenever the STROBE input is high and is latched on the falling edge of STROBE. A logical “1” written into a memory cell turns the corresponding crosspoint switch on and a logical “0” turns the crosspoint off. Only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memory. The remaining switches retain their previous states. Any combination of X and Y lines can be interconnected by establishing appropriate patterns in the control memory. A logical “1” on the RESET input line will asynchronously return all memory locations to logical “0” turning off all crosspoint switches.

Address Decode

The seven address lines along with the STROBE input are logically ANDed to form an enable signal for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to a location, RESET must be low while the address and data lines are set up. Then the STROBE input is set high and then low causing the data to be latched. The data can be changed while STROBE is high, however, the corresponding switch will turn on and off in accordance with the data. Data must be stable on the falling edge of STROBE in order for correct data to be written to the latch.

Zarlink Semiconductor Inc.

MT093

Data Sheet

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Datasheet ID: MT093AE1 649079