LX8233ILQ-TR

LX8233ILQ-TR Datasheet

LX8233

Part	Datasheet
LX8233ILQ-TR	LX8233ILQ-TR (pdf)

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LX8233 2.5A 5V E-Fuse with Bi-Directional Protection Switch and DevSleep/Disable Mode Voltage protection features include under-voltage lockout UVLO , and over-voltage clamping. This clamp limits VOUT voltage allowing continued circuit operation during an input over-voltage transient condition, while UVLO ensures that VOUT remains off until VCC reaches its minimum operating threshold. On the current side, the LX8233 protects the input from a output short circuit and/or over current condtion with a 2.5A current limit circuit. Another protection feature is latching thermal shutdown of VOUT, with a fault flag output on the combined EN/FAULT pin. Once thermal shutdown threshold is reached and the eFuse switch opens, the tristate EN/FAULT pin will be pulled to about 1.6V signaling to the system and potentially other connected eFuse switches that a fault has occurred. The LX8233 latches at this level until reset by the Enable pin, DEVSLP pin, or there is a VCC power recycle. At device power up the user can initialize the DevSleep pin functionality and VOUT slew rate in one of two modes depending on the state of the FET_ON pin. In DevSleep Disabled Mode the slew rate is set to 13ms, and VOUT shutdown is engaged when the DEVSLP pin is toggled high regardless of the state of the FET_ON pin. In DevSleep Enabled Mode the slew rate is reduced to 1.4ms, and shutdown is engaged when the DEVSLP pin is toggled high and the FET_ON pin is low. • typ. Rdson Internal eFuse FET Protected From 15V • Bi-directional Current Blocking Switch • SATA DevSleep Support • SAS-DISABLE Support • Up to 15V Transient Input Range • 6V Output Voltage Clamp • Continuous Operation During VCC surge • Current Limit at Overload and Short-Circuit Protection • Over-Temperature Protection • Selectable Soft-start 13ms or 1.4ms Risetime • UVLO Detection • VQFN 2mm x 3mm 13L Package • Hard-Disk Drive • Solid-State Drive • Hot Swap • PC Cards 2014 Microsemi Corporation 2.5A 5V E-Fuse with Bi-Directional Protection Switch and DevSleep/Disable Mode HOST +12V VOUT RT EN/FAULT 12V E-Fuse +5V DEVSLP 1µF LX8233 DEVSLP VOUT EN/FAULT DEVSLPOUTB FET_ON 5V Bus 30µF DevSleep Enabled Mode VCC_12V VCC_5V SOC/ V1P8 PMIC DEVSLPOUTB FET_ON Figure 1 • Typical Application of LX8233, DevSleep Enable Mode HOST +12V VOUT RT EN/FAULT 12V E-Fuse +5V DEVSLP VCC 1µF LX8233 DEVSLP VOUT EN/FAULT DEVSLPOUTB FET_ON 5V Bus 30µF DevSleep Disabled Mode Ordering Information Ambient Temperature Type Package -40°C to 85°C RoHS Compliant, Pb-free VQFN 2mm x 3mm 13L LX8233ILQ-TR Packaging Type Bulk / Tube Tape and Reel 2.5A 5V E-Fuse with Bi-Directional Protection Switch and DevSleep/Disable Mode Pin Description Pin Number Pin Designator 1, 2, 3 Input/ Output Input DEVSLP Input Input of the device. DevSleep mode input. There are two modes for the usage of DEVSLP. One operational mode is DEVSLP Enable Mode. It is selected by connecting the FET_ON pin of LX8233 to SOC during power on initalization. In this mode, only when FET_ON is low will setting DEVSLP high shut down the LX8233. This handshake feature allows the SOC to override the shutdown process initiated by the host using DevSleep allowing any necessary housekeeping functions to complete before powering off the switch. When in this mode the VOUT softstart time is programmed to ms. The other mode is DEVSLP Disabled Mode. This is selected by letting FET_ON pin float during power on initalization. In this mode the LX8233 will shutdown by setting DEVSLP high regardless of the FET_ON state. When in this mode the VOUT softstart time is programmed to 13 ms. The two mode are summarized in the table below. FET_ON TRISE Shutdown DEVSLP Disabled Float ~13ms DEVSLP High DEVSLP Enabled Connected to SOC ~1.4ms DEVSLP High AND FET_ON Low 5 6 7 8 9, 10, 11 EN/FAULT Input/Output FET_ON Input DEVSLPOUTB Output VOUT Output The EN/FAULT pin is a tri−state, bidirectional interface. It can be used to disable the output of the device by pulling it to ground using an open drain or open collector device. If a thermal fault occurs, the voltage on this pin will go to an intermediate state ~1.6V to signal a monitoring circuit that the device is in thermal shutdown. It can also be connected to another device in this family to cause a simultaneous shutdown during thermal events. See simplified schematic in Theory of Operation/ Application section. Ground Pin 6 and Pin 13 are internally connected . DEVSLP mode is configured by the FET_ON state during power on initializaiton. When FET_ON is floating 50pf maximum pin capacitance , the LX8233 is set to DEVSLP Disabled Mode. In this mode, the LX8233 can be shut down by setting the DEVSLP pin high. When FET_ON is connected to SOC, the LX8233 can only be shut down by setting both DEVSLP high and FET_ON low. Open-drain output. A pull-up resistor is connected to the I/O supply of SOC. DEVSLPOUTB is the inversed polarity version of DEVSLP.

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LX8233
2.5A 5V E-Fuse with Bi-Directional Protection Switch and DevSleep/Disable Mode

Voltage protection features include under-voltage lockout UVLO , and over-voltage clamping. This clamp limits VOUT voltage allowing continued circuit operation during an input over-voltage transient condition, while UVLO ensures that VOUT remains off until VCC reaches its minimum operating threshold. On the current side, the LX8233 protects the input from a output short circuit and/or over current condtion with a 2.5A current limit circuit.

Another protection feature is latching thermal shutdown of VOUT, with a fault flag output on the combined EN/FAULT pin. Once thermal shutdown threshold is reached and the eFuse switch opens, the tristate EN/FAULT pin will be pulled to about 1.6V signaling to the system and potentially other connected eFuse switches that a fault has occurred. The LX8233 latches at this level until reset by the Enable pin, DEVSLP pin, or there is a VCC power recycle.

At device power up the user can initialize the DevSleep pin functionality and VOUT slew rate in one of two modes depending on the state of the FET_ON pin. In DevSleep Disabled Mode the slew rate is set to 13ms, and VOUT shutdown is engaged when the DEVSLP pin is toggled high regardless of the state of the FET_ON pin. In DevSleep Enabled Mode the slew rate is reduced to 1.4ms, and shutdown is engaged when the DEVSLP pin is toggled high and the FET_ON pin is low.
• typ. Rdson Internal eFuse FET Protected From 15V
• Bi-directional Current Blocking Switch
• SATA DevSleep Support
• SAS-DISABLE Support
• Up to 15V Transient Input Range
• 6V Output Voltage Clamp
• Continuous Operation During VCC surge
• Current Limit at Overload and Short-Circuit

Protection
• Over-Temperature Protection
• Selectable Soft-start 13ms or 1.4ms

Risetime
• UVLO Detection
• VQFN 2mm x 3mm 13L Package
• Hard-Disk Drive
• Solid-State Drive
• Hot Swap
• PC Cards
2014 Microsemi Corporation
2.5A 5V E-Fuse with Bi-Directional Protection Switch and DevSleep/Disable Mode

HOST +12V

VOUT

RT EN/FAULT 12V E-Fuse
+5V DEVSLP
1µF

LX8233

DEVSLP

VOUT

EN/FAULT

DEVSLPOUTB FET_ON
5V Bus 30µF

DevSleep Enabled Mode

VCC_12V

VCC_5V SOC/

V1P8 PMIC

DEVSLPOUTB FET_ON

Figure 1
• Typical Application of LX8233, DevSleep Enable Mode

HOST +12V

VOUT

RT EN/FAULT 12V E-Fuse
+5V DEVSLP

VCC 1µF

LX8233

DEVSLP

VOUT

EN/FAULT

DEVSLPOUTB FET_ON
5V Bus 30µF

DevSleep Disabled Mode
Ordering Information

Ambient Temperature

Type

Package
-40°C to 85°C

RoHS Compliant, Pb-free

VQFN 2mm x 3mm 13L

LX8233ILQ-TR

Packaging Type

Bulk / Tube Tape and Reel
2.5A 5V E-Fuse with Bi-Directional Protection Switch and DevSleep/Disable Mode

Pin Description

Pin Number

Pin Designator
1, 2, 3

Input/ Output

Input

DEVSLP

Input

Input of the device.

DevSleep mode input. There are two modes for the usage of DEVSLP.

One operational mode is DEVSLP Enable Mode. It is selected by connecting the FET_ON pin of LX8233 to SOC during power on initalization. In this mode, only when FET_ON is low will setting DEVSLP high shut down the LX8233. This handshake feature allows the SOC to override the shutdown process initiated by the host using DevSleep allowing any necessary housekeeping functions to complete before powering off the switch. When in this mode the VOUT softstart time is programmed to ms.

The other mode is DEVSLP Disabled Mode. This is selected by letting FET_ON pin float during power on initalization. In this mode the LX8233 will shutdown by setting DEVSLP high regardless of the FET_ON state. When in this mode the VOUT softstart time is programmed to 13 ms.

The two mode are summarized in the table below.

FET_ON TRISE

Shutdown

DEVSLP Disabled Float ~13ms

DEVSLP High

DEVSLP Enabled Connected to SOC
~1.4ms DEVSLP High AND FET_ON Low
5 6 7 8 9, 10, 11

EN/FAULT Input/Output

FET_ON

Input

DEVSLPOUTB Output

VOUT

Output

The EN/FAULT pin is a tri−state, bidirectional interface. It can be used to disable the output of the device by pulling it to ground using an open drain or open collector device. If a thermal fault occurs, the voltage on this pin will go to an intermediate state ~1.6V to signal a monitoring circuit that the device is in thermal shutdown. It can also be connected to another device in this family to cause a simultaneous shutdown during thermal events. See simplified schematic in Theory of Operation/ Application section.

Ground Pin 6 and Pin 13 are internally connected .

DEVSLP mode is configured by the FET_ON state during power on initializaiton. When FET_ON is floating 50pf maximum pin capacitance , the LX8233 is set to DEVSLP Disabled Mode. In this mode, the LX8233 can be shut down by setting the DEVSLP pin high. When FET_ON is connected to SOC, the LX8233 can only be shut down by setting both DEVSLP high and FET_ON low.

Open-drain output. A pull-up resistor is connected to the I/O supply of SOC. DEVSLPOUTB is the inversed polarity version of DEVSLP.

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Datasheet ID: LX8233ILQ-TR 649033