CORE1553BBC-AR

CORE1553BBC-AR Datasheet

Core1553BBC MIL-STD-1553B Bus Controller

Part	Datasheet
CORE1553BBC-AR	CORE1553BBC-AR (pdf)

Related Parts	Information
CORE1553-SA	CORE1553-SA
CORE1553BBC-AN	CORE1553BBC-AN

PDF Datasheet Preview
Core1553BBC MIL-STD-1553B Bus Controller Product Summary Intended Use • 1553B Bus Controller BC • DMA Backend Interface to External Memory Key Features • Supports MIL-STD-1553B • Interfaces to External RAM Supports up to 128kbytes of Memory Synchronous or Asynchronous Backend Interface Backend Interface Identical to Core1553BRT • Selectable Clock Rate of 12, 16, 20, or 24 MHz • Provides Direct CPU Access to Memory • Interfaces to Standard 1553B Transceivers • Fully Automated Message Scheduling Frame Support Conditional Branching and Sub-routines Variable Inter-message Gaps and RT Response Times Real Time Clock for Message Scheduling Asynchronous Message Support Supported Families • Fusion • ProASIC3/E • ProASICPLUS • Axcelerator • RTAX • SX-A • RTSX-S Core Deliverables • Netlist Version Compiled RTL Simulation Model, Compliant with the Actel Libero Integrated Design Environment IDE Compatible with the Actel Designer Place-andRoute Tool • RTL Version VHDL or Verilog Core Source Code Synthesis Scripts • Actel-Developed Testbenches, VHDL and Verilog Synthesis and Simulation Support • Synthesis Design FPGA CompilerTM/FPGA ExpressTM , ExemplarTM • Simulation Vital-Compliant VHDL Simulators and OVI-Compliant Verilog Simulators Verification and Compliance • Actel-Developed Simulation Testbench • Core Implemented on the 1553B BC Development System • Third-Party 1553B Compliance Testing of the 1553B Encoder and Decoder Blocks Implemented in an A54SXA32-STD Device Development System Optional • Complete 1553B BC Implementation in an SX-A Device • Includes a PCI Interface for Host CPU Connection • Includes Transceivers and Bus Termination Components Contents General Description 2 Core1553BBC Device Requirements 4 Core1553BBC Verification and Compliance 4 MIL-STD-1553B Bus Overview 4 I/O Signal Descriptions 6 Bus Transceivers 20 Development System 20 Typical BC System 22 Specifications 24 Ordering Information 28 List of Changes 29 Datasheet Categories 29 December 2005 v4.0 2005 Actel Corporation Core1553BBC MIL-STD-1553B Bus Controller The Core1553BBC provides a complete, MIL-STD-1553B Bus Controller BC . A typical system implementation using the Core1553BBC is shown in Figure Core1553BBC reads message descriptor blocks from the memory and generates messages that are transmitted on the 1553B bus. Data words are read from the memory and transmitted on the 1553B bus. Data received is written to the memory. The core can be configured directly to connect to synchronous or asynchronous memory devices. The core consists of five main blocks the 1553B encoder, the 1553B decoder, a protocol controller block, a CPU interface, and a backend interface Figure Backend Interface Memory CPU Glue Logic CPU Interface BUSAINEN BUSAINP BUSAINN BUSAOUTINH BUSAOUTP BUSAOUTN BUSBINEN BUSBINP BUSBIN BUSAOUTINH BUSBOUTP BUSBOUTN Core1553BBC Figure 1 • Typical Core1553BBC System Actel FPGA RCVSTBA RXDAIN TXINHA TXDAIN Transceiver Not Included RCVSTBA RXDBIN TXINHA TXDBIN BusA BusB Encoder Decoder Protocol Controller Core1553BBC CPU Interface and Registers Backend Interface Figure 2 • Core1553BBC BC Block Diagram v4.0 Memory 64K*16 Core1553BBC MIL-STD-1553B Bus Controller A single 1553B encoder takes each word to be transmitted and serializes it using Manchester encoding. The encoder includes independent logic to prevent the BC from transmitting for greater than the allowed period and to provide loopback fail logic. The loopback logic monitors the received data and verifies that the core has correctly received every word that is transmitted. The encoder output is gated with the bus enable signals to select which buses the RT should be transmitting. Since the BC knows which bus is in use at any time, only a single decoder is required. The decoder takes the serial Manchester received data from the bus and extracts the received data words. The decoder requires a 12, 16, 20, or 24 MHz clock to extract the data and the clock from the serial stream. The decoder contains a digital phased lock loop PLL that generates a recovery clock used to sample the incoming serial data. The data is then deserialized and the 16-bit word decoded. The decoder detects whether a command, status or data word has been received and checks that no Manchester encoding or parity errors occurred in the word. The protocol controller block handles all the message sequencing and error recovery. This is a complex state machine that reads the 1553B message frames from the memory and transmits them on the 1553B bus. The CPU interface allows the system CPU to access the control registers within the BC. It also allows the CPU to Ordering Information Core1553BBC can be ordered through your local Actel sales representative. It should be ordered using the following number scheme Core1553BBC-XX, where XX is Table 19 Table 19 • Ordering Codes XX Description EV Evaluation Version SN Netlist for single-use on Actel devices AN Netlist for unlimited use on Actel devices SR RTL for single-use on Actel devices AR RTL for unlimited use on Actel devices UR RTL for unlimited use and not restricted to Actel devices The Evaluation board can also be ordered using the order code "Core1553BBC Eval Board." v4.0 Core1553BBC MIL-STD-1553B Bus Controller List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version v 0 v3.0 The "Supported Families" section has been updated to include Fusion. Table 1 was updated to include Fusion data. v2.0 The "Supported Families" section has been updated to include ProASIC3/E. Table 1 was updated to include ProASIC3/E data. Page 1 4 1 4 Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," and "Production." The definition of these categories are as follows: The product brief is a summarized version of an advanced or production datasheet containing general product information. This brief summarizes specific device and family information for unreleased products. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unmarked production This datasheet version contains information that is considered to be final. v4.0 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone Fax Actel Europe Ltd. Dunlop House, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone +44 0 1276 401 450 Fax +44 0 1276 401 490 Actel Japan EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone Fax Actel Hong Kong Suite 2114, Two Pacific Place 88 Queensway, Admiralty Hong Kong Phone +852 2185 6460 Fax +852 2185 6488

PDF Datasheet Preview

Core1553BBC MIL-STD-1553B Bus Controller

Product Summary

Intended Use
• 1553B Bus Controller BC
• DMA Backend Interface to External Memory

Key Features
• Supports MIL-STD-1553B
• Interfaces to External RAM

Supports up to 128kbytes of Memory Synchronous or Asynchronous Backend

Interface Backend Interface Identical to Core1553BRT
• Selectable Clock Rate of 12, 16, 20, or 24 MHz
• Provides Direct CPU Access to Memory
• Interfaces to Standard 1553B Transceivers
• Fully Automated Message Scheduling Frame Support Conditional Branching and Sub-routines Variable Inter-message Gaps and RT Response

Times Real Time Clock for Message Scheduling Asynchronous Message Support

Supported Families
• Fusion
• ProASIC3/E
• ProASICPLUS
• Axcelerator
• RTAX
• SX-A
• RTSX-S

Core Deliverables
• Netlist Version Compiled RTL Simulation Model, Compliant with the Actel Libero Integrated Design Environment IDE Compatible with the Actel Designer Place-andRoute Tool
• RTL Version VHDL or Verilog Core Source Code

Synthesis Scripts
• Actel-Developed Testbenches, VHDL and Verilog

Synthesis and Simulation Support
• Synthesis Design FPGA CompilerTM/FPGA ExpressTM , ExemplarTM
• Simulation Vital-Compliant VHDL Simulators and OVI-Compliant Verilog Simulators

Verification and Compliance
• Actel-Developed Simulation Testbench
• Core Implemented on the 1553B BC Development

System
• Third-Party 1553B Compliance Testing of the
1553B Encoder and Decoder Blocks Implemented in an A54SXA32-STD Device

Development System Optional
• Complete 1553B BC Implementation in an SX-A Device
• Includes a PCI Interface for Host CPU Connection
• Includes Transceivers and Bus Termination

Components

Contents
General Description 2 Core1553BBC Device Requirements 4 Core1553BBC Verification and Compliance 4 MIL-STD-1553B Bus Overview 4 I/O Signal Descriptions 6 Bus Transceivers 20 Development System 20 Typical BC System 22 Specifications 24 Ordering Information 28 List of Changes 29 Datasheet Categories 29

December 2005
v4.0
2005 Actel Corporation

Core1553BBC MIL-STD-1553B Bus Controller

The Core1553BBC provides a complete, MIL-STD-1553B Bus Controller BC . A typical system implementation using the Core1553BBC is shown in Figure

Core1553BBC reads message descriptor blocks from the memory and generates messages that are transmitted on the 1553B bus. Data words are read from the memory
and transmitted on the 1553B bus. Data received is written to the memory. The core can be configured directly to connect to synchronous or asynchronous memory devices.

The core consists of five main blocks the 1553B encoder, the 1553B decoder, a protocol controller block, a CPU interface, and a backend interface Figure

Backend Interface

Memory CPU

Glue Logic

CPU Interface

BUSAINEN BUSAINP BUSAINN

BUSAOUTINH BUSAOUTP BUSAOUTN

BUSBINEN BUSBINP BUSBIN

BUSAOUTINH BUSBOUTP BUSBOUTN

Core1553BBC

Figure 1
• Typical Core1553BBC System

Actel FPGA

RCVSTBA RXDAIN

TXINHA TXDAIN

Transceiver Not Included

RCVSTBA RXDBIN

TXINHA TXDBIN

BusA BusB

Encoder Decoder

Protocol Controller

Core1553BBC

CPU Interface
and Registers

Backend Interface

Figure 2
• Core1553BBC BC Block Diagram
v4.0

Memory 64K*16

Core1553BBC MIL-STD-1553B Bus Controller

A single 1553B encoder takes each word to be transmitted and serializes it using Manchester encoding. The encoder includes independent logic to prevent the BC from transmitting for greater than the allowed period and to provide loopback fail logic. The loopback logic monitors the received data and verifies that the core has correctly received every word that is transmitted. The encoder output is gated with the bus enable signals to select which buses the RT should be transmitting.

Since the BC knows which bus is in use at any time, only a single decoder is required. The decoder takes the serial Manchester received data from the bus and extracts the received data words. The decoder requires a 12, 16, 20, or 24 MHz clock to extract the data and the clock from the serial stream.

The decoder contains a digital phased lock loop PLL that generates a recovery clock used to sample the incoming serial data. The data is then deserialized and the 16-bit word decoded. The decoder detects whether a command, status or data word has been received and checks that no Manchester encoding or parity errors occurred in the word.

The protocol controller block handles all the message sequencing and error recovery. This is a complex state machine that reads the 1553B message frames from the memory and transmits them on the 1553B bus.

The CPU interface allows the system CPU to access the control registers within the BC. It also allows the CPU to
Ordering Information
Core1553BBC can be ordered through your local Actel sales representative. It should be ordered using the following number scheme Core1553BBC-XX, where XX is Table 19 Table 19
• Ordering Codes XX Description EV Evaluation Version SN Netlist for single-use on Actel devices AN Netlist for unlimited use on Actel devices SR RTL for single-use on Actel devices AR RTL for unlimited use on Actel devices UR RTL for unlimited use and not restricted to Actel devices

The Evaluation board can also be ordered using the order code "Core1553BBC Eval Board."
v4.0

Core1553BBC MIL-STD-1553B Bus Controller

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous Version Changes in Current Version v 0
v3.0

The "Supported Families" section has been updated to include Fusion.

Table 1 was updated to include Fusion data.
v2.0

The "Supported Families" section has been updated to include ProASIC3/E.

Table 1 was updated to include ProASIC3/E data.

Page 1 4 1 4

Datasheet Categories

In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," and "Production." The definition of these categories are as follows:

The product brief is a summarized version of an advanced or production datasheet containing general product information. This brief summarizes specific device and family information for unreleased products.

Advanced

This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production.

Unmarked production

This datasheet version contains information that is considered to be final.
v4.0

Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners.

Actel Corporation
2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone Fax

Actel Europe Ltd.

Dunlop House, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone +44 0 1276 401 450 Fax +44 0 1276 401 490

Actel Japan

EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan

Phone Fax

Actel Hong Kong

Suite 2114, Two Pacific Place 88 Queensway, Admiralty Hong Kong

Phone +852 2185 6460 Fax +852 2185 6488

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CORE1553BBC-AR Datasheet file may be downloaded here without warranties.

Datasheet ID: CORE1553BBC-AR 648928