MT29C4G96MAYBACJG-5 WT
MT29C4G96MAYBACJG-5 WT Datasheet
MT29C4G48MAYBAAKQ-5 WT, MT29C4G48MAZBAAKQ-5 WT, MT29C4G96MAYBACJG-5 WT, MT29C4G96MAZBACJG-5 WT, MT29C8G96MAYBADJV-5 WT, MT29C8G96MAZBADJV-5 WT MT29C4G48MAZBAAKQ-5 IT, MT29C4G96MAZBACJG-5 IT MT29C8G96MAZBADJV-5 IT
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MT29C4G96MAYBACJG-5 WT |
MT29C4G96MAYBACJG-5 WT (pdf) |
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MT29C8G96MAYBADJV-5 WT TR |
MT29C8G96MAYBADJV-5 WT TR |
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MT29C4G48MAYBAAKQ-5 WT TR |
MT29C4G48MAYBAAKQ-5 WT TR |
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MT29C4G96MAYBACJG-5 WT TR |
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MT29C4G96MAYBACKD-5 WT TR |
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MT29C4G48MAZBAAKQ-5 WT TR |
MT29C4G48MAZBAAKQ-5 WT TR |
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MT29C4G96MAZBACJG-5 IT TR |
MT29C4G96MAZBACJG-5 IT TR |
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MT29C8G96MAZBADJV-5 IT TR |
MT29C8G96MAZBADJV-5 IT TR |
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MT29C8G96MAZBADJV-5 WT TR |
MT29C8G96MAZBADJV-5 WT TR |
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MT29C4G48MAZBAAKQ-5 WT |
MT29C4G48MAZBAAKQ-5 WT |
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MT29C8G96MAYBADJV-5 WT |
MT29C8G96MAYBADJV-5 WT |
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MT29C8G96MAZBADJV-5 IT |
MT29C8G96MAZBADJV-5 IT |
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MT29C4G96MAZBACJG-5 IT |
MT29C4G96MAZBACJG-5 IT |
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MT29C4G96MAYBACKD-5 WT |
MT29C4G96MAYBACKD-5 WT |
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MT29C8G96MAZBADJV-5 WT |
MT29C8G96MAZBADJV-5 WT |
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MT29C4G48MAYBAAKQ-5 WT |
MT29C4G48MAYBAAKQ-5 WT |
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MT29C4G96MAZBACJG-5 WT |
MT29C4G96MAZBACJG-5 WT |
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MT29C4G96MAZBACJG-5 WT TR |
MT29C4G96MAZBACJG-5 WT TR |
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| Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP TI OMAP MCP Features NAND Flash and Mobile LPDDR 168-Ball Package-on-Package PoP MCP Combination Memory TI MT29C4G48MAYBAAKQ-5 WT, MT29C4G48MAZBAAKQ-5 WT, MT29C4G96MAYBACJG-5 WT, MT29C4G96MAZBACJG-5 WT, MT29C8G96MAYBADJV-5 WT, MT29C8G96MAZBADJV-5 WT MT29C4G48MAZBAAKQ-5 IT, MT29C4G96MAZBACJG-5 IT MT29C8G96MAZBADJV-5 IT • NAND Flash and LPDDR components • RoHS-compliant, “green” package • Separate NAND Flash and LPDDR interfaces • Space-saving multichip package/package-on-package combination • Low-voltage operation • Wireless temperature range to +85°C • Industrial temperature range to +85°C NAND Flash-Specific Features Organization • Page size x8 2112 bytes 2048 + 64 bytes x16 1056 words 1024 + 32 words • Block size 64 pages 128K + 4K bytes Mobile LPDDR-Specific Features • No external voltage reference required • No minimum clock rate requirement • 1.8V LVCMOS-compatible inputs • Programmable burst lengths • Partial-array self refresh PASR • Deep power-down DPD mode • Selectable output drive strength • STATUS REGISTER READ SRR supported1 Notes Contact factory for remapped SRR output. For physical part markings, see on page Figure 1 PoP Block Diagram NAND Flash Power NAND Flash Device LPDRAM Power LPDRAM Device NAND Flash Interface LPDRAM Interface Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP TI OMAP MCP Features Part Numbering Information Micron NAND Flash and LPDRAM devices are available in different configurations and densities. The MCP/PoP part numbering guide is available at Figure 2 Part Number Chart MT 29C XX XXX X XX -X XX Micron Technology Product Family NAND Flash Density LPDRAM Density Operating Voltage Range NAND Flash Configuration Production Status Operating Temperature Range LPDRAM Access Time Package Codes Chip Count LPDRAM Configuration Device Marking Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead, an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site To view the location of the abbreviated mark on the device, refer to customer service note CSN-11, “Product Mark/ Label,” at Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP TI OMAP MCP Features Contents MCP General Description 11 Ball Assignments and Descriptions 12 Electrical Specifications 16 Device Diagrams 17 Package Dimensions 19 4Gb, 8Gb x8, x16 NAND Flash Memory 22 Features 22 General Description 23 Architecture 24 Device and Array Organization 25 Asynchronous Interface Bus Operation 29 Asynchronous Enable/Standby 29 Asynchronous Commands 29 Asynchronous Addresses 31 Asynchronous Data Input 32 Asynchronous Data Output 33 Write Protect# 34 Ready/Busy# 34 Device Initialization 39 Command Definitions 40 Reset Operations 43 RESET FFh 43 Identification Operations 44 READ ID 90h 44 READ ID Parameter Tables 45 READ PARAMETER PAGE ECh 48 Bare Die Parameter Page Data Structure Tables 49 READ UNIQUE ID EDh 52 Feature Operations 53 SET FEATURES EFh 54 GET FEATURES EEh 55 Status Operations 58 READ STATUS 70h 59 READ STATUS ENHANCED 78h 59 Column Address Operations 61 RANDOM DATA READ 05h-E0h 61 RANDOM DATA READ TWO-PLANE 06h-E0h 62 RANDOM DATA INPUT 85h 63 PROGRAM FOR INTERNAL DATA INPUT 85h 64 Read Operations 66 READ MODE 00h 68 READ PAGE 00h-30h 68 READ PAGE CACHE SEQUENTIAL 31h 69 READ PAGE CACHE RANDOM 00h-31h 70 READ PAGE CACHE LAST 3Fh 72 READ PAGE TWO-PLANE 00h-00h-30h 73 Program Operations 75 PROGRAM PAGE 80h-10h 76 PROGRAM PAGE CACHE 80h-15h 76 PROGRAM PAGE TWO-PLANE 80h-11h 79 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary Accesses within a given burst can be programmed to be either sequential or interleaved via the standard mode register. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address. Table 55 Burst Definition Table Burst Length Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 168-Ball NAND Flash and LPDDR PoP TI OMAP MCP Standard Mode Register Table 55 Burst Definition Table Continued Burst Length Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0 1-0-3-2-5-4-7-6-9-8-B-A-D-C-F-E 2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1 2-3-0-1-6-7-4-5-A-B-8-9-E-F-C-D 3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2 3-2-1-0-7-6-5-4-B-A-9-8-F-E-D-C 4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3 4-5-6-7-0-1-2-3-C-D-E-F-8-9-A-B 5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4 5-4-7-6-1-0-3-2-D-C-F-E-9-8-B-A 6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5 6-7-4-5-2-3-0-1-E-F-C-D-A-B-8-9 7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0-F-E-D-C-B-A-9-8 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8 9-8-B-A-D-C-F-E-1-0-3-2-5-4-7-6 A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9 |
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