A42MX36-3PQG240

A42MX36-3PQG240 Datasheet

Ordering Information 3 42MX C-Module Implementation 7 42MX C-Module Implementation 7 42MX S-Module Implementation 8 A42MX24 and A42MX36 D-Module Implementation 9 A42MX36 Dual-Port SRAM Block 9 MX Routing Structure 10 Clock Networks of 42MX Devices 11 Quadrant Clock Network of A42MX36 Devices 11 42MX I/O Module 12 PCI Output Structure of A42MX24 and A42MX36 Devices 12 Silicon Explorer II Setup with 40MX 16 Silicon Explorer II Setup with 42MX 17 42MX IEEE Boundary Scan Circuitry 18 Device Selection Wizard 19 Typical Output Drive Characteristics Based Upon Measured Data 28 40MX Timing Model* 30 42MX Timing Model 30 42MX Timing Model Logic Functions Using Quadrant Clocks 31 42MX Timing Model SRAM Functions 32 Output Buffer Delays 32 AC Test Loads 33 Input Buffer Delays 33 Module Delays 33 Flip-Flops and Latches 34 Input Buffer Latches 34 Output Buffer Latches 35 Decode Module Timing 35 SRAM Timing Characteristics 35 42MX SRAM Write Operation 36 42MX SRAM Synchronous Read Operation 36 42MX SRAM Asynchronous Read 1 Read Address Controlled 36 42MX SRAM Asynchronous Read 2 Write Address Controlled 37 42MX Junction Temperature and Voltage Derating Curves Normalized to TJ = 25°C, VCCA = V 38 40MX Junction Temperature and Voltage Derating Curves Normalized to TJ = 25°C, VCC = V 39 42MX Junction Temperature and Voltage Derating Curves Normalized to TJ = 25°C, VCCA = V 39 40MX Junction Temperature and Voltage Derating Curves Normalized to TJ = 25°C, VCC = V 40 PL44 86 PL68 88 PL84 90 PQ100 93 PQ144 97 PQ160 102 PQ208 107 PQ240 113 VQ80 120 VQ100 123 TQ176 126 CQ208 131 CQ256 138

Part	Datasheet
A42MX36-3PQG240	A42MX36-3PQG240 (pdf)

Related Parts	Information
A42MX09-PG132C	A42MX09-PG132C
A42MX09-PQ144	A42MX09-PQ144
A42MX09-PG132B	A42MX09-PG132B
A42MX36-2PQ240I	A42MX36-2PQ240I
A42MX36-PQG240M	A42MX36-PQG240M
A42MX36-PQ240M	A42MX36-PQ240M
A42MX36-1PQG240I	A42MX36-1PQG240I
A42MX36-2PQ240	A42MX36-2PQ240
A42MX36-PQG240	A42MX36-PQG240
A42MX36-3PQ240	A42MX36-3PQ240
A42MX36-2PQG240I	A42MX36-2PQG240I
A42MX36-3PQ240I	A42MX36-3PQ240I
A42MX36-1PQ240I	A42MX36-1PQ240I
A42MX36-FPQ240	A42MX36-FPQ240
A42MX36-1PQG240M	A42MX36-1PQG240M
A42MX36-PQ240	A42MX36-PQ240
A42MX36-2PQG240	A42MX36-2PQG240
A42MX36-1PQ240M	A42MX36-1PQ240M
A42MX36-3PQG240I	A42MX36-3PQG240I
A42MX36-PQ240I	A42MX36-PQ240I
A42MX36-1PQG240	A42MX36-1PQG240
A42MX36-1PQ240	A42MX36-1PQ240
A42MX36-FPQG240	A42MX36-FPQG240
A42MX36-PQG240I	A42MX36-PQG240I
A42MX09-PG132M	A42MX09-PG132M

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DS2316 Datasheet 40MX and 42MX FPGA Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA +1 800 713-4113 Outside the USA +1 949 380-6100 Fax +1 949 215-4996 Email: 2016 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice. About Microsemi Microsemi Corporation Nasdaq MSCC offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs power management products timing and synchronization devices and precise time solutions, setting the world's standard for time voice processing devices RF solutions discrete components enterprise storage and communication solutions, security technologies and scalable anti-tamper products Ethernet solutions Power-over-Ethernet ICs and midspans as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has approximately 4,800 employees globally. Learn more at 12/16 Contents 2 40MX and 42MX FPGA Families 1 Features 1 High Capacity 1 High Performance 1 HiRel Features 1 Ease of Integration 1 Product Profile 1 Ordering Information 3 Plastic Device Resources 4 Ceramic Device Resources 4 Temperature Grade Offerings 5 Speed Grade Offerings 5 3 40MX and 42MX FPGAs 6 General Description 6 MX Architectural Overview 6 Logic Modules 6 Dual-Port SRAM Modules 8 Routing Structure 9 Clock Networks 10 MultiPlex I/O Modules 11 Other Architectural Features 12 Performance 12 User Security 12 Programming 12 Power Supply 13 Power-Up/Down in Mixed-Voltage Mode 13 Transient Current 13 Low Power Mode 14 Power Dissipation 14 General Power Equation 14 Static Power Component 14 Active Power Component 14 Equivalent Capacitance 15 CEQ Values for Microsemi MX FPGAs 15 Test Circuitry and Silicon Explorer II Probe 16 Design Consideration 17 IEEE Standard Boundary Scan Test BST Circuitry 17 JTAG Mode Activation 19 TRST Pin and TAP Controller Reset 19 Boundary Scan Description Language BSDL File 19 Development Tool Support 19 Related Documents 20 Application Notes 20 User Guides and Manuals 20 Miscellaneous 20 V Operating Conditions 20 5 V TTL Electrical Specifications 21 V Operating Conditions 22 V LVTTL Electrical Specifications 23 Ordering Information 3 42MX C-Module Implementation 7 42MX C-Module Implementation 7 42MX S-Module Implementation 8 A42MX24 and A42MX36 D-Module Implementation 9 A42MX36 Dual-Port SRAM Block 9 MX Routing Structure 10 Clock Networks of 42MX Devices 11 Quadrant Clock Network of A42MX36 Devices 11 42MX I/O Module 12 PCI Output Structure of A42MX24 and A42MX36 Devices 12 Silicon Explorer II Setup with 40MX 16 Silicon Explorer II Setup with 42MX 17 42MX IEEE Boundary Scan Circuitry 18 Device Selection Wizard 19 Typical Output Drive Characteristics Based Upon Measured Data 28 40MX Timing Model* 30 42MX Timing Model 30 42MX Timing Model Logic Functions Using Quadrant Clocks 31 42MX Timing Model SRAM Functions 32 Output Buffer Delays 32 AC Test Loads 33 Input Buffer Delays 33 Module Delays 33 Flip-Flops and Latches 34 Input Buffer Latches 34 Output Buffer Latches 35 Decode Module Timing 35 SRAM Timing Characteristics 35 42MX SRAM Write Operation 36 42MX SRAM Synchronous Read Operation 36 42MX SRAM Asynchronous Read 1 Read Address Controlled 36 42MX SRAM Asynchronous Read 2 Write Address Controlled 37 42MX Junction Temperature and Voltage Derating Curves Normalized to TJ = 25°C, VCCA = V 38 40MX Junction Temperature and Voltage Derating Curves Normalized to TJ = 25°C, VCC = V 39 42MX Junction Temperature and Voltage Derating Curves Normalized to TJ = 25°C, VCCA = V 39 40MX Junction Temperature and Voltage Derating Curves Normalized to TJ = 25°C, VCC = V 40 PL44 86 PL68 88 PL84 90 PQ100 93 PQ144 97 PQ160 102 PQ208 107 PQ240 113 VQ80 120 VQ100 123 TQ176 126 CQ208 131 CQ256 138 Figure 51 Figure 52 Figure 53 BG272 145 PG132 153 CQ172 158 Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Product profile 1 Plastic Device Resources 4 Ceramic Device Resources 4 Temperature Grade Offerings 5 Speed Grade Offerings 5 Voltage Support of MX Devices 13 Fixed Capacitance Values for MX FPGAs pF 16 Device Configuration Options for Probe Capability 17 Test Access Port Descriptions 18 Supported BST Public Instructions 18 Boundary Scan Pin Configuration and Functionality 19 Absolute Maximum Ratings for 40MX Devices* 20 Absolute Maximum Ratings for 42MX Devices* 20 Recommended Operating Conditions 21 5V TTL Electrical Specifications 21 Absolute Maximum Ratings for 40MX Devices* 22 Absolute Maximum Ratings for 42MX Devices* 22 Recommended Operating Conditions 22 3.3V LVTTL Electrical Specifications 23 Absolute Maximum Ratings* 23 Recommended Operating Conditions 24 Mixed 5.0V/3.3V Electrical Specifications 25 DC Specification V PCI Signaling 25 AC Specifications 5.0V PCI Signaling * 26 DC Specification V PCI Signaling 27 AC Specifications for V PCI Signaling * 27 Package Thermal Characteristics 29 42MX Temperature and Voltage Derating Factors Normalized to TJ = 25°C, VCCA = V 38 40MX Temperature and Voltage Derating Factors Normalized to TJ = 25°C, VCC = V 38 42MX Temperature and Voltage Derating Factors Normalized to TJ = 25°C, VCCA = V 39 40MX Temperature and Voltage Derating Factors Normalized to TJ = 25°C, VCC = V 39 Clock Specification for 33 MHz PCI 40 Timing Parameters for 33 MHz PCI 40 A40MX02 Timing Characteristics Nominal V Operation 41 A40MX02 Timing Characteristics Nominal V Operation 43 A40MX04 Timing Characteristics Nominal V Operation Worst-Case Commercial Conditions, VCC = V, TJ = 70°C 46 A40MX04 Timing Characteristics Nominal V Operation Worst-Case Commercial Conditions, VCC = V, TJ = 70°C 49 A42MX09 Timing Characteristics Nominal V Operation Worst-Case Commercial Conditions, VCCA = V, TJ = 70°C 52 A42MX09 Timing Characteristics Nominal V Operation Worst-Case Commercial Conditions, VCCA = V, TJ = 70°C 56 A42MX16 Timing Characteristics Nominal V Operation Worst-Case Commercial Conditions, VCCA = V, TJ = 70°C 60 A42MX16 Timing Characteristics Nominal V Operation Worst-Case Commercial Conditions, VCCA = V, TJ = 70°C 64 A42MX24 Timing Characteristics Nominal V Operation Worst-Case Commercial Conditions, VCCA = V, TJ = 70°C 67 A42MX24 Timing Characteristics Nominal V Operation Worst-Case Commercial Conditions, VCCA = V, TJ = 70°C 71 A42MX36 Timing Characteristics Nominal V Operation Worst-Case Commercial Conditions, VCCA = V, TJ = 70°C 75 A42MX36 Timing Characteristics Nominal V Operation Worst-Case Commercial Conditions, Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 VCCA = V, TJ = 70°C 79 Configuration of Unused I/Os 84 PL44 86 PL68 88 PL84 90 PQ 100 93 PQ144 97 PQ160 102 PQ208 107 PQ240 113 VQ80 120 VQ100 123 TQ176 126 CQ208 132 CQ256 138 BG272 145 PG132 153 CQ172 158 viii • Table 15, page 21 is edited to add the footnote, VIH Min is 2.4V for A42MX36 family. This applies only to VCCI of 5V and is not applicable to VCCI of 3.3V • Table 22, page 25 is edited to add the footnote, VIH Min is 2.4V for A42MX36 family. This applies only to VCCI of 5V and is not applicable to VCCI of 3.3V • Table 23, page 25 is edited to add the footnote, VIH Min is 2.4V for A42MX36 family. This applies only to VCCI of 5V and is not applicable to VCCI of 3.3V • Added CQFP package information for A42MX16 device in Product Profile, page 1 and Ceramic Device Resources, page 4 SAR • Added Military M and MIL-STD-883 Class B grades for CPGA 132 Package and added Commercial C , Military M , and MIL-STD-883 Class B grades for CQFP 172 Package in Temperature Grade Offerings, page 5 SAR 79519 • Changed Silicon Sculptor II to Silicon Sculptor in Programming, page 12 SAR 38754 • Added Figure 53, page 158 CQ172 package SAR • Added Figure 42, page 97 PQ144 Package for A42MX09 device SAR 69776 • Added Figure 52, page 153 PQ132 Package for A42MX09 device SAR 69776 • Added information on power-up behavior for A42MX24 and A42MX36 devices to the Power Supply, page 13 SAR 42096 • Corrected the inadvertent mistake in the naming of the PL68 pin assignment table SARs 48999, 49793 • Ordering Information, page 3 was updated to include lead-free package ordering codes SAR 21968 SAR 34774 • In Table 20, page 23, the limits in VI were changed from to VCCI + to VCCA + In Table 22, page 25, VOH was changed from to for the min in industrial and military. VIH had VCCI and that was changed to VCCA • The Ease of Integration, page 1 was updated • The Temperature Grade Offerings, page 5 is new • The Speed Grade Offerings, page 5 is new • The General Description, page 6 was updated • The MultiPlex I/O Modules, page 11 was updated • The User Security, page 12 was updated • Table 6, page 13 was updated • The Power Dissipation, page 14 was updated. • The Static Power Component, page 14 was updated • The Equivalent Capacitance, page 15 was updated • Figure 13, page 17 was updated • Table 10, page 18 was updated. • Figure 14, page 18 was updated. • Table 11, page 19 was updated. 40MX and 42MX FPGA Families 2 40MX and 42MX FPGA Families The following sections list out various features of the 40MX and 42MX FPGA family devices. High Capacity • Single-Chip ASIC Alternative • 3,000 to 54,000 System Gates • Up to kbits Configurable Dual-Port SRAM • Fast Wide-Decode Circuitry • Up to 202 User-Programmable I/O Pins High Performance • ns Clock-to-Out • 250 MHz Performance • 5 ns Dual-Port SRAM Access • 100 MHz FIFOs • ns 35-Bit Address Decode HiRel Features • Commercial, Industrial, Automotive, and Military Temperature Plastic Packages • Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages • QML Certification • Ceramic Devices Available to DSCC SMD Ease of Integration • Mixed-Voltage Operation V or V for core and I/Os , with PCI-Compliant I/Os • Up to 100% Resource Utilization and 100% Pin Locking • Deterministic, User-Controllable Timing • Unique In-System Diagnostic and Verification Capability with Silicon Explorer II • Low Power Consumption • IEEE Standard JTAG Boundary Scan Testing Product Profile The following table gives the features of the products. Table 1 • Product profile Device Capacity System Gates SRAM Bits Logic Modules Sequential Combinatorial Decode Clock-to-Out SRAM Modules 64x4 or 32x8 Dedicated Flip-Flops A40MX02 A40MX04 A42MX09 A42MX16 3,000 6,000 14,000 24,000 348 336 624 608 A42MX24 A42MX36 36,000 54,000 2,560 954 912 24 1,230 1,184 24 1,230 40MX and 42MX FPGA Families Table 1 • Product profile Ordering Information The following figure shows ordering information.All the following tables show plastic and ceramic device resources, temperature and speed grade offerings. Figure 1 • Ordering Information A42MX16 _ 1 Application Temperature Range Blank = Commercial 0 to +70°C I = Industrial to +85°C M = Military to +125°C B = MIL-STD-883 A = Automotive to +125°C Package Lead Count Lead-Free Packaging Blank = Standard Packaging G = RoHS Compliant Packaging Package Type PL = Plastic Leaded Chip Carrier PQ = Plastic Quad Flat Pack TQ = Thin mm Quad Flat Pack VQ = Very Thin mm Quad Flat Pack BG = Plastic Ball Grid Array CQ =Ceramic Quad Flat Pack PG =Ceramic Pin Grid Array Speed Grade Blank = Standard Speed = Approximately 15% Faster than Standard = Approximately 25% Faster than Standard = Approximately 35% Faster than Standard = Approximately 40% Slower than Standard Part Number A40MX02 = 3,000 System Gates A40MX04 = 6,000 System Gates A42MX09 = 14,000 System Gates A42MX16 = 24,000 System Gates A42MX24 = 36,000 System Gates A42MX36 = 54,000 System Gates 40MX and 42MX FPGA Families Plastic Device Resources Table 2 • Plastic Device Resources User I/Os Device PQFP PLCC PQFP 14444-Pin 68-Pin 84-Pin 100-Pin A40MX02 34 57 A40MX04 34 57 A42MX09 A42MX16 A42MX24 A42MX36 PQFP 208160-Pin 125 140 125 176 VQFP PQFP VQFP 100240-Pin 80-Pin TQFP 176Pin 104 140 150 PBGA 272Pin 202 Note Package Definitions PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack, PBGA = Plastic Ball Grid Array Ceramic Device Resources Table 3 • Ceramic Device Resources Device A42MX09 A42MX16 A42MX36 User I/Os CPGA 132-Pin 95 CQFP 172-Pin 131 CQFP 208-Pin 176 CQFP 256-Pin 202 Note Package Definitions CQFP = Ceramic Quad Flat Pack 40MX and 42MX FPGA Families Temperature Grade Offerings Table 4 • Temperature Grade Offerings Package PLCC 44 PLCC 68 PLCC 84 PQFP 100 PQFP 144 PQFP 160 PQFP 208 PQFP 240 VQFP 80 VQFP 100 TQFP 176 PBGA 272 CQFP 172 CQFP 208 CQFP 256 CPGA 132 A40MX02 C, I, M C, I, A, M C, I, A, M C, I, A, M

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DS2316 Datasheet 40MX and 42MX FPGA

Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA +1 800 713-4113 Outside the USA +1 949 380-6100 Fax +1 949 215-4996 Email:
2016 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.

Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.

About Microsemi

Microsemi Corporation Nasdaq MSCC offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs power management products timing and synchronization devices and precise time solutions, setting the world's standard for time voice processing devices RF solutions discrete components enterprise storage and communication solutions, security technologies and scalable anti-tamper products Ethernet solutions Power-over-Ethernet ICs and midspans as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has approximately 4,800 employees globally. Learn more at
12/16

Contents
2 40MX and 42MX FPGA Families 1

Features 1

High Capacity 1

High Performance 1

HiRel Features 1

Ease of Integration 1

Product Profile 1
Ordering Information 3

Plastic Device Resources 4

Ceramic Device Resources 4

Temperature Grade Offerings 5

Speed Grade Offerings 5
3 40MX and 42MX FPGAs 6

General Description 6

MX Architectural Overview 6

Logic Modules 6

Dual-Port SRAM Modules 8

Routing Structure 9

Clock Networks 10

MultiPlex I/O Modules 11

Other Architectural Features 12

Performance 12

User Security 12

Programming 12

Power Supply 13

Power-Up/Down in Mixed-Voltage Mode 13

Transient Current 13

Low Power Mode 14

Power Dissipation 14

General Power Equation 14

Static Power Component 14

Active Power Component 14

Equivalent Capacitance 15

CEQ Values for Microsemi MX FPGAs 15 Test Circuitry and Silicon Explorer II Probe 16

Design Consideration 17

IEEE Standard Boundary Scan Test BST Circuitry 17

JTAG Mode Activation 19

TRST Pin and TAP Controller Reset 19

Boundary Scan Description Language BSDL File 19

Development Tool Support 19

Related Documents 20

Application Notes 20

User Guides and Manuals 20

Miscellaneous 20

V Operating Conditions 20
5 V TTL Electrical Specifications 21

V Operating Conditions 22

V LVTTL Electrical Specifications 23
Ordering Information 3 42MX C-Module Implementation 7 42MX C-Module Implementation 7 42MX S-Module Implementation 8 A42MX24 and A42MX36 D-Module Implementation 9 A42MX36 Dual-Port SRAM Block 9 MX Routing Structure 10 Clock Networks of 42MX Devices 11 Quadrant Clock Network of A42MX36 Devices 11 42MX I/O Module 12 PCI Output Structure of A42MX24 and A42MX36 Devices 12 Silicon Explorer II Setup with 40MX 16 Silicon Explorer II Setup with 42MX 17 42MX IEEE Boundary Scan Circuitry 18 Device Selection Wizard 19 Typical Output Drive Characteristics Based Upon Measured Data 28 40MX Timing Model* 30 42MX Timing Model 30 42MX Timing Model Logic Functions Using Quadrant Clocks 31 42MX Timing Model SRAM Functions 32 Output Buffer Delays 32 AC Test Loads 33 Input Buffer Delays 33 Module Delays 33 Flip-Flops and Latches 34 Input Buffer Latches 34 Output Buffer Latches 35 Decode Module Timing 35 SRAM Timing Characteristics 35 42MX SRAM Write Operation 36 42MX SRAM Synchronous Read Operation 36 42MX SRAM Asynchronous Read 1 Read Address Controlled 36 42MX SRAM Asynchronous Read 2 Write Address Controlled 37 42MX Junction Temperature and Voltage Derating Curves Normalized to TJ = 25°C, VCCA = V 38 40MX Junction Temperature and Voltage Derating Curves Normalized to TJ = 25°C, VCC = V 39 42MX Junction Temperature and Voltage Derating Curves Normalized to TJ = 25°C, VCCA = V 39 40MX Junction Temperature and Voltage Derating Curves Normalized to TJ = 25°C, VCC = V 40 PL44 86 PL68 88 PL84 90 PQ100 93 PQ144 97 PQ160 102 PQ208 107 PQ240 113 VQ80 120 VQ100 123 TQ176 126 CQ208 131 CQ256 138

Figure 51 Figure 52 Figure 53

BG272 145 PG132 153 CQ172 158

Tables

Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36

Table 37

Table 38

Table 39

Table 40

Table 41

Table 42

Table 43

Table 44

Table 45

Product profile 1

Plastic Device Resources 4 Ceramic Device Resources 4

Temperature Grade Offerings 5 Speed Grade Offerings 5 Voltage Support of MX Devices 13

Fixed Capacitance Values for MX FPGAs pF 16 Device Configuration Options for Probe Capability 17 Test Access Port Descriptions 18

Supported BST Public Instructions 18 Boundary Scan Pin Configuration and Functionality 19 Absolute Maximum Ratings for 40MX Devices* 20

Absolute Maximum Ratings for 42MX Devices* 20 Recommended Operating Conditions 21 5V TTL Electrical Specifications 21

Absolute Maximum Ratings for 40MX Devices* 22 Absolute Maximum Ratings for 42MX Devices* 22 Recommended Operating Conditions 22
3.3V LVTTL Electrical Specifications 23 Absolute Maximum Ratings* 23 Recommended Operating Conditions 24

Mixed 5.0V/3.3V Electrical Specifications 25 DC Specification V PCI Signaling 25 AC Specifications 5.0V PCI Signaling * 26 DC Specification V PCI Signaling 27 AC Specifications for V PCI Signaling * 27 Package Thermal Characteristics 29
42MX Temperature and Voltage Derating Factors Normalized to TJ = 25°C, VCCA = V 38 40MX Temperature and Voltage Derating Factors Normalized to TJ = 25°C, VCC = V 38 42MX Temperature and Voltage Derating Factors Normalized to TJ = 25°C, VCCA = V 39
40MX Temperature and Voltage Derating Factors Normalized to TJ = 25°C, VCC = V 39 Clock Specification for 33 MHz PCI 40 Timing Parameters for 33 MHz PCI 40

A40MX02 Timing Characteristics Nominal V Operation 41 A40MX02 Timing Characteristics Nominal V Operation 43 A40MX04 Timing Characteristics Nominal V Operation Worst-Case Commercial Conditions,

VCC = V, TJ = 70°C 46 A40MX04 Timing Characteristics Nominal V Operation Worst-Case Commercial Conditions, VCC = V, TJ = 70°C 49 A42MX09 Timing Characteristics Nominal V Operation Worst-Case Commercial Conditions, VCCA = V, TJ = 70°C 52 A42MX09 Timing Characteristics Nominal V Operation Worst-Case Commercial Conditions,

VCCA = V, TJ = 70°C 56 A42MX16 Timing Characteristics Nominal V Operation Worst-Case Commercial Conditions, VCCA = V, TJ = 70°C 60 A42MX16 Timing Characteristics Nominal V Operation Worst-Case Commercial Conditions, VCCA = V, TJ = 70°C 64 A42MX24 Timing Characteristics Nominal V Operation Worst-Case Commercial Conditions, VCCA = V, TJ = 70°C 67 A42MX24 Timing Characteristics Nominal V Operation Worst-Case Commercial Conditions,

VCCA = V, TJ = 70°C 71 A42MX36 Timing Characteristics Nominal V Operation Worst-Case Commercial Conditions, VCCA = V, TJ = 70°C 75 A42MX36 Timing Characteristics Nominal V Operation Worst-Case Commercial Conditions,

Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62

VCCA = V, TJ = 70°C 79 Configuration of Unused I/Os 84 PL44 86 PL68 88 PL84 90 PQ 100 93 PQ144 97 PQ160 102 PQ208 107 PQ240 113 VQ80 120 VQ100 123 TQ176 126 CQ208 132 CQ256 138 BG272 145 PG132 153 CQ172 158
viii
• Table 15, page 21 is edited to add the footnote, VIH Min is 2.4V for A42MX36 family. This applies only to VCCI of 5V and is not applicable to VCCI of 3.3V
• Table 22, page 25 is edited to add the footnote, VIH Min is 2.4V for A42MX36 family. This applies only to VCCI of 5V and is not applicable to VCCI of 3.3V
• Table 23, page 25 is edited to add the footnote, VIH Min is 2.4V for A42MX36 family. This applies only to VCCI of 5V and is not applicable to VCCI of 3.3V
• Added CQFP package information for A42MX16 device in Product Profile, page 1 and Ceramic Device Resources, page 4 SAR
• Added Military M and MIL-STD-883 Class B grades for CPGA 132 Package and added Commercial C , Military M , and MIL-STD-883 Class B grades for CQFP 172 Package in Temperature Grade Offerings, page 5 SAR 79519
• Changed Silicon Sculptor II to Silicon Sculptor in Programming, page 12 SAR 38754
• Added Figure 53, page 158 CQ172 package SAR
• Added Figure 42, page 97 PQ144 Package for A42MX09 device SAR 69776
• Added Figure 52, page 153 PQ132 Package for A42MX09 device SAR 69776
• Added information on power-up behavior for A42MX24 and A42MX36 devices to the Power Supply, page 13 SAR 42096
• Corrected the inadvertent mistake in the naming of the PL68 pin assignment table SARs 48999, 49793
• Ordering Information, page 3 was updated to include lead-free package ordering codes SAR 21968

SAR 34774
• In Table 20, page 23, the limits in VI were changed from to VCCI + to VCCA +

In Table 22, page 25, VOH was changed from to for the min in industrial and military. VIH had VCCI and that was changed to VCCA
• The Ease of Integration, page 1 was updated
• The Temperature Grade Offerings, page 5 is new
• The Speed Grade Offerings, page 5 is new
• The General Description, page 6 was updated
• The MultiPlex I/O Modules, page 11 was updated
• The User Security, page 12 was updated
• Table 6, page 13 was updated
• The Power Dissipation, page 14 was updated.
• The Static Power Component, page 14 was updated
• The Equivalent Capacitance, page 15 was updated
• Figure 13, page 17 was updated
• Table 10, page 18 was updated.
• Figure 14, page 18 was updated.
• Table 11, page 19 was updated.
40MX and 42MX FPGA Families
2 40MX and 42MX FPGA Families

The following sections list out various features of the 40MX and 42MX FPGA family devices.

High Capacity
• Single-Chip ASIC Alternative
• 3,000 to 54,000 System Gates
• Up to kbits Configurable Dual-Port SRAM
• Fast Wide-Decode Circuitry
• Up to 202 User-Programmable I/O Pins

High Performance
• ns Clock-to-Out
• 250 MHz Performance
• 5 ns Dual-Port SRAM Access
• 100 MHz FIFOs
• ns 35-Bit Address Decode

HiRel Features
• Commercial, Industrial, Automotive, and Military Temperature Plastic Packages
• Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages
• QML Certification
• Ceramic Devices Available to DSCC SMD

Ease of Integration
• Mixed-Voltage Operation V or V for core and I/Os , with PCI-Compliant I/Os
• Up to 100% Resource Utilization and 100% Pin Locking
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Verification Capability with Silicon Explorer II
• Low Power Consumption
• IEEE Standard JTAG Boundary Scan Testing

Product Profile

The following table gives the features of the products.

Table 1
• Product profile

Device

Capacity System Gates SRAM Bits

Logic Modules Sequential Combinatorial Decode

Clock-to-Out

SRAM Modules 64x4 or 32x8

Dedicated Flip-Flops

A40MX02 A40MX04 A42MX09 A42MX16
3,000
6,000
14,000
24,000
348 336
624 608

A42MX24 A42MX36
36,000
54,000 2,560
954 912 24
1,230 1,184 24
1,230
40MX and 42MX FPGA Families

Table 1
• Product profile
Ordering Information
The following figure shows ordering information.All the following tables show plastic and ceramic device resources, temperature and speed grade offerings.
Figure 1
• Ordering Information

A42MX16 _ 1

Application Temperature Range Blank = Commercial 0 to +70°C I = Industrial to +85°C M = Military to +125°C B = MIL-STD-883 A = Automotive to +125°C

Package Lead Count

Lead-Free Packaging Blank = Standard Packaging G = RoHS Compliant Packaging

Package Type PL = Plastic Leaded Chip Carrier PQ = Plastic Quad Flat Pack TQ = Thin mm Quad Flat Pack VQ = Very Thin mm Quad Flat Pack BG = Plastic Ball Grid Array CQ =Ceramic Quad Flat Pack PG =Ceramic Pin Grid Array

Speed Grade Blank = Standard Speed = Approximately 15% Faster than Standard = Approximately 25% Faster than Standard = Approximately 35% Faster than Standard = Approximately 40% Slower than Standard

Part Number A40MX02 = 3,000 System Gates A40MX04 = 6,000 System Gates A42MX09 = 14,000 System Gates A42MX16 = 24,000 System Gates A42MX24 = 36,000 System Gates A42MX36 = 54,000 System Gates
40MX and 42MX FPGA Families

Plastic Device Resources

Table 2
• Plastic Device Resources

User I/Os

Device

PQFP PLCC PQFP 14444-Pin 68-Pin 84-Pin 100-Pin

A40MX02 34 57

A40MX04 34 57

A42MX09

A42MX16

A42MX24

A42MX36

PQFP 208160-Pin
125 140
125 176

VQFP PQFP VQFP 100240-Pin 80-Pin

TQFP 176Pin 104 140 150

PBGA 272Pin 202

Note Package Definitions PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack, PBGA = Plastic Ball Grid Array

Ceramic Device Resources

Table 3
• Ceramic Device Resources

Device A42MX09 A42MX16 A42MX36

User I/Os CPGA 132-Pin 95

CQFP 172-Pin 131

CQFP 208-Pin 176

CQFP 256-Pin 202

Note Package Definitions CQFP = Ceramic Quad Flat Pack
40MX and 42MX FPGA Families

Temperature Grade Offerings

Table 4
• Temperature Grade Offerings

Package PLCC 44 PLCC 68 PLCC 84 PQFP 100 PQFP 144 PQFP 160 PQFP 208 PQFP 240 VQFP 80 VQFP 100 TQFP 176 PBGA 272 CQFP 172 CQFP 208 CQFP 256 CPGA 132

A40MX02 C, I, M C, I, A, M C, I, A, M

C, I, A, M

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived A42MX36-3PQG240 Datasheet file may be downloaded here without warranties.

Datasheet ID: A42MX36-3PQG240 648594