MAX3629EVKIT+

MAX3629EVKIT+ Datasheet

MAX3629

Part	Datasheet
MAX3629EVKIT+	MAX3629EVKIT+ (pdf)

Related Parts	Information
MAX3629CTJ+T	MAX3629CTJ+T
MAX3629CTJ+	MAX3629CTJ+

PDF Datasheet Preview
MAX3629 +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs The MAX3629 is a low-jitter precision clock generator optimized for network applications. The device integrates a crystal oscillator and a phase-locked loop PLL to generate high-frequency clock outputs for Ethernet applications. Maxim’s proprietary PLL design features ultra-low jitter 0.4psRMS and excellent power-supply noise rejection PSNR , minimizing design risk for network equipment. The MAX3629 contains five LVDS outputs and three LVCMOS outputs. The output frequencies are selectable among 125MHz, 156.25MHz, and 312.5MHz by pin control. Ethernet Networking Equipment Typical Operating Circuit +3.3V ±5% 0.1uF 0.1uF 0.1uF 10uF 0.01uF VDDA VDD VDDO_DIFF 33pF 25MHz CL = 18pF 27pF OSC_IN X_OUT MAX3629 X_IN VDD PLL_BP GND, OPEN, OR VDD GND, OPEN, OR VDD FSELA FSELB VDDO_SE Q0 Z0 = 50Ω 125MHz/156.25MHz/ 312.5MHz Z0 = 50Ω Z0 = 50Ω 125MHz/156.25MHz/ 312.5MHz Z0 = 50Ω Z0 = 50Ω 125MHz/156.25MHz/ 312.5MHz Z0 = 50Ω Z0 = 50Ω 125MHz/156.25MHz/ 312.5MHz Z0 = 50Ω Z0 = 50Ω 125MHz/156.25MHz/ Ordering Information PART TEMP RANGE PIN-PACKAGE MAX3629CTJ+ 0°C to +70°C 32 TQFN-EP* +Denotes a lead Pb -free/RoHS-compliant package. EP = Exposed pad. Pin Configuration RESERVED VDDO_SE Q7 GND Q6 VDDO_SE Q5 GND TOP VIEW 24 23 22 21 20 19 18 17 VDDA 25 16 FSELB PLL_BP 26 15 RESERVED VDD 27 14 Q4 FSELA 28 OSC_IN 29 MAX3629 13 Q4 12 VDDO_DIFF X_IN 30 11 Q3 X_OUT 31 GND 32 10 Q3 9 GND 1 2345678 Q0 GND Q1 VDDO_DIFF Q2 33Ω 125MHz/156.25MHz Z0 = 50Ω ASIC 33Ω 125MHz/156.25MHz Z0 = 50Ω ASIC THIN QFN-EP 5mm x 5mm EXPOSED PAD CONNECTED TO GROUND. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at MAX3629 +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs ABSOLUTE MAXIMUM RATINGS Supply Voltage Range at VDD, VDDA, VDDO_SE, VDDO_DIFF to +4.0V Voltage Range at Q0, Q0, Q1, Q1, Q2, Q2, Q3, Q3, Q4, Q4, Q5, Q6, Q7, PLL_BP, FSELA, FSELB, OSC_IN .........................-0.3V to VDD + 0.3V Voltage Range at X_IN Pin to +1.2V Voltage Range at X_OUT Pin ..........................-0.3V to VDD - 0.6V Continuous Power Dissipation TA = +70°C 32-Pin TQFN-EP derate 34.5mW/°C above +70°C ..2759mW Operating Junction Temperature ......................-55°C to +150°C Storage Temperature Range .............................-65°C to +160°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS VDD = +3.0V to +3.6V, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VDD = +3.3V, TA = +25°C, unless otherwise noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled, PLL_BP = high-Z or high. When PLL is bypassed, PLL_BP = low. Note 1 PARAMETER CONDITIONS Power-Supply Current Note 2 PLL enabled IDD PLL bypassed LVDS OUTPUTS Q0, Q0, Q1, Q1, Q2, Q2, Q3, Q3, Q4, Q4 Pins Output High Voltage Output Low Voltage Differential Output Voltage Amplitude \|VOD\| Figure 1 Change in Magnitude of Differential Output for Complementary States Output Offset Voltage Change in Magnitude of Output Offset Voltage for Complementary States Differential Output Impedance Output Current Shorted together Short to ground Note 3 Clock Output Rise/Fall Time Output Duty-Cycle Distortion tr, tf 20% to 80%, RL = PLL enabled PLL bypassed Note 4 LVCMOS/LVTTL OUTPUTS Q5, Q6, Q7 Pins Output High Voltage Output Low Voltage Output Rise/Fall Time Output Duty-Cycle Distortion VOH IOH = -12mA IOL = 12mA tr, tf 20% to 80% at 125MHz Note 5 PLL enabled, PLL bypassed Note 4

PDF Datasheet Preview

MAX3629
+3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs

The MAX3629 is a low-jitter precision clock generator optimized for network applications. The device integrates a crystal oscillator and a phase-locked loop PLL to generate high-frequency clock outputs for Ethernet applications.

Maxim’s proprietary PLL design features ultra-low jitter 0.4psRMS and excellent power-supply noise rejection PSNR , minimizing design risk for network equipment.

The MAX3629 contains five LVDS outputs and three LVCMOS outputs. The output frequencies are selectable among 125MHz, 156.25MHz, and 312.5MHz by pin control.

Ethernet Networking Equipment

Typical Operating Circuit
+3.3V ±5%
0.1uF
0.1uF
0.1uF
10uF 0.01uF

VDDA

VDD VDDO_DIFF
33pF
25MHz CL = 18pF
27pF

OSC_IN X_OUT

MAX3629

X_IN

VDD PLL_BP

GND, OPEN, OR VDD GND, OPEN, OR VDD

FSELA FSELB

VDDO_SE Q0

Z0 = 50Ω 125MHz/156.25MHz/
312.5MHz

Z0 = 50Ω

Z0 = 50Ω
125MHz/156.25MHz/
312.5MHz

Z0 = 50Ω

Z0 = 50Ω
125MHz/156.25MHz/
312.5MHz

Z0 = 50Ω

Z0 = 50Ω
125MHz/156.25MHz/
312.5MHz

Z0 = 50Ω

Z0 = 50Ω
125MHz/156.25MHz/
Ordering Information

PART

TEMP RANGE

PIN-PACKAGE

MAX3629CTJ+
0°C to +70°C
32 TQFN-EP*
+Denotes a lead Pb -free/RoHS-compliant package. *EP = Exposed pad.

Pin Configuration

RESERVED VDDO_SE Q7 GND Q6 VDDO_SE Q5 GND

TOP VIEW
24 23 22 21 20 19 18 17

VDDA 25
16 FSELB

PLL_BP 26
15 RESERVED

VDD 27
14 Q4

FSELA 28 OSC_IN 29

MAX3629
13 Q4 12 VDDO_DIFF

X_IN 30
11 Q3

X_OUT 31

GND 32
10 Q3
9 GND
1 2345678

Q0 GND Q1 VDDO_DIFF Q2
33Ω 125MHz/156.25MHz

Z0 = 50Ω

ASIC
33Ω 125MHz/156.25MHz

Z0 = 50Ω

ASIC

THIN QFN-EP 5mm x 5mm
*EXPOSED PAD CONNECTED TO GROUND.

Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at

MAX3629
+3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs

ABSOLUTE MAXIMUM RATINGS

Supply Voltage Range at VDD, VDDA, VDDO_SE, VDDO_DIFF to +4.0V

Voltage Range at Q0, Q0, Q1, Q1, Q2, Q2, Q3, Q3, Q4, Q4, Q5, Q6, Q7, PLL_BP, FSELA, FSELB, OSC_IN .........................-0.3V to VDD + 0.3V

Voltage Range at X_IN Pin to +1.2V

Voltage Range at X_OUT Pin ..........................-0.3V to VDD - 0.6V Continuous Power Dissipation TA = +70°C
32-Pin TQFN-EP derate 34.5mW/°C above +70°C ..2759mW Operating Junction Temperature ......................-55°C to +150°C

Storage Temperature Range .............................-65°C to +160°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

VDD = +3.0V to +3.6V, TA = 0°C to +70°C, unless otherwise noted. Typical values are at VDD = +3.3V, TA = +25°C, unless otherwise noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled, PLL_BP = high-Z or high. When PLL is bypassed, PLL_BP = low. Note 1

PARAMETER

CONDITIONS

Power-Supply Current Note 2

PLL enabled IDD

PLL bypassed

LVDS OUTPUTS Q0, Q0, Q1, Q1, Q2, Q2, Q3, Q3, Q4, Q4 Pins

Output High Voltage

Output Low Voltage

Differential Output Voltage Amplitude
|VOD| Figure 1

Change in Magnitude of Differential Output for Complementary States

Output Offset Voltage

Change in Magnitude of Output Offset Voltage for Complementary States

Differential Output Impedance

Output Current

Shorted together Short to ground Note 3

Clock Output Rise/Fall Time Output Duty-Cycle Distortion
tr, tf
20% to 80%, RL =

PLL enabled

PLL bypassed Note 4

LVCMOS/LVTTL OUTPUTS Q5, Q6, Q7 Pins

Output High Voltage Output Low Voltage Output Rise/Fall Time Output Duty-Cycle Distortion

VOH IOH = -12mA

IOL = 12mA
tr, tf
20% to 80% at 125MHz Note 5

PLL enabled, PLL bypassed Note 4

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Datasheet ID: MAX3629EVKIT+ 647310