DS31407GN+

DS31407GN+ Datasheet

DS31407 3-Input, 4-Output, Single DPLL Timing IC

Part	Datasheet
DS31407GN+	DS31407GN+ (pdf)

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ABRIDGED DATA SHEET DS31407 3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter The DS31407 is a flexible, high-performance timing IC for diverse frequency conversion and frequency synthesis applications. On each of its three input clocks and four output clocks, the device can accept or generate nearly any frequency between 2kHz and 750MHz. The input clocks are divided down, fractionally scaled as needed, and continuously monitored for activity and frequency accuracy. The best input clock is selected, manually or automatically, as the reference clock for the rest of the device. A flexible, high-performance digital PLL locks to the selected reference and provides programmable bandwidth, very high resolution holdover capability, and truly hitless switching between input clocks. The digital PLL is followed by a clock synthesis subsystem that has two fully programmable digital frequency synthesis blocks, a high-speed low-jitter APLL, and four output clocks, each with its own 32-bit divider and phase adjustment. The APLL provides fractional scaling and output jitter less than 1ps RMS. For telecom systems, the DS31407 has all required features and functions to serve as a central timing function or as a line card timing IC. With a suitable oscillator the DS31407 meets the requirements of Stratum 2, 3E, 3, 4E, and 4, G.812 Types G.813, and G.8262. Frequency Conversion Applications in a Wide Variety of Equipment Types Telecom Line Cards or Timing Cards with Any Mix of SONET/SDH, Synchronous Ethernet and/or OTN Ports in WAN Equipment Including MSPPs, Ethernet Switches, Routers, DSLAMs, and Base Stations Ordering Information PART DS31407GN+ TEMP RANGE -40C to +85C PIN-PACKAGE 256 CSBGA +Denotes a lead Pb -free/RoHS-compliant package. SPI is a trademark of Motorola, Inc. • Three Input Clocks • Differential or CMOS/TTL Format • Any Frequency from 2kHz to 750MHz • Fractional Scaling for 64B/66B and FEC Scaling e.g., 64/66, 237/255, 238/255 or Any Other Downscaling Requirement • Continuous Input Clock Quality Monitoring • Automatic or Manual Clock Selection • Three 2/4/8kHz Frame Sync Inputs • High-Performance DPLL • Hitless Reference Switching on Loss of Input • Automatic or Manual Phase Build-Out • Holdover on Loss of All Inputs • Programmable Bandwidth, 0.5mHz to 400Hz • Two Digital Frequency Synthesizers • Produce Any 2kHz Multiple Up to 77.76MHz • Per-DFS Clock Phase Adjust • High-Performance Output APLL • Output Frequencies to 750MHz • High Resolution Fractional Scaling for FEC and 64B/66B e.g., 255/237, 255/238, 66/64 or Any Other Scaling Requirement • Less than 1ps RMS Output Jitter • Four Output Clocks in Two Groups • Nearly Any Frequency from < 1Hz to 750MHz • Each Group Slaves to a DFS Clock, an APLL Clock, or Any Input Clock Divided and Scaled • Each Has a Differential Output 1 CML, 1 LVDS/ LVPECL and Separate CMOS/TTL Output • 32-Bit Frequency Divider Per Output • Two Sync Pulse Outputs 8kHz and 2kHz • General Features • Suitable Line Card IC or Timing Card IC for Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU • Accepts and Produces Nearly Any Frequency Up to 750MHz Including 1Hz, 2kHz, 8kHz, NxDS1, NxE1, DS2/J2, DS3, E3, 2.5M, 25M, 125M, 156.25M, and Nx19.44M Up to 622.08M • Internal Compensation for Local Oscillator Frequency Error • SPI Processor Interface • 1.8V Operation with 3.3V I/O 5V Tolerant Maxim Integrated Products 1 ABRIDGED DATA SHEET Application Example DS31407 Block Diagram SYNC1 SYNC2 SYNC3 IC1 POS/NEG IC2 POS/NEG IC3 POS/NEG DS31407 PLL Bypass Input Clock Block Frequency Scaler, 3 Activity Monitor, Freq. Monitor, Optional Inversion per input clock status Clock Selector DPLL Filtering, Holdover, Hitless Switching, PBO, Frequency Conversion, Manual Phase Adjust MFSYNC DFS Muxes DFS 1 APLL1 FSYNC MFSYNC Divider Muxes Divider 1 lowest jitter path Dif Mux OC1 OC1POS/NEG DFS 4 Divider 4 OC4 OC4POS/NEG JTRST JTMS JTCLK JTDI JTDO JTAG Microprocessor Port SPI Serial and HW Control and Status Pins Master Clock APLL MCLKOSC Local Oscillator TCXO or OCXO RST TEST SRCSW INTREQ SRFAIL LOCK GPIO[4:1] CS SCLK SDO SDI

PDF Datasheet Preview

ABRIDGED DATA SHEET

DS31407 3-Input, 4-Output, Single DPLL Timing IC
with Sub-ps Output Jitter

The DS31407 is a flexible, high-performance timing IC for diverse frequency conversion and frequency synthesis applications. On each of its three input clocks and four output clocks, the device can accept or generate nearly any frequency between 2kHz and 750MHz.

The input clocks are divided down, fractionally scaled as needed, and continuously monitored for activity and frequency accuracy. The best input clock is selected, manually or automatically, as the reference clock for the rest of the device. A flexible, high-performance digital PLL locks to the selected reference and provides programmable bandwidth, very high resolution holdover capability, and truly hitless switching between input clocks. The digital PLL is followed by a clock synthesis subsystem that has two fully programmable digital frequency synthesis blocks, a high-speed low-jitter APLL, and four output clocks, each with its own 32-bit divider and phase adjustment. The APLL provides fractional scaling and output jitter less than 1ps RMS.

For telecom systems, the DS31407 has all required features and functions to serve as a central timing function or as a line card timing IC. With a suitable oscillator the DS31407 meets the requirements of Stratum 2, 3E, 3, 4E, and 4, G.812 Types G.813, and G.8262.

Frequency Conversion Applications in a Wide Variety of Equipment Types

Telecom Line Cards or Timing Cards with Any Mix of SONET/SDH, Synchronous Ethernet and/or OTN Ports in WAN Equipment Including MSPPs, Ethernet Switches, Routers, DSLAMs, and Base Stations
Ordering Information

PART DS31407GN+

TEMP RANGE -40C to +85C

PIN-PACKAGE 256 CSBGA
+Denotes a lead Pb -free/RoHS-compliant package. SPI is a trademark of Motorola, Inc.
• Three Input Clocks
• Differential or CMOS/TTL Format
• Any Frequency from 2kHz to 750MHz
• Fractional Scaling for 64B/66B and FEC

Scaling e.g., 64/66, 237/255, 238/255 or Any Other Downscaling Requirement
• Continuous Input Clock Quality Monitoring
• Automatic or Manual Clock Selection
• Three 2/4/8kHz Frame Sync Inputs
• High-Performance DPLL
• Hitless Reference Switching on Loss of Input
• Automatic or Manual Phase Build-Out
• Holdover on Loss of All Inputs
• Programmable Bandwidth, 0.5mHz to 400Hz
• Two Digital Frequency Synthesizers
• Produce Any 2kHz Multiple Up to 77.76MHz
• Per-DFS Clock Phase Adjust
• High-Performance Output APLL
• Output Frequencies to 750MHz
• High Resolution Fractional Scaling for FEC
and 64B/66B e.g., 255/237, 255/238, 66/64 or Any Other Scaling Requirement
• Less than 1ps RMS Output Jitter
• Four Output Clocks in Two Groups
• Nearly Any Frequency from < 1Hz to 750MHz
• Each Group Slaves to a DFS Clock, an APLL

Clock, or Any Input Clock Divided and Scaled
• Each Has a Differential Output 1 CML, 1 LVDS/

LVPECL and Separate CMOS/TTL Output
• 32-Bit Frequency Divider Per Output
• Two Sync Pulse Outputs 8kHz and 2kHz
• General Features
• Suitable Line Card IC or Timing Card IC for Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU
• Accepts and Produces Nearly Any Frequency Up to 750MHz Including 1Hz, 2kHz, 8kHz, NxDS1, NxE1, DS2/J2, DS3, E3, 2.5M, 25M, 125M, 156.25M, and Nx19.44M Up to 622.08M
• Internal Compensation for Local Oscillator Frequency Error
• SPI Processor Interface
• 1.8V Operation with 3.3V I/O 5V Tolerant

Maxim Integrated Products 1
ABRIDGED DATA SHEET

Application Example

DS31407

Block Diagram

SYNC1 SYNC2 SYNC3

IC1 POS/NEG IC2 POS/NEG IC3 POS/NEG

DS31407

PLL Bypass

Input Clock Block

Frequency Scaler, 3

Activity Monitor,

Freq. Monitor,

Optional Inversion per input clock
status

Clock Selector

DPLL

Filtering, Holdover, Hitless Switching, PBO, Frequency Conversion, Manual Phase Adjust

MFSYNC

DFS Muxes

DFS 1

APLL1

FSYNC MFSYNC

Divider Muxes

Divider 1
lowest jitter path

Dif Mux

OC1 OC1POS/NEG

DFS 4

Divider 4

OC4 OC4POS/NEG

JTRST JTMS JTCLK

JTDI JTDO

JTAG

Microprocessor Port SPI Serial
and HW Control and Status Pins

Master Clock APLL

MCLKOSC

Local Oscillator TCXO or OCXO

RST TEST SRCSW INTREQ SRFAIL LOCK GPIO[4:1]

CS SCLK

SDO SDI

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Datasheet ID: DS31407GN+ 647184