DS31406GN+

DS31406GN+ Datasheet

The DS31406 is a flexible, high-performance timing IC for diverse frequency conversion and frequency synthesis applications. On each of its two input clocks and fourteen output clocks, the device can accept or generate nearly any frequency between 2kHz and 750MHz.

Part	Datasheet
DS31406GN+	DS31406GN+ (pdf)

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ABRIDGED DATA SHEET 2-Input, The DS31406 is a flexible, high-performance timing IC for diverse frequency conversion and frequency synthesis applications. On each of its two input clocks and fourteen output clocks, the device can accept or generate nearly any frequency between 2kHz and 750MHz. The input clocks are divided down, fractionally scaled as needed, and continuously monitored for activity and frequency accuracy. The best input clock is selected, manually or automatically, as the reference clock for the rest of the device. A flexible, high-performance digital PLL locks to the selected reference and provides programmable bandwidth, very high resolution holdover capability, and truly hitless switching between input clocks. The digital PLL is followed by a clock synthesis subsystem which has seven fully programmable digital frequency synthesis blocks, three high-speed low-jitter APLLs, and 14 output clocks, each with its own 32-bit divider and phase adjustment. The APLLs provide fractional scaling and output jitter less than 1ps RMS. For telecom systems, the DS31406 has all required features and functions to serve as a central timing function or as a line card timing IC. With a suitable oscillator the DS31406 meets the requirements of Stratum 2, 3E, 3, 4E, and 4, G.812 Types G.813, and G.8262. Frequency Conversion Applications in a Wide Variety of Equipment Types Telecom Line Cards or Timing Cards with Any Mix of SONET/SDH, Synchronous Ethernet and/or OTN Ports in WAN Equipment Including MSPPs, Ethernet Switches, Routers, DSLAMs, and Base Stations Ordering Information PART DS31406GN+ TEMP RANGE -40C to +85C PIN-PACKAGE 256 CSBGA +Denotes a lead Pb -free/RoHS-compliant package. SPI is a trademark of Motorola, Inc. • Two Input Clocks • Differential or CMOS/TTL Format • Any Frequency from 2kHz to 750MHz • Fractional Scaling for 64B/66B and FEC Scaling e.g., 64/66, 237/255, 238/255 or Any Other Downscaling Requirement • Continuous Input Clock Quality Monitoring • Automatic or Manual Clock Selection • Two 2/4/8kHz Frame Sync Inputs • High-Performance DPLL • Hitless Reference Switching on Loss of Input • Automatic or Manual Phase Build-Out • Holdover on Loss of All Inputs • Programmable Bandwidth, 0.5mHz to 400Hz • Seven Digital Frequency Synthesizers • Produce Any 2kHz Multiple Up to 77.76MHz • Per-DFS Clock Phase Adjust • Three Output APLLs • Output Frequencies to 750MHz • High Resolution Fractional Scaling for FEC and 64B/66B e.g., 255/237, 255/238, 66/64 or Any Other Scaling Requirement • Less than 1ps RMS Output Jitter • Simultaneously Produce Three Low-Jitter Rates from the Same Reference e.g., 622.08MHz for SONET, 255/237*622.08MHz for OTU2, and 156.25MHz for 10GE • 14 Output Clocks in Seven Groups • Nearly Any Frequency from <1Hz to 750MHz • Each Group Slaves to a DFS Clock, Any APLL Clock, or Any Input Clock Divided and Scaled • Each Has a Differential Output 3 CML, 4 LVDS/ LVPECL and Separate CMOS/TTL Output • 32-Bit Frequency Divider Per Output • Two Sync Pulse Outputs 8kHz and 2kHz • General Features • Suitable Line Card IC or Timing Card IC for Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU • Accepts and Produces Nearly Any Frequency Up to 750MHz Including 1Hz, 2kHz, 8kHz, NxDS1, NxE1, DS2/J2, DS3, E3, 2.5M, 25M, 125M, 156.25M, and Nx19.44M Up to 622.08M • Internal Compensation for Local Oscillator Frequency Error • SPI Processor Interface • 1.8V Operation with 3.3V I/O 5V Tolerant Maxim Integrated Products 1 ABRIDGED DATA SHEET Application Example DS31406 ABRIDGED DATA SHEET Block Diagram DS31406 SYNC1 SYNC2 DS31406 IC1 POS/NEG IC2 POS/NEG Input Clock Block Frequency Scaler, 8 Activity Monitor, Freq. Monitor, Optional Inversion per input clock status JTRST JTMS JTCLK JTDI JTDO JTAG PLL Bypass DPLL Filtering, Holdover, Hitless Switching, PBO, Frequency Conversion, Manual Phase Adjust MFSYNC DFS Muxes DFS 1 DFS 2 DFS 3 APLL1 APLL2 APLL3 DFS 4 Clock Selector DFS 5 DFS 6 Microprocessor Port SPI Serial and HW Control and Status Pins DFS 7 Master Clock APLL FSYNC MFSYNC Divider Muxes Dif Muxes Divider 1 lowest jitter path OC1 OC1POS/NEG Divider 2 lowest jitter path OC2 OC2POS/NEG Divider 3 lowest jitter path

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ABRIDGED DATA SHEET
2-Input,

The DS31406 is a flexible, high-performance timing IC for diverse frequency conversion and frequency synthesis applications. On each of its two input clocks and fourteen output clocks, the device can accept or generate nearly any frequency between 2kHz and 750MHz.

The input clocks are divided down, fractionally scaled as needed, and continuously monitored for activity and frequency accuracy. The best input clock is selected, manually or automatically, as the reference clock for the rest of the device. A flexible, high-performance digital PLL locks to the selected reference and provides programmable bandwidth, very high resolution holdover capability, and truly hitless switching between input clocks. The digital PLL is followed by a clock synthesis subsystem which has seven fully programmable digital frequency synthesis blocks, three high-speed low-jitter APLLs, and 14 output clocks, each with its own 32-bit divider and phase adjustment. The APLLs provide fractional scaling and output jitter less than 1ps RMS.

For telecom systems, the DS31406 has all required features and functions to serve as a central timing function or as a line card timing IC. With a suitable oscillator the DS31406 meets the requirements of Stratum 2, 3E, 3, 4E, and 4, G.812 Types G.813, and G.8262.

Frequency Conversion Applications in a Wide Variety of Equipment Types

Telecom Line Cards or Timing Cards with Any Mix of SONET/SDH, Synchronous Ethernet and/or OTN Ports in WAN Equipment Including MSPPs, Ethernet Switches, Routers, DSLAMs, and Base Stations
Ordering Information

PART DS31406GN+

TEMP RANGE -40C to +85C

PIN-PACKAGE 256 CSBGA
+Denotes a lead Pb -free/RoHS-compliant package.

SPI is a trademark of Motorola, Inc.
• Two Input Clocks
• Differential or CMOS/TTL Format
• Any Frequency from 2kHz to 750MHz
• Fractional Scaling for 64B/66B and FEC Scaling
e.g., 64/66, 237/255, 238/255 or Any Other Downscaling Requirement
• Continuous Input Clock Quality Monitoring
• Automatic or Manual Clock Selection
• Two 2/4/8kHz Frame Sync Inputs
• High-Performance DPLL
• Hitless Reference Switching on Loss of Input
• Automatic or Manual Phase Build-Out
• Holdover on Loss of All Inputs
• Programmable Bandwidth, 0.5mHz to 400Hz
• Seven Digital Frequency Synthesizers
• Produce Any 2kHz Multiple Up to 77.76MHz
• Per-DFS Clock Phase Adjust
• Three Output APLLs
• Output Frequencies to 750MHz
• High Resolution Fractional Scaling for FEC and
64B/66B e.g., 255/237, 255/238, 66/64 or Any Other Scaling Requirement
• Less than 1ps RMS Output Jitter
• Simultaneously Produce Three Low-Jitter Rates from the Same Reference e.g., 622.08MHz for SONET, 255/237*622.08MHz for OTU2, and 156.25MHz for 10GE
• 14 Output Clocks in Seven Groups
• Nearly Any Frequency from <1Hz to 750MHz
• Each Group Slaves to a DFS Clock, Any APLL

Clock, or Any Input Clock Divided and Scaled
• Each Has a Differential Output 3 CML, 4 LVDS/

LVPECL and Separate CMOS/TTL Output
• 32-Bit Frequency Divider Per Output
• Two Sync Pulse Outputs 8kHz and 2kHz
• General Features
• Suitable Line Card IC or Timing Card IC for Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU
• Accepts and Produces Nearly Any Frequency Up to 750MHz Including 1Hz, 2kHz, 8kHz, NxDS1, NxE1, DS2/J2, DS3, E3, 2.5M, 25M, 125M, 156.25M, and Nx19.44M Up to 622.08M
• Internal Compensation for Local Oscillator Frequency Error
• SPI Processor Interface
• 1.8V Operation with 3.3V I/O 5V Tolerant

Maxim Integrated Products 1
ABRIDGED DATA SHEET

Application Example

DS31406

ABRIDGED DATA SHEET

Block Diagram

DS31406

SYNC1 SYNC2

DS31406

IC1 POS/NEG IC2 POS/NEG

Input Clock Block

Frequency Scaler, 8 Activity Monitor, Freq. Monitor, Optional Inversion per input clock
status

JTRST JTMS JTCLK JTDI JTDO

JTAG

PLL Bypass

DPLL

Filtering, Holdover, Hitless Switching, PBO, Frequency Conversion, Manual Phase Adjust

MFSYNC

DFS Muxes

DFS 1

DFS 2

DFS 3

APLL1 APLL2 APLL3

DFS 4

Clock Selector

DFS 5 DFS 6

Microprocessor Port SPI Serial
and HW Control and Status Pins

DFS 7

Master Clock APLL

FSYNC MFSYNC

Divider Muxes

Dif Muxes

Divider 1
lowest jitter path

OC1 OC1POS/NEG

Divider 2
lowest jitter path

OC2 OC2POS/NEG

Divider 3
lowest jitter path

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Datasheet ID: DS31406GN+ 647183