DS3102GN+

DS3102GN+ Datasheet

DS3102 Stratum 2/3E/3 Timing Card IC with

Part	Datasheet
DS3102GN+	DS3102GN+ (pdf)

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DS3102 Stratum 2/3E/3 Timing Card IC with Synchronous Ethernet Support The DS3102 is a low-cost, feature-rich timing IC for telecom timing cards. With 8 input clocks, the device directly accepts both line timing from a large number of line cards and external timing from external DS1/E1 BITS transceivers. The DS3102 continually monitors all input clocks and performs automatic hitless reference switching if the primary reference fails. The T0 DPLL complies with the Stratum 2, 3E, 3, 4E and 4 requirements of GR-1244, GR-253, G.812 Types I IV, G.813 and G.8262. The highly programmable DS3102 support numerous input and output frequencies including rates required for SONET/SDH, Synchronous Ethernet 1G, 10G, and 100Mbps , wireless base stations, and CMTS systems. PLL bandwidths from 0.5mHz to 400Hz are supported, and a wide variety of PLL characteristics and device features can be configured to meet the needs of many different applications. Two DS3102 devices can be configured in a master/slave arrangement for timing card equipment protection. The DS3102 register set is backward compatible with Semtech’s ACS8522 timing card IC. The DS3102 has a different package and pin arrangement than the ACS8522. SONET/SDH Equipment Clocks SECs Synchronous Ethernet Equipment Clocks EECs Timing Card IC in WAN Equipment Including MSPPs, Ethernet Switches, Routers, DSLAMs, and Wireless Base Stations Ordering Information PART DS3102GN+ TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 81 CSBGA 10mm 2 81 CSBGA 10mm 2 +Denotes a lead Pb -free/RoHS-compliant package. SPI is a trademark of Motorola, Inc. • Synchronization for Stratum 2, 3E, 3, 4E and 4 plus SMC, SEC and EEC • Meets Requirements of GR-1244 Stratum 2 4, GR-253, G.812 Types I IV, G.813, and G.8262 • Stratum 2, 3E or 3 Holdover Accuracy with Suitable External Oscillator • Programmable Bandwidth 0.5mHz to 400Hz • Hitless Reference Switching on Loss of Input • Automatic or Manual Phase Build-Out • Frequency Conversion Among SONET/SDH, PDH, Ethernet, Wireless, and CMTS Rates • 8 Input Clocks • Four CMOS/TTL Inputs 125MHz • Four LVDS/LVPECL/CMOS/TTL Inputs 156.25MHz • Three Optional Frame-Sync Inputs CMOS/TTL • Continuous Input Clock Quality Monitoring • Numerous Input Clock Frequencies Supported: SONET/SDH N x N x 51.84MHz Ethernet xMII 25, 125, 156.25MHz PDH N x DS1, N x E1, N x DS2, DS3, E3 Frame Sync 2kHz, 4kHz, 8kHz Custom Any Multiple of 2kHz Up to 131.072MHz, Any Multiple of 8kHz Up to 155.52MHz • 7 Output Clocks • Three CMOS/TTL Outputs 125MHz • Two LVDS/LVPECL Outputs 312.50MHz • Two Dual CMOS/TTL and LVDS/LVPECL Outputs • Five CMOS Outputs Have Additional Output Pins That Can Be Powered at 2.5V or 3.3V • Numerous Output Clock Frequencies Supported: SONET/SDH N x N x 51.84MHz Ethernet xMII 25, 125, 312.5MHz PDH N x DS1, N x E1, N x DS2, DS3, E3 Other 10, 13, 30.72MHz Frame Sync 2kHz, 8kHz Custom Clock Rates Any Multiple of 2kHz Up to 77.76MHz, Any Multiple of 8kHz Up to 311.04MHz, Any Multiple of 10kHz Up to 388.79MHz • General • Internal Compensation for Master Clock Oscillator • SPI Processor Interface • 1.8V Operation with 3.3V I/O 5V Tolerant • Industrial Temperature Range Maxim Integrated Products 1 DS3102 Table of Contents STANDARDS COMPLIANCE APPLICATION EXAMPLE BLOCK DIAGRAM DETAILED DESCRIPTION DETAILED FEATURES INPUT CLOCK FEATURES T0 DPLL T4 DPLL OUTPUT APLL FEATURES OUTPUT CLOCK REDUNDANCY FEATURES GENERAL FEATURES PIN DESCRIPTIONS FUNCTIONAL DESCRIPTION OVERVIEW DEVICE IDENTIFICATION AND PROTECTION LOCAL OSCILLATOR AND MASTER CLOCK INPUT CLOCK CONFIGURATION Signal Format Configuration 19 Frequency 20 INPUT CLOCK Frequency Monitoring 21 Activity Monitoring 21 Selected Reference Activity Monitoring 22 INPUT CLOCK PRIORITY, SELECTION, AND SWITCHING Priority 23 Automatic Selection Algorithm 23 Forced Selection 24 Ultra-Fast Reference Switching 24 External Reference Switching 24 Output Clock Phase Continuity During Reference Switching 25 Frequency Monitoring Hysteresis Required by Telcordia 25 DPLL ARCHITECTURE AND CONFIGURATION T0 DPLL State Machine 27 T4 DPLL State Machine 30 Bandwidth 32 Damping 32 Phase 32 Loss-of-Lock Detection 33 Phase Build-Out 34 Input to Output Manual Phase 35 Phase Recalibration 35 Frequency and Phase 35 Input Jitter and Wander 37 Jitter and Wander Transfer 37 Output Jitter and Wander 38 OUTPUT CLOCK Signal Format Configuration 39 Frequency 39 2 of 142 DS3102 EQUIPMENT REDUNDANCY Master-Slave Output Clock-Phase Alignment 46 Master-Slave Frame and Multiframe Alignment with the External Frame-Sync Signals 47 SYNCn Pins 49 Other Configuration Options 50 MICROPROCESSOR INTERFACE RESET POWER-SUPPLY REGISTER DESCRIPTIONS STATUS CONFIGURATION FIELDS MULTIREGISTER REGISTER DEFINITIONS JTAG TEST ACCESS PORT AND BOUNDARY SCAN JTAG DESCRIPTION JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION JTAG INSTRUCTION REGISTER AND INSTRUCTIONS JTAG TEST REGISTERS ELECTRICAL DC CHARACTERISTICS INPUT CLOCK TIMING OUTPUT CLOCK SPI INTERFACE TIMING JTAG INTERFACE TIMING RESET PIN TIMING PIN ASSIGNMENTS PACKAGE INFORMATION ACRONYMS AND ABBREVIATIONS 3 of 142 DS3102 List of Figures Figure Typical Application Example 7 Figure Block Diagram 8 Figure DPLL Block Diagram 26 Figure T0 DPLL State Transition Diagram 28 Figure T4 DPLL State Transition Diagram 31 Figure FSYNC 8kHz 45 Figure SPI Clock Phase Options 51 Figure SPI Bus 52 Figure JTAG Block 124 Figure JTAG TAP Controller State Machine 126 Figure Recommended Termination for LVDS Pins 131 Figure Recommended Termination for LVPECL Signals on LVDS Input Pins 131 Figure Recommended Termination for LVPECL-Compatible Output Pins 132 Figure SPI Interface Timing Diagram 135 Figure JTAG Timing 136 Figure Reset Pin Timing Diagram 137 Figure Pin Assignment 139 4 of 142 DS3102 List of Tables Table Applicable Telecom 6 Table Input Clock Pin Descriptions 13 Table Output Clock Pin 14 Table Global Pin Descriptions 15 Table SPI Bus Mode Pin Descriptions 15 Table JTAG Interface Pin Descriptions 16 Table Power-Supply Pin Descriptions 16 Table GR-1244 Stratum 2/3E/3 Stability 18 Table Input Clock Capabilities 19 Table Locking Frequency Modes 20 Table Default Input Clock Priorities 23 Table Damping Factors and Peak Jitter/Wander 32 Table T0 DPLL Adaptation for the T4 DPLL Phase Measurement Mode 37 Table Output Clock Capabilities 38 Table Digital1 40 Table Digital2 41 Table APLL Frequency to Output Frequencies T0 APLL and T4 APLL 41 Table T0 APLL Frequency Configuration 41 Table T0 APLL2 Frequency Configuration 41 Table T4 APLL Frequency Configuration 42 Table OC1 to OC7 Output Frequency Selection 42 Table Standard Frequencies for Programmable Outputs 43 Table Equipment Redundancy Methodology 46 Table External Frame-Sync Mode and Source 48 Table External Frame-Sync Source 49 Table Register Map 55 Table JTAG Instruction Codes 127 Table JTAG ID Code 128 Table Recommended DC Operating Conditions 129 Table DC 129 Table CMOS/TTL Pins 130 Table LVDS/LVPECL Input Pins 130 Table LVDS Output Pins 130 Table LVPECL Level-Compatible Output 131 Table Input Clock 133 Table Input Clock to Output Clock Delay 133 Table Output Clock Phase Alignment, Frame-Sync Alignment 133 Table SPI Interface Timing 134 Table JTAG Interface 136 Table Reset Pin Timing 137 Table Pin Assignments Sorted by Signal 138 Table CSBGA Package Thermal Properties, Natural Convection 140 5 of 142 DS3102 Standards Compliance Table Applicable Telecom Standards SPECIFICATION

PDF Datasheet Preview

DS3102 Stratum 2/3E/3 Timing Card IC with

Synchronous Ethernet Support

The DS3102 is a low-cost, feature-rich timing IC for telecom timing cards. With 8 input clocks, the device directly accepts both line timing from a large number of line cards and external timing from external DS1/E1 BITS transceivers. The DS3102 continually monitors all input clocks and performs automatic hitless reference switching if the primary reference fails. The T0 DPLL complies with the Stratum 2, 3E, 3, 4E and 4 requirements of GR-1244, GR-253, G.812 Types I IV, G.813 and G.8262. The highly programmable DS3102 support numerous input and output frequencies including rates required for SONET/SDH, Synchronous Ethernet 1G, 10G, and 100Mbps , wireless base stations, and CMTS systems. PLL bandwidths from 0.5mHz to 400Hz are supported, and a wide variety of PLL characteristics and device features can be configured to meet the needs of many different applications. Two DS3102 devices can be configured in a master/slave arrangement for timing card equipment protection.

The DS3102 register set is backward compatible with Semtech’s ACS8522 timing card IC. The DS3102 has a different package and pin arrangement than the ACS8522.

SONET/SDH Equipment Clocks SECs Synchronous Ethernet Equipment Clocks EECs Timing Card IC in WAN Equipment Including MSPPs,

Ethernet Switches, Routers, DSLAMs, and Wireless Base Stations
Ordering Information

PART DS3102GN+

TEMP RANGE -40C to +85C -40C to +85C

PIN-PACKAGE 81 CSBGA 10mm 2 81 CSBGA 10mm 2
+Denotes a lead Pb -free/RoHS-compliant package.

SPI is a trademark of Motorola, Inc.
• Synchronization for Stratum 2, 3E, 3, 4E and 4 plus SMC, SEC and EEC
• Meets Requirements of GR-1244 Stratum 2 4, GR-253, G.812 Types I IV, G.813, and G.8262
• Stratum 2, 3E or 3 Holdover Accuracy with Suitable External Oscillator
• Programmable Bandwidth 0.5mHz to 400Hz
• Hitless Reference Switching on Loss of Input
• Automatic or Manual Phase Build-Out
• Frequency Conversion Among SONET/SDH,

PDH, Ethernet, Wireless, and CMTS Rates
• 8 Input Clocks
• Four CMOS/TTL Inputs 125MHz
• Four LVDS/LVPECL/CMOS/TTL Inputs
156.25MHz
• Three Optional Frame-Sync Inputs CMOS/TTL
• Continuous Input Clock Quality Monitoring
• Numerous Input Clock Frequencies Supported:

SONET/SDH N x N x 51.84MHz Ethernet xMII 25, 125, 156.25MHz PDH N x DS1, N x E1, N x DS2, DS3, E3 Frame Sync 2kHz, 4kHz, 8kHz Custom Any Multiple of 2kHz Up to 131.072MHz,

Any Multiple of 8kHz Up to 155.52MHz
• 7 Output Clocks
• Three CMOS/TTL Outputs 125MHz
• Two LVDS/LVPECL Outputs 312.50MHz
• Two Dual CMOS/TTL and LVDS/LVPECL Outputs
• Five CMOS Outputs Have Additional Output Pins

That Can Be Powered at 2.5V or 3.3V
• Numerous Output Clock Frequencies Supported:

SONET/SDH N x N x 51.84MHz Ethernet xMII 25, 125, 312.5MHz PDH N x DS1, N x E1, N x DS2, DS3, E3 Other 10, 13, 30.72MHz Frame Sync 2kHz, 8kHz Custom Clock Rates Any Multiple of 2kHz Up to
77.76MHz, Any Multiple of 8kHz Up to 311.04MHz, Any Multiple of 10kHz Up to 388.79MHz
• General
• Internal Compensation for Master Clock Oscillator
• SPI Processor Interface
• 1.8V Operation with 3.3V I/O 5V Tolerant
• Industrial Temperature Range

Maxim Integrated Products 1
DS3102

Table of Contents

STANDARDS COMPLIANCE

APPLICATION EXAMPLE

BLOCK DIAGRAM

DETAILED DESCRIPTION

DETAILED FEATURES

INPUT CLOCK FEATURES T0 DPLL T4 DPLL OUTPUT APLL FEATURES OUTPUT CLOCK REDUNDANCY FEATURES GENERAL FEATURES

PIN DESCRIPTIONS

FUNCTIONAL DESCRIPTION

OVERVIEW DEVICE IDENTIFICATION AND PROTECTION LOCAL OSCILLATOR AND MASTER CLOCK INPUT CLOCK CONFIGURATION

Signal Format Configuration 19 Frequency 20 INPUT CLOCK Frequency Monitoring 21 Activity Monitoring 21 Selected Reference Activity Monitoring 22 INPUT CLOCK PRIORITY, SELECTION, AND SWITCHING Priority 23 Automatic Selection Algorithm 23 Forced Selection 24 Ultra-Fast Reference Switching 24 External Reference Switching 24 Output Clock Phase Continuity During Reference Switching 25 Frequency Monitoring Hysteresis Required by Telcordia 25 DPLL ARCHITECTURE AND CONFIGURATION T0 DPLL State Machine 27 T4 DPLL State Machine 30 Bandwidth 32 Damping 32 Phase 32 Loss-of-Lock Detection 33 Phase Build-Out 34 Input to Output Manual Phase 35 Phase Recalibration 35 Frequency and Phase 35 Input Jitter and Wander 37 Jitter and Wander Transfer 37 Output Jitter and Wander 38 OUTPUT CLOCK Signal Format Configuration 39 Frequency 39
2 of 142

DS3102

EQUIPMENT REDUNDANCY

Master-Slave Output Clock-Phase Alignment 46

Master-Slave Frame and Multiframe Alignment with the External Frame-Sync Signals 47

SYNCn Pins 49

Other Configuration Options 50 MICROPROCESSOR INTERFACE RESET POWER-SUPPLY

REGISTER DESCRIPTIONS

STATUS CONFIGURATION FIELDS MULTIREGISTER REGISTER DEFINITIONS

JTAG TEST ACCESS PORT AND BOUNDARY SCAN

JTAG DESCRIPTION JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION JTAG INSTRUCTION REGISTER AND INSTRUCTIONS JTAG TEST REGISTERS

ELECTRICAL

DC CHARACTERISTICS INPUT CLOCK TIMING OUTPUT CLOCK SPI INTERFACE TIMING JTAG INTERFACE TIMING RESET PIN TIMING

PIN ASSIGNMENTS

PACKAGE INFORMATION

ACRONYMS AND ABBREVIATIONS
3 of 142

DS3102

List of Figures

Figure Typical Application Example 7 Figure Block Diagram 8 Figure DPLL Block Diagram 26 Figure T0 DPLL State Transition Diagram 28 Figure T4 DPLL State Transition Diagram 31 Figure FSYNC 8kHz 45 Figure SPI Clock Phase Options 51 Figure SPI Bus 52 Figure JTAG Block 124 Figure JTAG TAP Controller State Machine 126 Figure Recommended Termination for LVDS Pins 131 Figure Recommended Termination for LVPECL Signals on LVDS Input Pins 131 Figure Recommended Termination for LVPECL-Compatible Output Pins 132 Figure SPI Interface Timing Diagram 135 Figure JTAG Timing 136 Figure Reset Pin Timing Diagram 137 Figure Pin Assignment 139
4 of 142

DS3102

List of Tables

Table Applicable Telecom 6 Table Input Clock Pin Descriptions 13 Table Output Clock Pin 14 Table Global Pin Descriptions 15 Table SPI Bus Mode Pin Descriptions 15 Table JTAG Interface Pin Descriptions 16 Table Power-Supply Pin Descriptions 16 Table GR-1244 Stratum 2/3E/3 Stability 18 Table Input Clock Capabilities 19 Table Locking Frequency Modes 20 Table Default Input Clock Priorities 23 Table Damping Factors and Peak Jitter/Wander 32 Table T0 DPLL Adaptation for the T4 DPLL Phase Measurement Mode 37 Table Output Clock Capabilities 38 Table Digital1 40 Table Digital2 41 Table APLL Frequency to Output Frequencies T0 APLL and T4 APLL 41 Table T0 APLL Frequency Configuration 41 Table T0 APLL2 Frequency Configuration 41 Table T4 APLL Frequency Configuration 42 Table OC1 to OC7 Output Frequency Selection 42 Table Standard Frequencies for Programmable Outputs 43 Table Equipment Redundancy Methodology 46 Table External Frame-Sync Mode and Source 48 Table External Frame-Sync Source 49 Table Register Map 55 Table JTAG Instruction Codes 127 Table JTAG ID Code 128 Table Recommended DC Operating Conditions 129 Table DC 129 Table CMOS/TTL Pins 130 Table LVDS/LVPECL Input Pins 130 Table LVDS Output Pins 130 Table LVPECL Level-Compatible Output 131 Table Input Clock 133 Table Input Clock to Output Clock Delay 133 Table Output Clock Phase Alignment, Frame-Sync Alignment 133 Table SPI Interface Timing 134 Table JTAG Interface 136 Table Reset Pin Timing 137 Table Pin Assignments Sorted by Signal 138 Table CSBGA Package Thermal Properties, Natural Convection 140
5 of 142

DS3102

Standards Compliance

Table Applicable Telecom Standards

SPECIFICATION

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Datasheet ID: DS3102GN+ 647179