PC28F256G18FE

PC28F256G18FE Datasheet

P/N PC28F128G18xx P/N PC28F256G18xx P/N PC28F512G18xx P/N PC28F00AG18xx

Part	Datasheet
PC28F256G18FE	PC28F256G18FE (pdf)

Related Parts	Information
PC28F128G18AE	PC28F128G18AE
PC28F128G18FE	PC28F128G18FE
PC28F512G18FE	PC28F512G18FE
PC28F128G18FF TR	PC28F128G18FF TR
PC28F256G18AE	PC28F256G18AE
PC28F00AG18FF TR	PC28F00AG18FF TR
PC28F00AG18FE	PC28F00AG18FE
PC28F256G18AF TR	PC28F256G18AF TR
PC28F512G18AE	PC28F512G18AE
PC28F00AG18AE	PC28F00AG18AE
PC28F512G18FF TR	PC28F512G18FF TR
PC28F256G18FF TR	PC28F256G18FF TR

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128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory Features Micron StrataFlash Embedded Memory P/N PC28F128G18xx P/N PC28F256G18xx P/N PC28F512G18xx P/N PC28F00AG18xx • High-Performance Read, Program and Erase 96 ns initial read access 108 MHz with zero wait-state synchronous burst reads 7 ns clock-to-data output 133 MHz with zero wait-state synchronous burst reads ns clock-to-data output 8-, 16-, and continuous-word synchronous-burst Reads Programmable WAIT configuration Customer-configurable output driver impedance Buffered Programming us/Word typ , 512Mbit 65 nm Block Erase s per block typ 20 us typ program/erase suspend • Architecture 16-bit wide data bus Multi-Level Cell Technology Symmetrically-Blocked Array Architecture 256-Kbyte Erase Blocks 1-Gbit device Eight 128-Mbit partitions 512-Mbit device Eight 64-Mbit partitions 256-Mbit device Eight 32-Mbit partitions 128-Mbit device Eight 16-Mbit partitions Read-While-Program and Read-While-Erase Status Register for partition/device status Blank Check feature • Quality and Reliability Expanded temperature °C to +85 °C Minimum 100,000 erase cycles per block 65nm Process Technology • Power Core voltage V - V I/O voltage V - V Standby current 60 uA typ for 512-Mbit, 65 nm Deep Power-Down mode 2 uA typ Automatic Power Savings mode 16-word synchronous-burst read current 23 mA typ 108 MHz 24 mA typ 133 MHz • Software Flash data integrator FDI optimized Basic command set BCS and extended command set ECS compatible Common Flash interface CFI capable • Security One-time programmable OTP space 64 unique factory device identifier bits 2112 user-programmable OTP bits Absolute write protection VPP = GND Power-transition erase/program lockout Individual zero latency block locking Individual block lock-down • Density and packaging 128Mb, 256Mb, 512Mbit, and 1-Gbit Address-data multiplexed and non-multiplexed interfaces 64-Ball Easy BGA Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory Features Contents General Description 8 Functional Overview 8 Configuration and Memory Map 9 Device ID 12 Package Dimensions 13 Signal Assignments 14 Signal Descriptions 15 Bus Interface 16 Reset 16 Standby 16 Output Disable 16 Asynchronous Read 17 Synchronous Read 17 Burst Wrapping 17 End-of-Wordline Delay 18 Write 19 Command Definitions 20 Status Register 23 Clear Status Register 24 Read Configuration Register 25 Programming the Read Configuration Register 26 Extended Configuration Register 27 Output Driver Control 27 Programming the Extended Configuration Register 28 Read Operations 29 Read Array 29 Read ID 29 Read CFI 30 Read Status Register 30 WAIT Operation 31 Programming Modes 32 Control Mode 32 Object Mode 33 Program Operations 37 Single-Word Programming 37 Buffered Programming 38 Buffered Enhanced Factory Programming 38 Erase Operations 41 BLOCK ERASE 41 SUSPEND and RESUME Operations 42 SUSPEND Operation 42 RESUME Operation 43 BLANK CHECK Operation 44 Block Lock 45 One-Time Programmable Operations 47 Programming OTP Area 49 Reading OTP Area 49 Global Main-Array Protection 50 Dual Operation 51 Power and Reset Specifications 52 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory Features Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory Features List of Figures Figure 1 64-Ball Easy BGA 8mm x 10mm x 1.2mm 13 Figure 2 64-Ball Easy BGA Top View, Balls Down 14 Figure 3 Main Array Word Lines 18 Figure 4 Wrap/No-Wrap Example 18 Figure 5 End-of-Wordline Delay 18 Figure 6 Two-Cycle Command Sequence 20 Figure 7 Single-Cycle Command Sequence 20 Figure 8 READ Cycle Between WRITE Cycles 20 Figure 9 Illegal Command Sequence 21 Figure 10 Configurable Programming Regions Control Mode and Object Mode 33 Figure 11 Configurable Programming Regions Control Mode and Object Mode Segments 35 Figure 12 BLOCK LOCK Operations 46 Figure 13 OTP Area Map 48 Figure 14 VPP Supply Connection Example 50 Figure 15 RESET Operation Waveforms 53 Figure 16 AC Input/Output Reference Waveform 60 Figure 17 Transient Equivalent Testing Load Circuit 60 Figure 18 Clock Input AC Waveform 61 Figure 19 Asynchronous Page-Mode Read Non-MUX 64 Figure 20 Synchronous 8- or 16-Word Burst Read Non-MUX 65 Figure 21 Synchronous Continuous Misaligned Burst Read Non-MUX 66 Figure 22 Synchronous Burst with Burst Interrupt Read Non-MUX 67 Figure 23 Asynchronous Single-Word Read 68 Figure 24 Synchronous 8- or 16-Word Burst Read A/D MUX 69 Figure 25 Synchronous Continuous Misaligned Burst Read A/D MUX 70 Figure 26 Synchronous Burst with Burst-Interrupt AD-Mux 70 Figure 27 Write Timing 73 Figure 28 Write to Write Non-Mux 74 Figure 29 Async Read to Write Non-Mux 74 Figure 30 Write to Async Read Non-Mux 75 Figure 31 Sync Read to Write Non-Mux 75 Figure 32 Write to Sync Read Non-Mux 76 Figure 33 Write to Write AD-Mux 76 Figure 34 Async Read to Write AD-Mux 77 Figure 35 Write to Async Read AD-Mux 77 Figure 36 Sync Read to Write AD-Mux 78 Figure 37 Write to Sync Read AD-Mux 78 Figure 38 Word Program Procedure 91 Figure 39 Word Program Full Status Check Procedure 92 Figure 40 Program Suspend/Resume Procedure 93 Figure 41 Buffer Programming Procedure 95 Figure 42 Buffered Enhanced Factory Programming BEFP Procedure 97 Figure 43 Block Erase Procedure 99 Figure 44 Block Erase Full Status Check Procedure 100 Figure 45 Erase Suspend/Resume Procedure 101 Figure 46 Block Lock Operations Procedure 103 Figure 47 Protection Register Programming Procedure 104 Figure 48 Protection Register Programming Full Status Check Procedure 105 Figure 49 Blank Check Procedure 106 Figure 50 Blank Check Full Status Check Procedure 107 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory Features Figure 51 AADM Asynchronous READ Cycle Latching A[MAX:0] 110 Figure 52 AADM Asynchronous READ Cycle Latching A[15:0] only 110 Figure 53 AADM Asynchronous WRITE Cycle Latching A[MAX:0] 111 Figure 54 AADM Asynchronous WRITE Cycle Latching A[15:0] only 112 Figure 55 AADM Synchronous Burst READ Cycle ADV# De-asserted Between Address Cycles 113 Figure 56 AADM Synchronous Burst READ Cycle ADV# Not De-asserted Between Address Cycles 114 Figure 57 AADM Synchronous Burst READ Cycle Latching A[15:0] only 114 Figure 58 Part Number Chart for G18 Components 116 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory Features List of Tables Table 1 Main Array Memory Map 128Mb, 256Mb 9 Table 2 Main Array Memory Map 512Mb, 1Gb 10 Table 3 Device ID Codes 12 Table 4 Signal Descriptions 15 Table 5 Bus Control Signals 16 Table 6 Command Set 21 Table 7 Status Register Bit Definitions Default Value = 0080h 23 Table 8 CLEAR STATUS REGISTER Command Bus Cycles 24 Table 9 Read Configuration Register Bit Definitions Default Value = BFCFh 25 Table 10 Supported Clock Frequencies 25 Table 11 PROGRAM READ CONFIGURATION REGISTER Bus Cycles 26 Table 12 Extended Configuration Register Bit Definitions Default Value = 0004h 27 Table 13 Output Driver Control Characteristics 27 Table 14 Program Extended Configuration Register Command Bus Cycles 28 Table 15 READ MODE Command Bus Cycles 29 Table 16 Device Information 30 Table 17 WAIT Behavior Summary Non-MUX 31 Table 18 WAIT Behavior Summary AD MUX 31 Table 19 Programming Region Next State 36 Table 20 PROGRAM Command Bus Cycles 37 Table 21 BEFP Requirements and Considerations 39 Table 22 ERASE Command Bus Cycle 41 Table 23 Valid Commands During Suspend 42 Table 24 SUSPEND and RESUME Command Bus Cycles 43 Table 25 BLANK CHECK Command Bus Cycles 44 Table 26 BLOCK LOCK Command Bus Cycles 45 Table 27 Block Lock Configuration 46 Table 28 Program OTP Area Command Bus Cycles 47 Table 29 Dual Operation Restrictions 51 Table 30 Power Sequencing 52 Table 31 Reset Specifications 53 Table 32 Absolute Maximum Ratings 55 Table 33 Operating Conditions 55 Table 34 DC Current Characteristics and Operating Conditions 56 Table 35 DC Voltage Characteristics and Operating Conditions 59 Table 36 AC Input Requirements 60 Table 37 Test Configuration Load Capacitor Values for Worst Case Speed Conditions 60 Table 38 Capacitance 61 Table 39 AC Read Specifications CLK-Latching, 133 MHz , VCCQ = 1.7V to 2.0V 62 Table 40 AC Write Specifications 72 Table 41 Program/Erase Characteristics 79 Table 42 Example of CFI Output x16 Device as a Function of Device and Mode 80 Table 43 CFI Database Addresses and Sections 80 Table 44 CFI ID String 81 Table 45 System Interface Information 81 Table 46 Device Geometry 82 Table 47 Block Region Map Information 83 Table 48 Primary Micron-Specific Extended Query 85 Table 49 One Time Programmable OTP Space Information 86 Table 50 Burst Read Informaton 87 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory Features Table 51 Partition and Block Erase Region Information 88 Table 52 Partition Region 1 Information Top and Bottom Offset/Address 88 Table 53 Partition and Erase Block Map Information 90 Table 54 AADM Asynchronous and Latching Timings 109 Table 55 AADM Asynchronous Write Timings 111 Table 56 AADM Synchronous Timings 112 Table 57 Valid Line Items 116 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory General Description Micron's 65nm device is the latest generation of wireless memory featuring flexible, multiple-partition, dual-operation architecture. The device provides highperformance, asynchronous read mode and synchronous-burst read mode using 1.8V low-voltage, multilevel cell MLC technology. The multiple-partition architecture enables background programming or erasing to occur in one partition while code execution or data reads take place in another partition. This dual-operation architecture also allows two processors to interleave code operations while PROGRAM and ERASE operations take place in the background. The multiple partitions allow flexibility for system designers to choose the size of the code and data segments. The device is manufactured using 65nm process technologies and is available in industry-standard chip scale packaging. Functional Overview This device provides high read and write performance at low voltage on a 16-bit data bus. The multi-partition architecture provides read-while-write and read-while-erase capability, with individually erasable memory blocks sized for optimum code and data storage. This device is offered in densities from 128Mb to 1Gb. The device supports synchronous burst reads up to 133 MHz using enhanced CLK latching for all densities on 45nm. Upon initial power-up or return from reset, the device defaults to asynchronous read mode. Configuring the read configuration register enables synchronous burst mode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. In continuous-burst mode, a data read can traverse partition boundaries. A WAIT signal simplifies synchronizing the CPU to the memory. Designed for low-voltage applications, the device supports READ operations with VCC at 1.8V, and ERASE and PROGRAM operations with VPP at 1.8V or 9.0V. VCC and VPP can be tied together for a simple, ultra low-power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when VPP is less than VPPLK. A status register provides status and error conditions of ERASE and PROGRAM operations. One-time programmable OTP area enables unique identification that can be used to increase security. Additionally, the individual block lock feature provides zero-latency block locking and unlocking to protect against unwanted program or erase of the array. The device offers power-savings features, including automatic power savings mode, standby mode, and deep power-down mode. For power savings, the device automatically enters APS following a READ cycle. Standby is initiated when the system deselects the device by de-asserting CE#. Deep power-down provides the lowest power consumption and is enabled by programming in the extended configuration register. DPD is initiated by asserting the DPD pin. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. 128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory Configuration and Memory Map Configuration and Memory Map The device features a symmetrical block architecture. The main array of the 128Mb device is divided into eight 16Mb partitions. Each partition is divided into eight 256KB blocks 8 x 8 = 64 blocks . The main array of the 256Mb device is divided into eight 32Mb partitions. Each partition is divided into sixteen 256KB blocks 8 x 16 = 128 blocks . The main array of the 512Mb device is divided into eight 64Mb partitions. Each partition is divided into thirty-two 256KB blocks 8 x 32 = 256 blocks . The main array of the 1Gb device is divided into eight 128Mb partitions. Each partition is divided into sixty-four 256KB blocks 8 x 64 = 512 blocks . Each block is divided into as many as 256 1KB programming regions. Each region is divided into as many as thirty-two 32-byte segments Table 1 Main Array Memory Map 128Mb, 256Mb Partition 7 6 5 4 3 Size Mb 128Mb Block # 63 56 55 48 47 40 39 32 31 24 Address Range Ordering Information 128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory Ordering Information Figure 58 Part Number Chart for G18 Components Package Designator PC = Easy BGA, RoHS PC 28F 512 G 18 F Shipping Media E = Tray F = Tape and Reel Product Line Designator 28F = Micron Flash Memory Device Density Configuration 512 = 512Mb, x16 256 = 256Mb, x16 128 = 128Mb, x16 00A = 1Gb, x16 Interface F = Non-Mux A = AD-Mux Voltage 18 = core and I/O NOR Flash Product Family G = StrataFlash Embedded Memory Table 57 Valid Line Items Part Number PC28F128G18FE PC28F128G18FF PC28F256G18FE PC28F256G18FF PC28F256G18AE PC28F256G18AF PC28F512G18FE PC28F512G18FF PC28F00AG18FE PC28F00AG18FF Density 128Mb 256Mb 512Mb Package Easy BGA Easy BGA Easy BGA Easy BGA Easy BGA Easy BGA Easy BGA Easy BGA Easy BGA Easy BGA Interface Non-Mux Non-Mux Non-Mux Non-Mux AD-Mux AD-Mux Non-Mux Non-Mux Non-Mux Non-Mux Shipping Media Tray Tape and Reel Tray Tape and Reel Tray Tape and Reel Tray Tape and Reel Tray Tape and Reel Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved. • CFI ID string table, hex offset 13h Changed address 13 hex code to 00 changed address 14 hex code to • Table DC Voltage Characteristics and Operating Conditions Changed V IL Max to changed VIH Min to VCCQ - • Added AAD-mux description. • Made miscellaneous text edits and formatting improvements. • Initial release. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel 208-368-3900 Customer Comment Line 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.

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128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory Features

Micron StrataFlash Embedded Memory

P/N PC28F128G18xx P/N PC28F256G18xx P/N PC28F512G18xx P/N PC28F00AG18xx
• High-Performance Read, Program and Erase 96 ns initial read access 108 MHz with zero wait-state synchronous burst reads 7 ns clock-to-data output 133 MHz with zero wait-state synchronous burst reads ns clock-to-data output 8-, 16-, and continuous-word synchronous-burst Reads Programmable WAIT configuration Customer-configurable output driver impedance Buffered Programming us/Word typ , 512Mbit 65 nm Block Erase s per block typ 20 us typ program/erase suspend
• Architecture 16-bit wide data bus Multi-Level Cell Technology Symmetrically-Blocked Array Architecture 256-Kbyte Erase Blocks 1-Gbit device Eight 128-Mbit partitions 512-Mbit device Eight 64-Mbit partitions 256-Mbit device Eight 32-Mbit partitions 128-Mbit device Eight 16-Mbit partitions Read-While-Program and Read-While-Erase Status Register for partition/device status Blank Check feature
• Quality and Reliability Expanded temperature °C to +85 °C Minimum 100,000 erase cycles per block 65nm Process Technology
• Power Core voltage V - V I/O voltage V - V Standby current 60 uA typ for 512-Mbit, 65 nm Deep Power-Down mode 2 uA typ Automatic Power Savings mode 16-word synchronous-burst read current 23 mA typ 108 MHz 24 mA typ 133 MHz
• Software Flash data integrator FDI optimized Basic command set BCS and extended command set ECS compatible Common Flash interface CFI capable
• Security One-time programmable OTP space 64 unique factory device identifier bits 2112 user-programmable OTP bits Absolute write protection VPP = GND Power-transition erase/program lockout Individual zero latency block locking Individual block lock-down
• Density and packaging 128Mb, 256Mb, 512Mbit, and 1-Gbit Address-data multiplexed and non-multiplexed interfaces 64-Ball Easy BGA

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory Features

Contents

General Description 8 Functional Overview 8 Configuration and Memory Map 9 Device ID 12 Package Dimensions 13 Signal Assignments 14 Signal Descriptions 15 Bus Interface 16

Reset 16 Standby 16 Output Disable 16 Asynchronous Read 17 Synchronous Read 17 Burst Wrapping 17 End-of-Wordline Delay 18 Write 19 Command Definitions 20 Status Register 23 Clear Status Register 24 Read Configuration Register 25 Programming the Read Configuration Register 26 Extended Configuration Register 27 Output Driver Control 27 Programming the Extended Configuration Register 28 Read Operations 29 Read Array 29 Read ID 29 Read CFI 30 Read Status Register 30 WAIT Operation 31 Programming Modes 32 Control Mode 32 Object Mode 33 Program Operations 37 Single-Word Programming 37 Buffered Programming 38 Buffered Enhanced Factory Programming 38 Erase Operations 41 BLOCK ERASE 41 SUSPEND and RESUME Operations 42 SUSPEND Operation 42 RESUME Operation 43 BLANK CHECK Operation 44 Block Lock 45 One-Time Programmable Operations 47 Programming OTP Area 49 Reading OTP Area 49 Global Main-Array Protection 50 Dual Operation 51 Power and Reset Specifications 52

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.
128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory Features
Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.
128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory Features

List of Figures

Figure 1 64-Ball Easy BGA 8mm x 10mm x 1.2mm 13 Figure 2 64-Ball Easy BGA Top View, Balls Down 14 Figure 3 Main Array Word Lines 18 Figure 4 Wrap/No-Wrap Example 18 Figure 5 End-of-Wordline Delay 18 Figure 6 Two-Cycle Command Sequence 20 Figure 7 Single-Cycle Command Sequence 20 Figure 8 READ Cycle Between WRITE Cycles 20 Figure 9 Illegal Command Sequence 21 Figure 10 Configurable Programming Regions Control Mode and Object Mode 33 Figure 11 Configurable Programming Regions Control Mode and Object Mode Segments 35 Figure 12 BLOCK LOCK Operations 46 Figure 13 OTP Area Map 48 Figure 14 VPP Supply Connection Example 50 Figure 15 RESET Operation Waveforms 53 Figure 16 AC Input/Output Reference Waveform 60 Figure 17 Transient Equivalent Testing Load Circuit 60 Figure 18 Clock Input AC Waveform 61 Figure 19 Asynchronous Page-Mode Read Non-MUX 64 Figure 20 Synchronous 8- or 16-Word Burst Read Non-MUX 65 Figure 21 Synchronous Continuous Misaligned Burst Read Non-MUX 66 Figure 22 Synchronous Burst with Burst Interrupt Read Non-MUX 67 Figure 23 Asynchronous Single-Word Read 68 Figure 24 Synchronous 8- or 16-Word Burst Read A/D MUX 69 Figure 25 Synchronous Continuous Misaligned Burst Read A/D MUX 70 Figure 26 Synchronous Burst with Burst-Interrupt AD-Mux 70 Figure 27 Write Timing 73 Figure 28 Write to Write Non-Mux 74 Figure 29 Async Read to Write Non-Mux 74 Figure 30 Write to Async Read Non-Mux 75 Figure 31 Sync Read to Write Non-Mux 75 Figure 32 Write to Sync Read Non-Mux 76 Figure 33 Write to Write AD-Mux 76 Figure 34 Async Read to Write AD-Mux 77 Figure 35 Write to Async Read AD-Mux 77 Figure 36 Sync Read to Write AD-Mux 78 Figure 37 Write to Sync Read AD-Mux 78 Figure 38 Word Program Procedure 91 Figure 39 Word Program Full Status Check Procedure 92 Figure 40 Program Suspend/Resume Procedure 93 Figure 41 Buffer Programming Procedure 95 Figure 42 Buffered Enhanced Factory Programming BEFP Procedure 97 Figure 43 Block Erase Procedure 99 Figure 44 Block Erase Full Status Check Procedure 100 Figure 45 Erase Suspend/Resume Procedure 101 Figure 46 Block Lock Operations Procedure 103 Figure 47 Protection Register Programming Procedure 104 Figure 48 Protection Register Programming Full Status Check Procedure 105 Figure 49 Blank Check Procedure 106 Figure 50 Blank Check Full Status Check Procedure 107

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.
128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory Features

Figure 51 AADM Asynchronous READ Cycle Latching A[MAX:0] 110 Figure 52 AADM Asynchronous READ Cycle Latching A[15:0] only 110 Figure 53 AADM Asynchronous WRITE Cycle Latching A[MAX:0] 111 Figure 54 AADM Asynchronous WRITE Cycle Latching A[15:0] only 112 Figure 55 AADM Synchronous Burst READ Cycle ADV# De-asserted Between Address Cycles 113 Figure 56 AADM Synchronous Burst READ Cycle ADV# Not De-asserted Between Address Cycles 114 Figure 57 AADM Synchronous Burst READ Cycle Latching A[15:0] only 114 Figure 58 Part Number Chart for G18 Components 116

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.
128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory Features

List of Tables

Table 1 Main Array Memory Map 128Mb, 256Mb 9 Table 2 Main Array Memory Map 512Mb, 1Gb 10 Table 3 Device ID Codes 12 Table 4 Signal Descriptions 15 Table 5 Bus Control Signals 16 Table 6 Command Set 21 Table 7 Status Register Bit Definitions Default Value = 0080h 23 Table 8 CLEAR STATUS REGISTER Command Bus Cycles 24 Table 9 Read Configuration Register Bit Definitions Default Value = BFCFh 25 Table 10 Supported Clock Frequencies 25 Table 11 PROGRAM READ CONFIGURATION REGISTER Bus Cycles 26 Table 12 Extended Configuration Register Bit Definitions Default Value = 0004h 27 Table 13 Output Driver Control Characteristics 27 Table 14 Program Extended Configuration Register Command Bus Cycles 28 Table 15 READ MODE Command Bus Cycles 29 Table 16 Device Information 30 Table 17 WAIT Behavior Summary Non-MUX 31 Table 18 WAIT Behavior Summary AD MUX 31 Table 19 Programming Region Next State 36 Table 20 PROGRAM Command Bus Cycles 37 Table 21 BEFP Requirements and Considerations 39 Table 22 ERASE Command Bus Cycle 41 Table 23 Valid Commands During Suspend 42 Table 24 SUSPEND and RESUME Command Bus Cycles 43 Table 25 BLANK CHECK Command Bus Cycles 44 Table 26 BLOCK LOCK Command Bus Cycles 45 Table 27 Block Lock Configuration 46 Table 28 Program OTP Area Command Bus Cycles 47 Table 29 Dual Operation Restrictions 51 Table 30 Power Sequencing 52 Table 31 Reset Specifications 53 Table 32 Absolute Maximum Ratings 55 Table 33 Operating Conditions 55 Table 34 DC Current Characteristics and Operating Conditions 56 Table 35 DC Voltage Characteristics and Operating Conditions 59 Table 36 AC Input Requirements 60 Table 37 Test Configuration Load Capacitor Values for Worst Case Speed Conditions 60 Table 38 Capacitance 61 Table 39 AC Read Specifications CLK-Latching, 133 MHz , VCCQ = 1.7V to 2.0V 62 Table 40 AC Write Specifications 72 Table 41 Program/Erase Characteristics 79 Table 42 Example of CFI Output x16 Device as a Function of Device and Mode 80 Table 43 CFI Database Addresses and Sections 80 Table 44 CFI ID String 81 Table 45 System Interface Information 81 Table 46 Device Geometry 82 Table 47 Block Region Map Information 83 Table 48 Primary Micron-Specific Extended Query 85 Table 49 One Time Programmable OTP Space Information 86 Table 50 Burst Read Informaton 87

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.
128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory Features

Table 51 Partition and Block Erase Region Information 88 Table 52 Partition Region 1 Information Top and Bottom Offset/Address 88 Table 53 Partition and Erase Block Map Information 90 Table 54 AADM Asynchronous and Latching Timings 109 Table 55 AADM Asynchronous Write Timings 111 Table 56 AADM Synchronous Timings 112 Table 57 Valid Line Items 116

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.
128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory General Description

Micron's 65nm device is the latest generation of wireless memory featuring flexible, multiple-partition, dual-operation architecture. The device provides highperformance, asynchronous read mode and synchronous-burst read mode using 1.8V low-voltage, multilevel cell MLC technology.

The multiple-partition architecture enables background programming or erasing to occur in one partition while code execution or data reads take place in another partition. This dual-operation architecture also allows two processors to interleave code operations while PROGRAM and ERASE operations take place in the background. The multiple partitions allow flexibility for system designers to choose the size of the code and data segments.

The device is manufactured using 65nm process technologies and is available in industry-standard chip scale packaging.

Functional Overview

This device provides high read and write performance at low voltage on a 16-bit data bus. The multi-partition architecture provides read-while-write and read-while-erase capability, with individually erasable memory blocks sized for optimum code and data storage.

This device is offered in densities from 128Mb to 1Gb. The device supports synchronous burst reads up to 133 MHz using enhanced CLK latching for all densities on 45nm.

Upon initial power-up or return from reset, the device defaults to asynchronous read mode. Configuring the read configuration register enables synchronous burst mode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. In continuous-burst mode, a data read can traverse partition boundaries. A WAIT signal simplifies synchronizing the CPU to the memory.

Designed for low-voltage applications, the device supports READ operations with VCC at 1.8V, and ERASE and PROGRAM operations with VPP at 1.8V or 9.0V. VCC and VPP can be tied together for a simple, ultra low-power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when VPP is less than VPPLK.

A status register provides status and error conditions of ERASE and PROGRAM operations.

One-time programmable OTP area enables unique identification that can be used to increase security. Additionally, the individual block lock feature provides zero-latency block locking and unlocking to protect against unwanted program or erase of the array.

The device offers power-savings features, including automatic power savings mode, standby mode, and deep power-down mode. For power savings, the device automatically enters APS following a READ cycle. Standby is initiated when the system deselects the device by de-asserting CE#. Deep power-down provides the lowest power consumption and is enabled by programming in the extended configuration register. DPD is initiated by asserting the DPD pin.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.
128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory Configuration and Memory Map

Configuration and Memory Map

The device features a symmetrical block architecture. The main array of the 128Mb device is divided into eight 16Mb partitions. Each partition is divided into eight 256KB blocks 8 x 8 = 64 blocks .

The main array of the 256Mb device is divided into eight 32Mb partitions. Each partition is divided into sixteen 256KB blocks 8 x 16 = 128 blocks .

The main array of the 512Mb device is divided into eight 64Mb partitions. Each partition is divided into thirty-two 256KB blocks 8 x 32 = 256 blocks .

The main array of the 1Gb device is divided into eight 128Mb partitions. Each partition is divided into sixty-four 256KB blocks 8 x 64 = 512 blocks .

Each block is divided into as many as 256 1KB programming regions. Each region is divided into as many as thirty-two 32-byte segments

Table 1 Main Array Memory Map 128Mb, 256Mb

Partition 7 6 5 4 3

Size Mb
128Mb

Block # 63 56 55 48 47 40 39 32 31 24

Address Range
Ordering Information
128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory Ordering Information

Figure 58 Part Number Chart for G18 Components

Package Designator

PC = Easy BGA, RoHS

PC 28F 512 G 18 F

Shipping Media

E = Tray F = Tape and Reel

Product Line Designator
28F = Micron Flash Memory

Device Density Configuration
512 = 512Mb, x16 256 = 256Mb, x16 128 = 128Mb, x16 00A = 1Gb, x16

Interface

F = Non-Mux A = AD-Mux

Voltage
18 = core and I/O

NOR Flash Product Family

G = StrataFlash Embedded Memory

Table 57 Valid Line Items

Part Number PC28F128G18FE PC28F128G18FF PC28F256G18FE PC28F256G18FF PC28F256G18AE PC28F256G18AF PC28F512G18FE PC28F512G18FF PC28F00AG18FE PC28F00AG18FF

Density 128Mb 256Mb 512Mb

Package Easy BGA Easy BGA Easy BGA Easy BGA Easy BGA Easy BGA Easy BGA Easy BGA Easy BGA Easy BGA

Interface Non-Mux Non-Mux Non-Mux Non-Mux AD-Mux AD-Mux Non-Mux Non-Mux Non-Mux Non-Mux

Shipping Media Tray

Tape and Reel Tray

Tape and Reel Tray

Tape and Reel Tray

Tape and Reel Tray

Tape and Reel

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.
• CFI ID string table, hex offset 13h Changed address 13 hex code to 00 changed address 14 hex code to
• Table DC Voltage Characteristics and Operating Conditions Changed V IL Max to changed VIH Min to VCCQ -
• Added AAD-mux description.
• Made miscellaneous text edits and formatting improvements.
• Initial release.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel 208-368-3900 Customer Comment Line 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2011 Micron Technology, Inc. All rights reserved.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived PC28F256G18FE Datasheet file may be downloaded here without warranties.

Datasheet ID: PC28F256G18FE 648545