NDC652P

NDC652P Datasheet

NDC652P P-Channel Logic Level Enhancement Mode Field Effect Transistor

Part	Datasheet
NDC652P	NDC652P (pdf)

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March 1996 NDC652P P-Channel Logic Level Enhancement Mode Field Effect Transistor These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package. -2.4A, -30V. RDS ON = VGS = -4.5V RDS ON = VGS = -10V. Proprietary SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS ON . Exceptional on-resistance and maximum DC current capability. Absolute Maximum Ratings Symbol Parameter TA = 25°C unless otherwise noted VDSS Drain-Source Voltage VGSS Gate-Source Voltage - Continuous Drain Current - Continuous - Pulsed Maximum Power Dissipation Note 1a Note 1b Note 1c TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Note 1a Thermal Resistance, Junction-to-Case Note 1 1997 Fairchild Semiconductor Corporation NDC652P -30 -20 -10 1 -55 to 150 78 30 Units V A W °C °C/W °C/W ELECTRICAL CHARACTERISTICS TA = 25°C unless otherwise noted Symbol Parameter Conditions OFF CHARACTERISTICS BVDSS IDSS Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = -250 µA VDS = -24 V, VGS = 0 V IGSSF Gate - Body Leakage, Forward IGSSR ON CHARACTERISTICS Note 2 VGS th Gate Threshold Voltage

PDF Datasheet Preview

March 1996

NDC652P P-Channel Logic Level Enhancement Mode Field Effect Transistor

These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package.
-2.4A, -30V. RDS ON = VGS = -4.5V RDS ON = VGS = -10V.

Proprietary SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities.

High density cell design for extremely low RDS ON .

Exceptional on-resistance and maximum DC current capability.

Absolute Maximum Ratings Symbol Parameter

TA = 25°C unless otherwise noted

VDSS

Drain-Source Voltage

VGSS

Gate-Source Voltage - Continuous

Drain Current - Continuous
- Pulsed

Maximum Power Dissipation

Note 1a Note 1b

Note 1c

TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Ambient Note 1a

Thermal Resistance, Junction-to-Case

Note 1
1997 Fairchild Semiconductor Corporation

NDC652P -30 -20 -10 1
-55 to 150
78 30

Units V A W
°C °C/W °C/W

ELECTRICAL CHARACTERISTICS TA = 25°C unless otherwise noted

Symbol Parameter

Conditions

OFF CHARACTERISTICS

BVDSS IDSS

Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current

VGS = 0 V, ID = -250 µA VDS = -24 V, VGS = 0 V

IGSSF

Gate - Body Leakage, Forward

IGSSR

ON CHARACTERISTICS Note 2

VGS th

Gate Threshold Voltage

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Datasheet ID: NDC652P 634592