N25Q512A11G1240F TR

N25Q512A11G1240F TR Datasheet

1.8V, Multiple I/O, 4KB Sector Erase N25Q512A

Part	Datasheet
N25Q512A11G1240F TR	N25Q512A11G1240F TR (pdf)

PDF Datasheet Preview
512Mb, 1.8V, Multiple I/O Serial Flash Memory Features Micron Serial NOR Flash Memory 1.8V, Multiple I/O, 4KB Sector Erase N25Q512A • Stacked device two 256Mb die • SPI-compatible serial bus interface • Double transfer rate DTR mode • single supply voltage • 108 MHz MAX clock frequency supported for all protocols in single transfer rate STR mode • 54 MHz MAX clock frequency supported for all protocols in DTR mode • Dual/quad I/O instruction provides increased throughput up to 54 MB/s • Supported protocols Extended SPI, dual I/O, and quad I/O DTR mode supported on all • Execute-in-place XIP mode for all three protocols Configurable via volatile or nonvolatile registers Enables memory to work in XIP mode directly af- ter power-on • PROGRAM/ERASE SUSPEND operations • Available protocols Available READ operations Quad or dual output fast read Quad or dual I/O fast read • Flexible to fit application Configurable number of dummy cycles Output buffer configurable • Software reset • RESET# pin for selected part numbers • 3-byte and 4-byte addressability mode supported • 64-byte, user-lockable, one-time programmable OTP dedicated area • Erase capability Subsector erase 4KB uniform granularity blocks Sector erase 64KB uniform granularity blocks Single die erase • Write protection Software write protection applicable to every 64KB sector via volatile lock bit Hardware write protection protected area size defined by five nonvolatile bits BP0, BP1, BP2, BP3, and TB Additional smart protections, available upon request • Electronic signature JEDEC-standard 2-byte signature BB20h Unique ID code UID 17 read-only bytes, including Two additional extended device ID bytes to identify device factory options and customized factory data 14 bytes • Minimum 100,000 ERASE cycles per sector • More than 20 years data retention • Packages JEDEC-standard, all RoHS-compliant V-PDFN-8/8mm x 6mm also known as SON, DFPN, MLP, MLF SOP2-16/300mils also known as SO16W, SO16Wide, SOIC-16 T-PBGA-24b05/6mm x 8mm also known as TBGA24 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 512Mb, 1.8V, Multiple I/O Serial Flash Memory Features Contents Device Description 6 Features 6 3-Byte Address and 4-Byte Address Modes 6 Operating Protocols 6 XIP Mode 7 Device Configurability 7 Signal Assignments 8 Signal Descriptions 10 Memory Organization 12 Memory Configuration and Block Diagram 12 Memory Map 512Mb Density 13 Device Protection 14 Serial Peripheral Interface Modes 16 SPI Protocols 18 Nonvolatile and Volatile Registers 19 Status Register 20 Nonvolatile and Volatile Configuration Registers 21 Extended Address Register 24 Enhanced Volatile Configuration Register 25 Flag Status Register 26 Command Definitions 28 READ REGISTER and WRITE REGISTER Operations 32 READ STATUS REGISTER or FLAG STATUS REGISTER Command 32 READ NONVOLATILE CONFIGURATION REGISTER Command 33 READ VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command 33 READ EXTENDED ADDRESS REGISTER Command 34 WRITE STATUS REGISTER Command 34 WRITE NONVOLATILE CONFIGURATION REGISTER Command 35 WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command 35 WRITE EXTENDED ADDRESS REGISTER Command 36 READ LOCK REGISTER Command 36 WRITE LOCK REGISTER Command 38 CLEAR FLAG STATUS REGISTER Command 39 READ IDENTIFICATION Operations 40 READ ID and MULTIPLE I/O READ ID Commands 40 READ SERIAL FLASH DISCOVERY PARAMETER Command 41 READ MEMORY Operations 45 3-Byte Address 45 4-Byte Address 46 READ MEMORY Operations Timing Single Transfer Rate 48 READ MEMORY Operations Timing Double Transfer Rate 52 PROGRAM Operations 56 WRITE Operations 61 WRITE ENABLE Command 61 WRITE DISABLE Command 61 ERASE Operations 63 SUBSECTOR ERASE Command 63 SECTOR ERASE Command 63 DIE ERASE Command 64 BULK ERASE Command 65 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 512Mb, 1.8V, Multiple I/O Serial Flash Memory Features Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 512Mb, 1.8V, Multiple I/O Serial Flash Memory Features List of Figures Figure 1 Logic Diagram 7 Figure 2 8-Lead, VDFPN8 MLP8 Top View 8 Figure 3 24-Ball TBGA Balls Down 8 Figure 4 16-Pin SO16 Top View 9 Figure 5 Block Diagram 12 Figure 6 Bus Master and Memory Devices on the SPI Bus 17 Figure 7 SPI Modes 17 Figure 8 Internal Configuration Register 19 Figure 9 Upper and Lower Memory Array Segments 24 Figure 10 READ REGISTER Command 33 Figure 11 WRITE REGISTER Command 35 Figure 12 READ LOCK REGISTER Command 38 Figure 13 WRITE LOCK REGISTER Command 39 Figure 14 READ ID and MULTIPLE I/O Read ID Commands 41 Figure 15 READ Command 48 Figure 16 FAST READ Command 48 Figure 17 DUAL OUTPUT FAST READ Command 49 Figure 18 DUAL INPUT/OUTPUT FAST READ Command 49 Figure 19 QUAD OUTPUT FAST READ Command 50 Figure 20 QUAD INPUT/OUTPUT FAST READ Command 51 Figure 21 FAST READ Command DTR 52 Figure 22 DUAL OUTPUT FAST READ Command DTR 53 Figure 23 DUAL INPUT/OUTPUT FAST READ Command DTR 53 Figure 24 QUAD OUTPUT FAST READ Command DTR 54 Figure 25 QUAD INPUT/OUTPUT FAST READ Command DTR 54 Figure 26 PAGE PROGRAM Command 57 Figure 27 DUAL INPUT FAST PROGRAM Command 58 Figure 28 EXTENDED DUAL INPUT FAST PROGRAM Command 58 Figure 29 QUAD INPUT FAST PROGRAM Command 59 Figure 30 EXTENDED QUAD INPUT FAST PROGRAM Command 60 Figure 31 WRITE ENABLE and WRITE DISABLE Command Sequence 62 Figure 32 SUBSECTOR and SECTOR ERASE Command 64 Figure 33 DIE ERASE Command 65 Figure 34 BULK ERASE Command 66 Figure 35 RESET ENABLE and RESET MEMORY Command 69 Figure 36 READ OTP Command 70 Figure 37 PROGRAM OTP Command 71 Figure 38 XIP Mode Directly After Power-On 74 Figure 39 Power-Up Timing 76 Figure 40 Reset AC Timing During PROGRAM or ERASE Cycle 79 Figure 41 Reset Enable 79 Figure 42 Serial Input Timing 79 Figure 43 Write Protect Setup and Hold During WRITE STATUS REGISTER Operation SRWD = 1 80 Figure 44 Hold Timing 81 Figure 45 Output Timing 81 Figure 46 VPPH Timing 82 Figure 47 AC Timing Input/Output Reference Levels 84 Figure 48 V-PDFN-8/8mm x 6mm 88 Figure 49 SOP2-16/300 mils 89 Figure 50 T-PBGA-24b05/6mm x 8mm 90 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 512Mb, 1.8V, Multiple I/O Serial Flash Memory Features List of Tables Table 1 Signal Descriptions 10 Table 2 Sectors[1023:0] 13 Table 3 Data Protection Using Device Protocols 14 Table 4 Memory Sector Protection Truth Table 14 Table 5 Protected Area Sizes Upper Area 14 Table 6 Protected Area Sizes Lower Area 15 Table 7 SPI Modes 16 Table 8 Extended, Dual, and Quad SPI Protocols 18 Table 9 Status Register Bit Definitions 20 Table 10 Nonvolatile Configuration Register Bit Definitions 21 Table 11 Volatile Configuration Register Bit Definitions 22 Table 12 Sequence of Bytes During Wrap 23 Table 13 Supported Clock Frequencies STR 23 Table 14 Supported Clock Frequencies DTR 23 Table 15 Extended Address Register Bit Definitions 25 Table 16 Enhanced Volatile Configuration Register Bit Definitions 25 Table 17 Flag Status Register Bit Definitions 26 Table 18 Command Set 28 Table 19 Lock Register 36 Table 20 Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands 40 Table 21 Read ID Data Out 40 Table 22 Extended Device ID, First Byte 40 Table 23 Serial Flash Discovery Parameter Data Structure 42 Table 24 Parameter ID 42 Table 25 Command/Address/Data Lines for READ MEMORY Commands 45 Table 26 Command/Address/Data Lines for READ MEMORY Commands 4-Byte Address 46 Table 27 Data/Address Lines for PROGRAM Commands 56 Table 28 Suspend Parameters 67 Table 29 Operations Allowed/Disallowed During Device States 67 Table 30 Reset Command Set 69 Table 31 OTP Control Byte 64 71 Table 32 XIP Confirmation Bit 74 Table 33 Effects of Running XIP in Different Protocols 74 Table 34 Power-Up Timing and VWI Threshold 77 Table 35 AC RESET Conditions 78 Table 36 Absolute Ratings 83 Table 37 Operating Conditions 83 Table 38 Input/Output Capacitance 83 Table 39 AC Timing Input/Output Conditions 84 Table 40 DC Current Characteristics and Operating Conditions 85 Table 41 DC Voltage Characteristics and Operating Conditions 85 Table 42 AC Characteristics and Operating Conditions 86 Table 43 Part Number Information 91 Table 44 Package Details 92 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 512Mb, 1.8V, Multiple I/O Serial Flash Memory Device Description Device Description The N25Q is a high-performance multiple input/output serial Flash memory device manufactured on 65nm NOR technology. It features execute-in-place XIP functionality, advanced write protection mechanisms, and a high-speed SPI-compatible bus interface. Innovative, high-performance, dual and quad input/output instructions enable double or quadruple the transfer bandwidth for READ and PROGRAM operations. The 512Mb N25Q stacked device contains two 256Mb die. From a user standpoint this stacked device behaves as a monolithic device, except with regard to READ MEMORY and ERASE operations and status polling. The device contains a single chip select S# a dual-chip version is also available. Contact the factory for more information. The memory is organized as 1024 64KB main sectors that are further divided into 16 subsectors each 16,384 subsectors in total . The memory can be erased one 4KB subsector at a time, 64KB sectors at a time, or single die 256Mb at a time. The memory can be write protected by software through volatile and nonvolatile protection features, depending on the application needs. The protection granularity is of 64KB sector granularity for volatile protections The device has 64 one-time programmable OTP bytes that can be read and programmed with the READ OTP and PROGRAM OTP commands. These 64 bytes can also be permanently locked with a PROGRAM OTP command. The device can also pause and resume PROGRAM and ERASE cycles by using dedicated PROGRAM/ERASE SUSPEND and RESUME instructions. 3-Byte Address and 4-Byte Address Modes The device features 3-byte or 4-byte address modes to access memory beyond 128Mb. When 4-byte address mode is enabled, all commands requiring an address must be entered and exited with a 4-byte address mode command ENTER 4-BYTE ADDRESS MODE command and EXIT 4-BYTE ADDRESS MODE command. The 4-byte address mode can also be enabled through the nonvolatile configuration register. See Registers for more information. Operating Protocols The memory can be operated with three different protocols: • Extended SPI standard SPI protocol upgraded with dual and quad operations • Dual I/O SPI • Quad I/O SPI The standard SPI protocol is extended and enhanced by dual and quad operations. In addition, the dual SPI and quad SPI protocols improve the data access time and throughput of a single I/O device by transmitting commands, addresses, and data across two or four data lines. Each protocol contains unique commands to perform READ operations in DTR mode. This enables high data throughput while running at lower clock frequencies. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 512Mb, 1.8V, Multiple I/O Serial Flash Memory Device Description XIP Mode XIP mode requires only an address no instruction to output data, improving random access time and eliminating the need to shadow code onto RAM for fast execution. Nonvolatile configuration register bits can set XIP mode as the default mode for applications that must enter XIP mode immediately after powering up. All protocols support XIP operation. For flexibility, multiple XIP entry and exit methods are available. For applications that must enter XIP mode immediately after power-up, nonvolatile configuration register bit settings can enable XIP as the default mode. Device Configurability The N25Q family offers additional features that are configured through the nonvolatile configuration register for default and/or nonvolatile settings. Volatile settings can be configured through the volatile and volatile-enhanced configuration registers. These configurable features include the following: • Number of dummy cycles for the fast READ commands • Output buffer impedance • SPI protocol types extended SPI, dual SPI, or quad SPI • Required XIP mode • Enabling/disabling HOLD RESET function • Enabling/disabling wrap mode Figure 1 Logic Diagram DQ0 C S# VPP/W#/DQ2 HOLD#/DQ3 DQ1 RESET2 Note Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for more details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. Signal Assignments 512Mb, 1.8V, Multiple I/O Serial Flash Memory Signal Assignments Figure 2 8-Lead, VDFPN8 MLP8 Top View DQ1 2 W#/VPP/DQ2 3 VSS 4 8 VCC 7 HOLD#/DQ3 5 DQ0 On the underside of the MLP8 package, there is an exposed central pad that is pulled internally to VSS and must not be connected to any other voltage or signal line on the PCB. Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for complete package names and details. Figure 3 24-Ball TBGA Balls Down NC RESET/NC NC W#/VPP/DQ2 NC DQ1 DQ0 HOLD#/DQ3 NC Note Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for complete package names and details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 512Mb, 1.8V, Multiple I/O Serial Flash Memory Signal Assignments Figure 4 16-Pin SO16 Top View HOLD#/DQ3 1 VCC 2 RESET/DNU2 3 DNU 4 DNU 5 DNU 6 S# 7 DQ1 8 16 C 15 DQ0 14 DNU 13 DNU 12 DNU 11 DNU 10 VSS 9 W#/VPP/DQ2 Note Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for complete package names and details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 512Mb, 1.8V, Multiple I/O Serial Flash Memory Signal Descriptions Signal Descriptions The signal description table below is a comprehensive list of signals for the N25 family devices. All signals listed may not be supported on this device. See Signal Assignments for information specific to this device. Table 1 Signal Descriptions Symbol C S# DQ2 DQ3 RESET# Type Input Input and I/O Output and I/O Input and I/O Input and I/O Control Input Clock Provides the timing of the serial interface. Commands, addresses, or data present at serial data inputs are latched on the rising edge of the clock. Data is shifted out on the falling edge of the clock. Chip select When S# is HIGH, the device is deselected and DQ1 is at High-Z. When in extended SPI mode, with the device deselected, DQ1 is tri-stated. Unless an internal PROGRAM, ERASE, or WRITE STATUS REGISTER cycle is in progress, the device enters standby power mode not deep power-down mode . Driving S# LOW enables the device, placing it in the active power mode. After power-up, a falling edge on S# is required prior to the start of any command. Serial data Transfers data serially into the device. It receives command codes, addresses, and the data to be programmed. Values are latched on the rising edge of the clock. DQ0 is used for input/output during the following operations DUAL OUTPUT FAST READ, QUAD OUTPUT FAST READ, DUAL INPUT/OUTPUT FAST READ, and QUAD INPUT/OUTPUT FAST READ. When used for output, data is shifted out on the falling edge of the clock. In DIO-SPI, DQ0 always acts as an input/output. In QIO-SPI, DQ0 always acts as an input/output, with the exception of the PROGRAM or ERASE cycle performed with VPP. The device temporarily enters the extended SPI protocol and then returns to QIO-SPI as soon as VPP goes LOW. Serial data:Transfers data serially out of the device. Data is shifted out on the falling edge of the clock. DQ1 is used for input/output during the following operations DUAL INPUT FAST PROGRAM, QUAD INPUT FAST PROGRAM, DUAL INPUT EXTENDED FAST PROGRAM, and QUAD INPUT EXTENDED FAST PROGRAM. When used for input, data is latched on the rising edge of the clock. In DIO-SPI, DQ1 always acts as an input/output. In QIO-SPI, DQ1 always acts as an input/output, with the exception of the PROGRAM or ERASE cycle performed with the enhanced program supply voltage VPP . In this case the device temporarily enters the extended SPI protocol and then returns to QIO-SPI as soon as VPP goes LOW. DQ2 When in QIO-SPI mode or in extended SPI mode using QUAD FAST READ commands, the signal functions as DQ2, providing input/output. All data input drivers are always enabled except when used as an output. Micron recommends customers drive the data signals normally to avoid unnecessary switching current and float the signals before the memory device drives data on them. DQ3 When in quad SPI mode or in extended SPI mode using quad FAST READ commands, the signal functions as DQ3, providing input/output. HOLD# is disabled and RESET# is disabled if the device is selected. RESET This is a hardware RESET# signal. When RESET# is driven HIGH, the memory is in the normal operating mode. When RESET# is driven LOW, the memory enters reset mode and output is High-Z. If RESET# is driven LOW while an internal WRITE, PROGRAM, or ERASE operation is in progress, data may be lost. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 512Mb, 1.8V, Multiple I/O Serial Flash Memory Signal Descriptions Table 1 Signal Descriptions Continued Symbol HOLD# VCC VSS DNU NC Type Control Input Control Input Power Power Ground HOLD Pauses any serial communications with the device without deselecting the device. DQ1 output is High-Z. DQ0 input and the clock are "Don't Care." To enable HOLD, the device must be selected with S# driven LOW. HOLD# is used for input/output during the following operations QUAD OUTPUT FAST READ, QUAD INPUT/OUTPUT FAST READ, QUAD INPUT FAST PROGRAM, and QUAD INPUT EXTENDED FAST PROGRAM. In QIO-SPI, HOLD# acts as an I/O DQ3 functionality , and the HOLD# functionality is disabled when the device is selected. When the device is deselected S# is HIGH in parts with RESET# functionality, it is possible to reset the device unless this functionality is not disabled by means of dedicated registers bits. The HOLD# functionality can be disabled using bit 4 of the NVCR or bit 4 of the VECR. On devices that include DTR mode capability, the HOLD# functionality is disabled as soon as a DTR operation is recognized. Write protect W# can be used as a protection control input or in QIO-SPI operations. When in extended SPI with single or dual commands, the WRITE PROTECT function is selectable by the voltage range applied to the signal. If voltage range is low 0V to VCC , the signal acts as a write protection control input. The memory size protected against PROGRAM or ERASE operations is locked as specified in the status register block protect bits W# is used as an input/output DQ2 functionality during QUAD INPUT FAST READ and QUAD INPUT/OUTPUT FAST READ operations and in QIO-SPI. Supply voltage If VPP is in the voltage range of VPPH, the signal acts as an additional power supply, as defined in the AC Measurement Conditions table. During QIFP, QIEFP, and QIO-SPI PROGRAM/ERASE operations, it is possible to use the additional VPP power supply to speed up internal operations. However, to enable this functionality, it is necessary to set bit 3 of the VECR to In this case, VPP is used as an I/O until the end of the operation. After the last input data is shifted in, the application should apply VPP voltage to VPP within 200ms to speed up the internal operations. If the VPP voltage is not applied within 200ms, the PROGRAM/ERASE operations start at standard speed. The default value of VECR bit 3 is 1, and the VPP functionality for quad I/O modify operations is disabled. Device core power supply Source voltage. Ground Reference for the VCC supply voltage. Do not use. No connect. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 512Mb, 1.8V, Multiple I/O Serial Flash Memory Organization Memory Organization Memory Configuration and Block Diagram The memory is a stacked device comprised of two 256Mb chips. Each chip is internally partitioned into two 128Mb segments. Each page of memory can be individually programmed. Bits are programmed from one through zero. The device is subsector, sector, or single 256Mb chip erasable, but not page-erasable. Bits are erased from zero through one. The memory is configured as 67,108,864 bytes 8 bits each 1024 sectors 64KB each 16,384 subsectors 4KB each and 262,144 pages 256 bytes each and 64 OTP bytes are located outside the main memory array. Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 512Mb, 1.8V, Multiple I/O Serial Flash Memory Package Dimensions Figure 49 SOP2-16/300 mils MIN/ MAX h x 45° MIN/ MAX 0° MIN/8° MAX MIN/ MAX TYP Z MIN/ MAX Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. Figure 50 T-PBGA-24b05/6mm x 8mm 512Mb, 1.8V, Multiple I/O Serial Flash Memory Package Dimensions Seating plane A 54321 Ball A1 ID A B C 8 D E Ball A1 ID Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 512Mb, 1.8V, Multiple I/O Serial Flash Memory Part Number Ordering Information Part Number Ordering Information Micron Serial NOR Flash devices are available in different configurations and densities. Verify valid part numbers by using Micron’s part catalog search at micron.com. To compare features and specifications by device type, visit micron.com/products. Contact the factory for devices not found. For more information on how to identify products and top-side marking by the process identification letter, refer to technical note TN-12-24, "Serial Flash Memory Device Marking for the M25P, M25PE, M25PX, and N25Q Product Families." Table 43 Part Number Information Part Number Category Device type Density Technology Feature set Operating voltage Block structure Package RoHS-compliant Temperature and test flow Security features Shipping material Category Details N25Q = Serial NOR Flash memory, Multiple Input/Output Single, Dual, Quad I/O , XIP 512 = 512Mb A = 65nm 1 = Byte addressability HOLD pin Micron XIP 2 = Byte addressability HOLD pin Basic XIP 3 = Byte addressability RESET# pin Micron XIP 4 = Byte addressability RESET# pin Basic XIP 7 = Byte addressability HOLD pin Micron XIP 8 = Byte addressability RESET# pin HOLD pin Micron XIP 1 = VCC = to 2.0V G = Uniform 64KB and 4KB , easy transparent stack F8 = V-PDFN-8/8mm x 6mm RP SF = SOP2-16/300mils 12 = T-PBGA-24b05/6mm x 8mm 4 = IT to 85°C Device tested with standard test flow A = Automotive temperature range, to 125°C Device tested with high reliability certified test flow H = IT to 85°C Device tested with high reliability certified test flow 0 = Default See the Security Ordering Information table below. E = Tray F = Tape and reel G = Tube Notes 1 2 3 Enter 4-byte address mode and exit 4-byte address mode supported. 4-byte addressing mode is the default at power-up. Enter and exit 4-byte addressing mode are not supported. See the table below for additional information. Additional secure options are available upon customer request. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 512Mb, 1.8V, Multiple I/O Serial Flash Memory Part Number Ordering Information Table 44 Package Details Micron SPI and JEDEC V-PDFN-8/8mm x 6mm RP SOP2-16/300mil T-PBGA-24b05/6x8 Names Shortened M25P and M45PE DFN-8/8mm MLP8, VDFPN8 SO16W TBGA 24 SO16W, SO16 wide 300 mil body width TBGA24 6mm x 8mm Alternate V-PSON1-8/8mm x 6mm, VSON SOIC-16/300 mil, SOP 16L 300 mil T-PBGA-24b05/6x8 Very thin, plastic smalloutline, 8 terminal pads no leads , 8mm x 6mm Small-outline integrated circuit, 16-pin, wide 300 mil Thin, plastic-ball grid array, 24-ball, 6mm x 8mm M25P M45PE N25Q Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. • In Command Set table, updated value for Quad I/O FAST READ DTR from 3Dh to 6Dh pin Micron XIP • Corrected RESET ENABLE and RESET MEMORY command timing diagram • Removed ICC1 grade 3 in the DC Current Characteristics and Operating Conditions table • Updated the READ ID Operation figure in READ ID Operations • Updated ERASE Operations • Added link to part number chart in Part Number Ordering Information • Updated part numbers in Features • Typo fix in Command Set table in Command Definitions Dual I/O FAST READ - DTR from DBh to BDh • Typo fix in Supported Clock Frequencies - DTR table in Nonvolatile and Volatile Registers • Updated tSSE specification in AC Reset Conditions table • Added V-PDFN 8/8mm x 6mm package • Updated AC Reset Specifications to include Write Protect Setup and Hold WRITE STATUS REGISTER Operation SRWD = 1 timing diagram Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. • Updated AC Reset Specifications to include power-down values • Correction to bit 1:0 A24 in Description corrected to A[25:24] of Extended Address Register Bit Definitions table in Nonvolatile and Volatile Registers • Initial release 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel 208-368-3900 Customer Comment Line 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.

PDF Datasheet Preview

512Mb, 1.8V, Multiple I/O Serial Flash Memory Features

Micron Serial NOR Flash Memory
1.8V, Multiple I/O, 4KB Sector Erase N25Q512A
• Stacked device two 256Mb die
• SPI-compatible serial bus interface
• Double transfer rate DTR mode
• single supply voltage
• 108 MHz MAX clock frequency supported for all
protocols in single transfer rate STR mode
• 54 MHz MAX clock frequency supported for all
protocols in DTR mode
• Dual/quad I/O instruction provides increased
throughput up to 54 MB/s
• Supported protocols

Extended SPI, dual I/O, and quad I/O DTR mode supported on all
• Execute-in-place XIP mode for all three protocols Configurable via volatile or nonvolatile registers Enables memory to work in XIP mode directly af-
ter power-on
• PROGRAM/ERASE SUSPEND operations
• Available protocols

Available READ operations Quad or dual output fast read Quad or dual I/O fast read
• Flexible to fit application Configurable number of dummy cycles Output buffer configurable
• Software reset
• RESET# pin for selected part numbers
• 3-byte and 4-byte addressability mode supported
• 64-byte, user-lockable, one-time programmable OTP dedicated area
• Erase capability Subsector erase 4KB uniform granularity blocks Sector erase 64KB uniform granularity blocks Single die erase
• Write protection Software write protection applicable to every 64KB sector via volatile lock bit Hardware write protection protected area size defined by five nonvolatile bits BP0, BP1, BP2, BP3, and TB Additional smart protections, available upon request
• Electronic signature JEDEC-standard 2-byte signature BB20h Unique ID code UID 17 read-only bytes, including Two additional extended device ID bytes to identify device factory options and customized factory data 14 bytes
• Minimum 100,000 ERASE cycles per sector
• More than 20 years data retention
• Packages JEDEC-standard, all RoHS-compliant

V-PDFN-8/8mm x 6mm also known as SON, DFPN, MLP, MLF

SOP2-16/300mils also known as SO16W, SO16Wide, SOIC-16

T-PBGA-24b05/6mm x 8mm also known as TBGA24

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
512Mb, 1.8V, Multiple I/O Serial Flash Memory Features

Contents

Device Description 6 Features 6 3-Byte Address and 4-Byte Address Modes 6 Operating Protocols 6 XIP Mode 7 Device Configurability 7

Signal Assignments 8 Signal Descriptions 10 Memory Organization 12

Memory Configuration and Block Diagram 12 Memory Map 512Mb Density 13 Device Protection 14 Serial Peripheral Interface Modes 16 SPI Protocols 18 Nonvolatile and Volatile Registers 19

Status Register 20 Nonvolatile and Volatile Configuration Registers 21 Extended Address Register 24 Enhanced Volatile Configuration Register 25 Flag Status Register 26 Command Definitions 28 READ REGISTER and WRITE REGISTER Operations 32 READ STATUS REGISTER or FLAG STATUS REGISTER Command 32 READ NONVOLATILE CONFIGURATION REGISTER Command 33 READ VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command 33 READ EXTENDED ADDRESS REGISTER Command 34 WRITE STATUS REGISTER Command 34 WRITE NONVOLATILE CONFIGURATION REGISTER Command 35 WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command 35 WRITE EXTENDED ADDRESS REGISTER Command 36 READ LOCK REGISTER Command 36 WRITE LOCK REGISTER Command 38 CLEAR FLAG STATUS REGISTER Command 39 READ IDENTIFICATION Operations 40 READ ID and MULTIPLE I/O READ ID Commands 40 READ SERIAL FLASH DISCOVERY PARAMETER Command 41 READ MEMORY Operations 45 3-Byte Address 45 4-Byte Address 46 READ MEMORY Operations Timing Single Transfer Rate 48 READ MEMORY Operations Timing Double Transfer Rate 52 PROGRAM Operations 56 WRITE Operations 61 WRITE ENABLE Command 61 WRITE DISABLE Command 61 ERASE Operations 63 SUBSECTOR ERASE Command 63 SECTOR ERASE Command 63 DIE ERASE Command 64 BULK ERASE Command 65

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.
512Mb, 1.8V, Multiple I/O Serial Flash Memory Features
Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.
512Mb, 1.8V, Multiple I/O Serial Flash Memory Features

List of Figures

Figure 1 Logic Diagram 7 Figure 2 8-Lead, VDFPN8 MLP8 Top View 8 Figure 3 24-Ball TBGA Balls Down 8 Figure 4 16-Pin SO16 Top View 9 Figure 5 Block Diagram 12 Figure 6 Bus Master and Memory Devices on the SPI Bus 17 Figure 7 SPI Modes 17 Figure 8 Internal Configuration Register 19 Figure 9 Upper and Lower Memory Array Segments 24 Figure 10 READ REGISTER Command 33 Figure 11 WRITE REGISTER Command 35 Figure 12 READ LOCK REGISTER Command 38 Figure 13 WRITE LOCK REGISTER Command 39 Figure 14 READ ID and MULTIPLE I/O Read ID Commands 41 Figure 15 READ Command 48 Figure 16 FAST READ Command 48 Figure 17 DUAL OUTPUT FAST READ Command 49 Figure 18 DUAL INPUT/OUTPUT FAST READ Command 49 Figure 19 QUAD OUTPUT FAST READ Command 50 Figure 20 QUAD INPUT/OUTPUT FAST READ Command 51 Figure 21 FAST READ Command DTR 52 Figure 22 DUAL OUTPUT FAST READ Command DTR 53 Figure 23 DUAL INPUT/OUTPUT FAST READ Command DTR 53 Figure 24 QUAD OUTPUT FAST READ Command DTR 54 Figure 25 QUAD INPUT/OUTPUT FAST READ Command DTR 54 Figure 26 PAGE PROGRAM Command 57 Figure 27 DUAL INPUT FAST PROGRAM Command 58 Figure 28 EXTENDED DUAL INPUT FAST PROGRAM Command 58 Figure 29 QUAD INPUT FAST PROGRAM Command 59 Figure 30 EXTENDED QUAD INPUT FAST PROGRAM Command 60 Figure 31 WRITE ENABLE and WRITE DISABLE Command Sequence 62 Figure 32 SUBSECTOR and SECTOR ERASE Command 64 Figure 33 DIE ERASE Command 65 Figure 34 BULK ERASE Command 66 Figure 35 RESET ENABLE and RESET MEMORY Command 69 Figure 36 READ OTP Command 70 Figure 37 PROGRAM OTP Command 71 Figure 38 XIP Mode Directly After Power-On 74 Figure 39 Power-Up Timing 76 Figure 40 Reset AC Timing During PROGRAM or ERASE Cycle 79 Figure 41 Reset Enable 79 Figure 42 Serial Input Timing 79 Figure 43 Write Protect Setup and Hold During WRITE STATUS REGISTER Operation SRWD = 1 80 Figure 44 Hold Timing 81 Figure 45 Output Timing 81 Figure 46 VPPH Timing 82 Figure 47 AC Timing Input/Output Reference Levels 84 Figure 48 V-PDFN-8/8mm x 6mm 88 Figure 49 SOP2-16/300 mils 89 Figure 50 T-PBGA-24b05/6mm x 8mm 90

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.
512Mb, 1.8V, Multiple I/O Serial Flash Memory Features

List of Tables

Table 1 Signal Descriptions 10 Table 2 Sectors[1023:0] 13 Table 3 Data Protection Using Device Protocols 14 Table 4 Memory Sector Protection Truth Table 14 Table 5 Protected Area Sizes Upper Area 14 Table 6 Protected Area Sizes Lower Area 15 Table 7 SPI Modes 16 Table 8 Extended, Dual, and Quad SPI Protocols 18 Table 9 Status Register Bit Definitions 20 Table 10 Nonvolatile Configuration Register Bit Definitions 21 Table 11 Volatile Configuration Register Bit Definitions 22 Table 12 Sequence of Bytes During Wrap 23 Table 13 Supported Clock Frequencies STR 23 Table 14 Supported Clock Frequencies DTR 23 Table 15 Extended Address Register Bit Definitions 25 Table 16 Enhanced Volatile Configuration Register Bit Definitions 25 Table 17 Flag Status Register Bit Definitions 26 Table 18 Command Set 28 Table 19 Lock Register 36 Table 20 Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands 40 Table 21 Read ID Data Out 40 Table 22 Extended Device ID, First Byte 40 Table 23 Serial Flash Discovery Parameter Data Structure 42 Table 24 Parameter ID 42 Table 25 Command/Address/Data Lines for READ MEMORY Commands 45 Table 26 Command/Address/Data Lines for READ MEMORY Commands 4-Byte Address 46 Table 27 Data/Address Lines for PROGRAM Commands 56 Table 28 Suspend Parameters 67 Table 29 Operations Allowed/Disallowed During Device States 67 Table 30 Reset Command Set 69 Table 31 OTP Control Byte 64 71 Table 32 XIP Confirmation Bit 74 Table 33 Effects of Running XIP in Different Protocols 74 Table 34 Power-Up Timing and VWI Threshold 77 Table 35 AC RESET Conditions 78 Table 36 Absolute Ratings 83 Table 37 Operating Conditions 83 Table 38 Input/Output Capacitance 83 Table 39 AC Timing Input/Output Conditions 84 Table 40 DC Current Characteristics and Operating Conditions 85 Table 41 DC Voltage Characteristics and Operating Conditions 85 Table 42 AC Characteristics and Operating Conditions 86 Table 43 Part Number Information 91 Table 44 Package Details 92

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.
512Mb, 1.8V, Multiple I/O Serial Flash Memory Device Description

Device Description

The N25Q is a high-performance multiple input/output serial Flash memory device manufactured on 65nm NOR technology. It features execute-in-place XIP functionality, advanced write protection mechanisms, and a high-speed SPI-compatible bus interface. Innovative, high-performance, dual and quad input/output instructions enable double or quadruple the transfer bandwidth for READ and PROGRAM operations.

The 512Mb N25Q stacked device contains two 256Mb die. From a user standpoint this stacked device behaves as a monolithic device, except with regard to READ MEMORY and ERASE operations and status polling. The device contains a single chip select S# a dual-chip version is also available. Contact the factory for more information.

The memory is organized as 1024 64KB main sectors that are further divided into 16 subsectors each 16,384 subsectors in total . The memory can be erased one 4KB subsector at a time, 64KB sectors at a time, or single die 256Mb at a time.

The memory can be write protected by software through volatile and nonvolatile protection features, depending on the application needs. The protection granularity is of 64KB sector granularity for volatile protections

The device has 64 one-time programmable OTP bytes that can be read and programmed with the READ OTP and PROGRAM OTP commands. These 64 bytes can also be permanently locked with a PROGRAM OTP command.

The device can also pause and resume PROGRAM and ERASE cycles by using dedicated PROGRAM/ERASE SUSPEND and RESUME instructions.
3-Byte Address and 4-Byte Address Modes

The device features 3-byte or 4-byte address modes to access memory beyond 128Mb.

When 4-byte address mode is enabled, all commands requiring an address must be entered and exited with a 4-byte address mode command ENTER 4-BYTE ADDRESS MODE command and EXIT 4-BYTE ADDRESS MODE command. The 4-byte address mode can also be enabled through the nonvolatile configuration register. See Registers for more information.

Operating Protocols

The memory can be operated with three different protocols:
• Extended SPI standard SPI protocol upgraded with dual and quad operations
• Dual I/O SPI
• Quad I/O SPI

The standard SPI protocol is extended and enhanced by dual and quad operations. In addition, the dual SPI and quad SPI protocols improve the data access time and throughput of a single I/O device by transmitting commands, addresses, and data across two or four data lines.

Each protocol contains unique commands to perform READ operations in DTR mode. This enables high data throughput while running at lower clock frequencies.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.
512Mb, 1.8V, Multiple I/O Serial Flash Memory Device Description

XIP Mode

XIP mode requires only an address no instruction to output data, improving random access time and eliminating the need to shadow code onto RAM for fast execution.

Nonvolatile configuration register bits can set XIP mode as the default mode for applications that must enter XIP mode immediately after powering up.

All protocols support XIP operation. For flexibility, multiple XIP entry and exit methods are available. For applications that must enter XIP mode immediately after power-up, nonvolatile configuration register bit settings can enable XIP as the default mode.

Device Configurability

The N25Q family offers additional features that are configured through the nonvolatile configuration register for default and/or nonvolatile settings. Volatile settings can be configured through the volatile and volatile-enhanced configuration registers. These configurable features include the following:
• Number of dummy cycles for the fast READ commands
• Output buffer impedance
• SPI protocol types extended SPI, dual SPI, or quad SPI
• Required XIP mode
• Enabling/disabling HOLD RESET function
• Enabling/disabling wrap mode

Figure 1 Logic Diagram

DQ0 C S#

VPP/W#/DQ2 HOLD#/DQ3

DQ1 RESET2
Note Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for more details.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.

Signal Assignments
512Mb, 1.8V, Multiple I/O Serial Flash Memory Signal Assignments

Figure 2 8-Lead, VDFPN8 MLP8 Top View

DQ1 2

W#/VPP/DQ2 3 VSS 4
8 VCC 7 HOLD#/DQ3
5 DQ0

On the underside of the MLP8 package, there is an exposed central pad that is pulled internally to VSS and must not be connected to any other voltage or signal line on the PCB.
Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for complete package names and details.

Figure 3 24-Ball TBGA Balls Down

NC RESET/NC

NC W#/VPP/DQ2 NC

DQ1 DQ0 HOLD#/DQ3 NC
Note Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for complete package names and details.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.
512Mb, 1.8V, Multiple I/O Serial Flash Memory Signal Assignments

Figure 4 16-Pin SO16 Top View

HOLD#/DQ3 1 VCC 2

RESET/DNU2 3 DNU 4 DNU 5 DNU 6 S# 7 DQ1 8
16 C 15 DQ0 14 DNU 13 DNU 12 DNU 11 DNU 10 VSS
9 W#/VPP/DQ2
Note Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for complete package names and details.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.
512Mb, 1.8V, Multiple I/O Serial Flash Memory Signal Descriptions

Signal Descriptions

The signal description table below is a comprehensive list of signals for the N25 family devices. All signals listed may not be supported on this device. See Signal Assignments for information specific to this device.

Table 1 Signal Descriptions

Symbol C S#

DQ2 DQ3 RESET#

Type Input

Input and I/O

Output and I/O

Input and I/O

Input and I/O Control Input

Clock Provides the timing of the serial interface. Commands, addresses, or data present at serial data inputs are latched on the rising edge of the clock. Data is shifted out on the falling edge of the clock.

Chip select When S# is HIGH, the device is deselected and DQ1 is at High-Z. When in extended SPI mode, with the device deselected, DQ1 is tri-stated. Unless an internal PROGRAM, ERASE, or WRITE STATUS REGISTER cycle is in progress, the device enters standby power mode not deep power-down mode . Driving S# LOW enables the device, placing it in the active power mode. After power-up, a falling edge on S# is required prior to the start of any command.

Serial data Transfers data serially into the device. It receives command codes, addresses, and the data to be programmed. Values are latched on the rising edge of the clock. DQ0 is used for input/output during the following operations DUAL OUTPUT FAST READ, QUAD OUTPUT FAST READ, DUAL INPUT/OUTPUT FAST READ, and QUAD INPUT/OUTPUT FAST READ. When used for output, data is shifted out on the falling edge of the clock. In DIO-SPI, DQ0 always acts as an input/output. In QIO-SPI, DQ0 always acts as an input/output, with the exception of the PROGRAM or ERASE cycle performed with VPP. The device temporarily enters the extended SPI protocol and then returns to QIO-SPI as soon as VPP goes LOW.

Serial data:Transfers data serially out of the device. Data is shifted out on the falling edge of the clock. DQ1 is used for input/output during the following operations DUAL INPUT FAST PROGRAM, QUAD INPUT FAST PROGRAM, DUAL INPUT EXTENDED FAST PROGRAM, and QUAD INPUT EXTENDED FAST PROGRAM. When used for input, data is latched on the rising edge of the clock. In DIO-SPI, DQ1 always acts as an input/output. In QIO-SPI, DQ1 always acts as an input/output, with the exception of the PROGRAM or ERASE cycle performed with the enhanced program supply voltage VPP . In this case the device temporarily enters the extended SPI protocol and then returns to QIO-SPI as soon as VPP goes LOW.

DQ2 When in QIO-SPI mode or in extended SPI mode using QUAD FAST READ commands, the signal functions as DQ2, providing input/output. All data input drivers are always enabled except when used as an output. Micron recommends customers drive the data signals normally to avoid unnecessary switching current and float the signals before the memory device drives data on them.

DQ3 When in quad SPI mode or in extended SPI mode using quad FAST READ commands, the signal functions as DQ3, providing input/output. HOLD# is disabled and RESET# is disabled if the device is selected.

RESET This is a hardware RESET# signal. When RESET# is driven HIGH, the memory is in the normal operating mode. When RESET# is driven LOW, the memory enters reset mode and output is High-Z. If RESET# is driven LOW while an internal WRITE, PROGRAM, or ERASE operation is in progress, data may be lost.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.
512Mb, 1.8V, Multiple I/O Serial Flash Memory Signal Descriptions

Table 1 Signal Descriptions Continued

Symbol HOLD#

VCC VSS DNU NC

Type Control Input

Control Input

Power

Power Ground

HOLD Pauses any serial communications with the device without deselecting the device. DQ1 output is High-Z. DQ0 input and the clock are "Don't Care." To enable HOLD, the device must be selected with S# driven LOW. HOLD# is used for input/output during the following operations QUAD OUTPUT FAST READ, QUAD INPUT/OUTPUT FAST READ, QUAD INPUT FAST PROGRAM, and QUAD INPUT EXTENDED FAST PROGRAM. In QIO-SPI, HOLD# acts as an I/O DQ3 functionality , and the HOLD# functionality is disabled when the device is selected. When the device is deselected S# is HIGH in parts with RESET# functionality, it is possible to reset the device unless this functionality is not disabled by means of dedicated registers bits. The HOLD# functionality can be disabled using bit 4 of the NVCR or bit 4 of the VECR. On devices that include DTR mode capability, the HOLD# functionality is disabled as soon as a DTR operation is recognized.

Write protect W# can be used as a protection control input or in QIO-SPI operations. When in extended SPI with single or dual commands, the WRITE PROTECT function is selectable by the voltage range applied to the signal. If voltage range is low 0V to VCC , the signal acts as a write protection control input. The memory size protected against PROGRAM or ERASE operations is locked as specified in the status register block protect bits W# is used as an input/output DQ2 functionality during QUAD INPUT FAST READ and QUAD INPUT/OUTPUT FAST READ operations and in QIO-SPI.

Supply voltage If VPP is in the voltage range of VPPH, the signal acts as an additional power supply, as defined in the AC Measurement Conditions table. During QIFP, QIEFP, and QIO-SPI PROGRAM/ERASE operations, it is possible to use the additional VPP power supply to speed up internal operations. However, to enable this functionality, it is necessary to set bit 3 of the VECR to In this case, VPP is used as an I/O until the end of the operation. After the last input data is shifted in, the application should apply VPP voltage to VPP within 200ms to speed up the internal operations. If the VPP voltage is not applied within 200ms, the PROGRAM/ERASE operations start at standard speed. The default value of VECR bit 3 is 1, and the VPP functionality for quad I/O modify operations is disabled.

Device core power supply Source voltage.

Ground Reference for the VCC supply voltage.

Do not use.

No connect.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.
512Mb, 1.8V, Multiple I/O Serial Flash Memory Organization

Memory Organization

Memory Configuration and Block Diagram

The memory is a stacked device comprised of two 256Mb chips. Each chip is internally partitioned into two 128Mb segments. Each page of memory can be individually programmed. Bits are programmed from one through zero. The device is subsector, sector, or single 256Mb chip erasable, but not page-erasable. Bits are erased from zero through one. The memory is configured as 67,108,864 bytes 8 bits each 1024 sectors 64KB each 16,384 subsectors 4KB each and 262,144 pages 256 bytes each and 64 OTP bytes are located outside the main memory array.
Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.
512Mb, 1.8V, Multiple I/O Serial Flash Memory Package Dimensions

Figure 49 SOP2-16/300 mils

MIN/ MAX
h x 45°

MIN/ MAX
0° MIN/8° MAX

MIN/ MAX

TYP Z

MIN/ MAX
Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.

Figure 50 T-PBGA-24b05/6mm x 8mm
512Mb, 1.8V, Multiple I/O Serial Flash Memory Package Dimensions

Seating plane A
54321

Ball A1 ID

A B C 8 D E

Ball A1 ID
Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.
512Mb, 1.8V, Multiple I/O Serial Flash Memory Part Number Ordering Information
Part Number Ordering Information

Micron Serial NOR Flash devices are available in different configurations and densities. Verify valid part numbers by using Micron’s part catalog search at micron.com. To compare features and specifications by device type, visit micron.com/products. Contact the factory for devices not found.

For more information on how to identify products and top-side marking by the process identification letter, refer to technical note TN-12-24, "Serial Flash Memory Device Marking for the M25P, M25PE, M25PX, and N25Q Product Families."

Table 43 Part Number Information

Part Number Category

Device type Density Technology Feature set

Operating voltage Block structure Package RoHS-compliant Temperature and test flow

Security features Shipping material

Category Details

N25Q = Serial NOR Flash memory, Multiple Input/Output Single, Dual, Quad I/O , XIP
512 = 512Mb

A = 65nm
1 = Byte addressability HOLD pin Micron XIP
2 = Byte addressability HOLD pin Basic XIP
3 = Byte addressability RESET# pin Micron XIP
4 = Byte addressability RESET# pin Basic XIP
7 = Byte addressability HOLD pin Micron XIP
8 = Byte addressability RESET# pin HOLD pin Micron XIP
1 = VCC = to 2.0V G = Uniform 64KB and 4KB , easy transparent stack

F8 = V-PDFN-8/8mm x 6mm RP SF = SOP2-16/300mils 12 = T-PBGA-24b05/6mm x 8mm
4 = IT to 85°C Device tested with standard test flow A = Automotive temperature range, to 125°C Device tested with high reliability certified test flow H = IT to 85°C Device tested with high reliability certified test flow
0 = Default See the Security Ordering Information table below.

E = Tray F = Tape and reel G = Tube

Notes 1 2 3

Enter 4-byte address mode and exit 4-byte address mode supported.
4-byte addressing mode is the default at power-up. Enter and exit 4-byte addressing mode are not supported.

See the table below for additional information.

Additional secure options are available upon customer request.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.
512Mb, 1.8V, Multiple I/O Serial Flash Memory Part Number Ordering Information

Table 44 Package Details

Micron SPI and JEDEC V-PDFN-8/8mm x 6mm RP

SOP2-16/300mil

T-PBGA-24b05/6x8

Names

Shortened M25P and M45PE DFN-8/8mm MLP8, VDFPN8

SO16W TBGA 24

SO16W, SO16 wide 300 mil body width

TBGA24 6mm x 8mm

Alternate V-PSON1-8/8mm x 6mm, VSON

SOIC-16/300 mil, SOP 16L 300 mil

T-PBGA-24b05/6x8

Very thin, plastic smalloutline, 8 terminal pads no leads , 8mm x 6mm

Small-outline integrated circuit, 16-pin, wide 300 mil

Thin, plastic-ball grid array, 24-ball, 6mm x 8mm

M25P M45PE N25Q

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.
• In Command Set table, updated value for Quad I/O FAST READ DTR from 3Dh to 6Dh
pin Micron XIP
• Corrected RESET ENABLE and RESET MEMORY command timing diagram
• Removed ICC1 grade 3 in the DC Current Characteristics and Operating Conditions table
• Updated the READ ID Operation figure in READ ID Operations
• Updated ERASE Operations
• Added link to part number chart in Part Number Ordering Information
• Updated part numbers in Features
• Typo fix in Command Set table in Command Definitions Dual I/O FAST READ - DTR from DBh to BDh
• Typo fix in Supported Clock Frequencies - DTR table in Nonvolatile and Volatile Registers
• Updated tSSE specification in AC Reset Conditions table
• Added V-PDFN 8/8mm x 6mm package
• Updated AC Reset Specifications to include Write Protect Setup and Hold WRITE STATUS REGISTER Operation SRWD = 1 timing diagram

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.
• Updated AC Reset Specifications to include power-down values
• Correction to bit 1:0 A24 in Description corrected to A[25:24] of Extended Address Register Bit Definitions table in Nonvolatile and Volatile Registers
• Initial release
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel 208-368-3900 Customer Comment Line 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived N25Q512A11G1240FTR Datasheet file may be downloaded here without warranties.

Datasheet ID: N25Q512A11G1240FTR 648537