9ZX21901CKLF

9ZX21901CKLF Datasheet

9ZX21901C

Part	Datasheet
9ZX21901CKLF	9ZX21901CKLF (pdf)

Related Parts	Information
9ZX21901CKLFT	9ZX21901CKLFT

PDF Datasheet Preview
DATASHEET 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 9ZX21901C The 9ZX21901 is Intel DB1900Z Differential Buffer suitable for PCIExpress Gen3 or QPI applications.The part is backwards compatible to PCIe Gen1 and Gen2. A fixed external feedback maintains low drift for critical QPI applications. In bypass mode, the 9ZX21901 can provide outputs up to 400MHz. Recommended Application 19 output PCIe Gen3/QPI buffer with fixed feedback for Romley platforms Output Features • 19 - 0.7V current mode differential HCSL output pairs Features/Benefits • Fixed feedback path/ 0ps input-to-output delay • 9 Selectable SMBus addresses/ Multiple devices can share same SMBus segment • 8 dedicated OE# pins/ hardware control of outputs • PLL or bypass mode/ PLL can dejitter incoming clock • Selectable PLL BW/ minimizes jitter peaking in downstream PLL's • Spread spectrum compatible/tracks spreading input clock for EMI reduction • SMBus Interface/ unused outputs can be disabled • 100MHz & 133.33MHz PLL mode/ Legacy QPI support • Undriven differential outputs in Power Down mode for maximum power savings Key Specifications • Cycle-to-cycle jitter < 50ps • Output-to-output skew <65ps • Input-to-output delay Fixed at 0 ps • Input-to-output delay variation <50ps • Phase jitter PCIe Gen3 < 1ps rms • Phase jitter QPI 9.6GB/s < 0.2ps rms Functional Block Diagram OE 5_12 # 8 DIF_IN# HIBW_BYPM_LOBW# 100M_133M# CKPWRGD/PD# SMB_A0_tri SMB_A1_tri SMBDAT SMBCLK Logic Z-PLL SS Compatible Note Even though the feedback is fixed, DFB_OUT still needs a termination network for the part to function. DFB_OUT DIF 18:0 IREF 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1648H - 12/08/11 9ZX21901C 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI Pin Configuration DIF_18# DIF_18 DIF_17# DIF_17 VDD DIF_16# DIF_16 DIF_15# DIF_15 GND DIF_14# DIF_14 DIF_13# DIF_13 VDD OE12# DIF_12# DIF_12 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 VDDA 1 54 OE11# GNDA 2 53 DIF_11# IREF 3 Ordering Information Part / Order Number 9ZX21901CKLF 9ZX21901CKLFT Shipping Package Trays Tape and Reel Package 72-pin MLF 72-pin MLF Temperature 0 to +70°C 0 to +70°C "LF" designates PB-free configuration, RoHS compliant. 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI 1648H- 12/08/11 9ZX21901C 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI Page # 1/20/2010 RDW Initial release Various Corrected input clock on block diagram, updated QPI reference to 9.6GTs, added note about fixed feedback path, added comment about DFB_OUT needed termination A 6/10/2010 RDW network. Reformatted electrical tables to fit new standard format 1,5,6,9 Added output termination/test load drawing and table Released to final 6/22/201 RDW Merged Phase Jitter Tables into Single Table. Reformatted Electrical Tables into common format for future datasheets. Updated front page to standard 9ZX format. C 8/3/2010 RDW Clarified that SMBus Address Selection table includes the Read/Write Bit. Minor clarifications to other tables. Added additive phase jitter table for bypass mode. 1-3, 5-11 D 3/2/2011 RDW Added rise/fall varation spec to HCSL_Out table E 5/11/2011 RDW Added note to pinout indicating that the DFB_OUT pins must be terminated. 9/20/2011 Added "Case Temperature" Thermal Char data specs. Various G 10/24/2011 LPL Updated Thermal Characteristics table. H 12/8/2011 RDW Updated tDSPO_BYP parameter from +/-350 to +/-250ps. Innovate with IDT and accelerate your future networks. Contact: For Sales 800-345-7015 408-284-8200 Fax 408-284-2775 For Tech Support 408-284-6578 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 outside U.S.

PDF Datasheet Preview

DATASHEET
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
9ZX21901C

The 9ZX21901 is Intel DB1900Z Differential Buffer suitable for PCIExpress Gen3 or QPI applications.The part is backwards compatible to PCIe Gen1 and Gen2. A fixed external feedback maintains low drift for critical QPI applications. In bypass mode, the 9ZX21901 can provide outputs up to 400MHz.

Recommended Application
19 output PCIe Gen3/QPI buffer with fixed feedback for Romley platforms

Output Features
• 19 - 0.7V current mode differential HCSL output pairs

Features/Benefits
• Fixed feedback path/ 0ps input-to-output delay
• 9 Selectable SMBus addresses/ Multiple devices can share same SMBus segment
• 8 dedicated OE# pins/ hardware control of outputs
• PLL or bypass mode/ PLL can dejitter incoming clock
• Selectable PLL BW/ minimizes jitter peaking in downstream PLL's
• Spread spectrum compatible/tracks spreading input clock for EMI reduction
• SMBus Interface/ unused outputs can be disabled
• 100MHz & 133.33MHz PLL mode/ Legacy QPI support
• Undriven differential outputs in Power Down mode for maximum power savings

Key Specifications
• Cycle-to-cycle jitter < 50ps
• Output-to-output skew <65ps
• Input-to-output delay Fixed at 0 ps
• Input-to-output delay variation <50ps
• Phase jitter PCIe Gen3 < 1ps rms
• Phase jitter QPI 9.6GB/s < 0.2ps rms

Functional Block Diagram

OE 5_12 # 8

DIF_IN#

HIBW_BYPM_LOBW# 100M_133M# CKPWRGD/PD# SMB_A0_tri SMB_A1_tri

SMBDAT SMBCLK

Logic

Z-PLL SS Compatible

Note Even though the feedback is fixed, DFB_OUT still needs a termination network for the part to function.

DFB_OUT DIF 18:0

IREF
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
1648H - 12/08/11
9ZX21901C 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI

Pin Configuration

DIF_18# DIF_18 DIF_17# DIF_17 VDD DIF_16# DIF_16 DIF_15# DIF_15 GND DIF_14# DIF_14 DIF_13# DIF_13 VDD OE12# DIF_12# DIF_12
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55

VDDA 1
54 OE11#

GNDA 2
53 DIF_11#

IREF 3
Ordering Information

Part / Order Number 9ZX21901CKLF 9ZX21901CKLFT

Shipping Package Trays

Tape and Reel

Package 72-pin MLF 72-pin MLF

Temperature 0 to +70°C 0 to +70°C
"LF" designates PB-free configuration, RoHS compliant.
19-Output Differential Zbuffer for PCIe Gen2/3 and QPI
1648H- 12/08/11
9ZX21901C 19-Output Differential Zbuffer for PCIe Gen2/3 and QPI

Page #
1/20/2010 RDW Initial release

Various

Corrected input clock on block diagram, updated QPI reference to 9.6GTs, added
note about fixed feedback path, added comment about DFB_OUT needed termination

A 6/10/2010 RDW network. Reformatted electrical tables to fit new standard format
1,5,6,9

Added output termination/test load drawing and table

Released to final
6/22/201 RDW Merged Phase Jitter Tables into Single Table.

Reformatted Electrical Tables into common format for future datasheets.

Updated front page to standard 9ZX format.

C 8/3/2010 RDW Clarified that SMBus Address Selection table includes the Read/Write Bit. Minor clarifications to other tables.

Added additive phase jitter table for bypass mode.
1-3, 5-11

D 3/2/2011 RDW Added rise/fall varation spec to HCSL_Out table

E 5/11/2011 RDW Added note to pinout indicating that the DFB_OUT pins must be terminated.
9/20/2011

Added
"Case Temperature" Thermal Char data
specs.

Various

G 10/24/2011 LPL Updated Thermal Characteristics table.

H 12/8/2011 RDW Updated tDSPO_BYP parameter from +/-350 to +/-250ps.

Innovate with IDT and accelerate your future networks. Contact:

For Sales
800-345-7015 408-284-8200 Fax 408-284-2775

For Tech Support
408-284-6578

Corporate Headquarters

Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 outside U.S.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 9ZX21901CKLF Datasheet file may be downloaded here without warranties.

Datasheet ID: 9ZX21901CKLF 636921