N25Q016A11EF640F TR

N25Q016A11EF640F TR Datasheet

1.8V, Multiple I/O, 4KB Sector Erase N25Q016A11E

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N25Q016A11EF640F TR	N25Q016A11EF640F TR (pdf)

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16Mb, Multiple I/O Serial Flash Memory Features Micron Serial NOR Flash Memory 1.8V, Multiple I/O, 4KB Sector Erase N25Q016A11E • SPI-compatible serial bus interface • 108 MHz MAX clock frequency • single supply voltage • Dual/quad I/O instruction provides increased throughput up to 432 MB/s • Supported protocols Extended SPI, dual I/O, and quad I/O • Execute-in-place XIP mode for all three protocols Configurable via volatile or nonvolatile registers Enables memory to work in XIP mode directly af- ter power-on • PROGRAM/ERASE SUSPEND operations • Continuous read of entire memory via a single com- mand Fast read Quad or dual output fast read Quad or dual I/O fast read • Flexible to fit application Configurable number of dummy cycles Output buffer configurable • Software reset • Hardware RESET function available upon customer request • 64-byte, user-lockable, one-time programmable OTP dedicated area • Erase capability Subsector erase 4KB uniform granularity blocks Subsector erase 32KB uniform granularity blocks Sector erase 64KB uniform granularity blocks • Deep power-down mode 5µA TYP • Write protection Software write protection applicable to every 64KB sector via volatile lock bit Hardware write protection protected area size defined by five nonvolatile bits BP0, BP1, BP2, and TB Additional smart protections, available upon request • Electronic signature JEDEC-standard 2-byte signature BB15h Two additional extended device ID EDID bytes to identify device factory options Unique ID code UID 14 read-only bytes • Minimum 100,000 ERASE cycles per sector • More than 20 years data retention • Packages JEDEC standard, all RoHS compliant F4 = U-PDFN-8/4mm x 3mm MLP8 F6 = V-PDFN-8/6mm x 5mm MLP8 SC = SOP2-8/150 mil SO8N 51 = XF-SCSP-8/2mm x 2.8mm XFCSP Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 16Mb, Multiple I/O Serial Flash Memory Features Contents Device Description 6 Features 6 3-Byte Address Modes 6 Operating Protocols 6 XIP Mode 6 Device Configurability 7 Signal Assignments 8 Signal Descriptions 9 Memory Organization 11 Memory Configuration and Block Diagram 11 Memory Map 12 Device Protection 13 Serial Peripheral Interface Modes 15 SPI Protocols 17 Nonvolatile and Volatile Registers 18 Status Register 19 Nonvolatile and Volatile Configuration Registers 20 Enhanced Volatile Configuration Register 23 Flag Status Register 24 Command Definitions 25 READ REGISTER and WRITE REGISTER Operations 27 READ STATUS REGISTER or FLAG STATUS REGISTER Command 27 READ NONVOLATILE CONFIGURATION REGISTER Command 28 READ VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command 28 WRITE STATUS REGISTER Command 28 WRITE NONVOLATILE CONFIGURATION REGISTER Command 29 WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command 29 READ LOCK REGISTER Command 30 WRITE LOCK REGISTER Command 31 CLEAR FLAG STATUS REGISTER Command 32 READ IDENTIFICATION Operations 33 READ ID and MULTIPLE I/O READ ID Commands 33 READ SERIAL FLASH DISCOVERY PARAMETER Command 34 READ MEMORY Operations 38 PROGRAM Operations 42 WRITE Operations 47 WRITE ENABLE Command 47 WRITE DISABLE Command 47 ERASE Operations 49 SUBSECTOR ERASE Command 49 SECTOR ERASE Command 49 BULK ERASE Command 50 PROGRAM/ERASE SUSPEND Command 51 PROGRAM/ERASE RESUME Command 53 RESET Operations 54 RESET ENABLE and RESET MEMORY Command 54 RESET Conditions 54 ONE TIME PROGRAMMABLE Operations 55 READ OTP ARRAY Command 55 PROGRAM OTP ARRAY Command 55 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 16Mb, Multiple I/O Serial Flash Memory Features XIP Mode 57 Activate or Terminate XIP Using Volatile Configuration Register 57 Activate or Terminate XIP Using Nonvolatile Configuration Register 57 Confirmation Bit Settings Required to Activate or Terminate XIP 58 Terminating XIP After a Controller and Memory Reset 58 Power Up and Power Down 60 Power Up and Power Down Requirements 60 Power Loss Recovery Sequence 61 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 16Mb, Multiple I/O Serial Flash Memory Features List of Figures Figure 1 Logic Diagram 7 Figure 2 SO8N, MLP8 TSOP Top View 8 Figure 3 8-Balls, XFCSP, 2mm x 2.8mm x 0.37mm Top View 8 Figure 4 Block Diagram 11 Figure 5 Bus Master and Memory Devices on the SPI Bus 16 Figure 6 SPI Modes 16 Figure 7 Internal Configuration Register 18 Figure 8 READ REGISTER Command 27 Figure 9 WRITE REGISTER Command 29 Figure 10 READ LOCK REGISTER Command 31 Figure 11 WRITE LOCK REGISTER Command 32 Figure 12 READ ID and MULTIPLE I/O Read ID Commands 34 Figure 13 READ Command 39 Figure 14 FAST READ Command 39 Figure 15 DUAL OUTPUT FAST READ 40 Figure 16 DUAL INPUT/OUTPUT FAST READ Command 40 Figure 17 QUAD OUTPUT FAST READ Command 41 Figure 18 QUAD INPUT/OUTPUT FAST READ Command 41 Figure 19 PAGE PROGRAM Command 43 Figure 20 DUAL INPUT FAST PROGRAM Command 44 Figure 21 EXTENDED DUAL INPUT FAST PROGRAM Command 44 Figure 22 QUAD INPUT FAST PROGRAM Command 45 Figure 23 EXTENDED QUAD INPUT FAST PROGRAM Command 46 Figure 24 WRITE ENABLE and WRITE DISABLE Command Sequence 48 Figure 25 SUBSECTOR and SECTOR ERASE Command 50 Figure 26 BULK ERASE Command 51 Figure 27 RESET ENABLE and RESET MEMORY Command 54 Figure 28 READ OTP Command 55 Figure 29 PROGRAM OTP Command 56 Figure 30 XIP Mode Directly After Power-On 58 Figure 31 Power-Up Timing 60 Figure 32 Reset AC Timing During PROGRAM or ERASE Cycle 63 Figure 33 Reset Enable 63 Figure 34 Serial Input Timing 63 Figure 35 Write Protect Setup and Hold During WRITE STATUS REGISTER Operation SRWD = 1 64 Figure 36 Hold Timing 64 Figure 37 Output Timing 65 Figure 38 VPPH Timing 65 Figure 39 AC Timing Input/Output Reference Levels 67 Figure 40 UFDFPN8-4x3 mm 71 Figure 41 DFN-6 x 5mm 72 Figure 42 S08N-150mils 73 Figure 43 XFCSP-2x2.8mm 74 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 16Mb, Multiple I/O Serial Flash Memory Features List of Tables Table 1 Signal Descriptions 9 Table 2 Sectors 31 0 12 Table 3 Data Protection using Device Protocols 13 Table 4 Memory Sector Protection Truth Table 13 Table 5 Protected Area Sizes Upper Area 14 Table 6 Protected Area Sizes Lower Area 14 Table 7 SPI Modes 15 Table 8 Extended, Dual, and Quad SPI Protocols 17 Table 9 Status Register Bit Definitions 19 Table 10 Nonvolatile Configuration Register Bit Definitions 20 Table 11 Volatile Configuration Register Bit Definitions 21 Table 12 Sequence of Bytes During Wrap 22 Table 13 Supported Clock Frequencies 22 Table 14 Enhanced Volatile Configuration Register Bit Definitions 23 Table 15 Flag Status Register Bit Definitions 24 Table 16 Command Set 25 Table 17 Lock Register 30 Table 18 Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands 33 Table 19 Read ID Data Out 33 Table 20 Extended Device ID, First Byte 33 Table 21 Serial Flash Discovery Parameter Data Structure 35 Table 22 Parameter ID 36 Table 23 Command/Address/Data Lines for READ MEMORY Commands 38 Table 24 Data/Address Lines for PROGRAM Commands 42 Table 25 Suspend Parameters 52 Table 26 Operations Allowed/Disallowed During Device States 52 Table 27 Reset Command Set 54 Table 28 OTP Control Byte 64 56 Table 29 XIP Confirmation Bit 58 Table 30 Effects of Running XIP in Different Protocols 58 Table 31 Power-Up Timing and VWI Threshold 61 Table 32 AC RESET Conditions 62 Table 33 Absolute Ratings 66 Table 34 Operating Conditions 66 Table 35 Input/Output Capacitance 66 Table 36 AC Timing Input/Output Conditions 67 Table 37 DC Current Characteristics and Operating Conditions 68 Table 38 DC Voltage Characteristics and Operating Conditions 68 Table 39 AC Characteristics and Operating Conditions 69 Table 40 Part Number Information 75 Table 41 Package Details 75 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 16Mb, Multiple I/O Serial Flash Memory Device Description Device Description The N25Q is the first high-performance multiple input/output serial Flash memory device manufactured on 65nm NOR technology. It features execute-in-place XIP functionality, advanced write protection mechanisms, and a high-speed SPI-compatible bus interface. The innovative, high-performance, dual and quad input/output instructions enable double or quadruple the transfer bandwidth for READ and PROGRAM operations. The memory is organized as 32 64KB main sectors that are divided into two subsectors each 32KB , that are further divided into eight 4KB subsectors each, 512 4KB subsectors in total. The memory can be erased one 4KB subsector at a time, one 32KB subsector at a time, one 64KB sector at a time, or as a whole. The memory can be write protected by software through volatile and nonvolatile protection features, depending on the application needs. The protection granularity is of 64KB sector granularity for volatile protections The device has 64 one-time programmable OTP bytes that can be read and programmed with the READ OTP and PROGRAM OTP commands. These 64 bytes can also be permanently locked with a PROGRAM OTP command. The device also has the ability to pause and resume PROGRAM and ERASE cycles by using dedicated PROGRAM/ERASE SUSPEND and RESUME instructions. 3-Byte Address Modes The device features 3-byte address modes to access the memory. Operating Protocols The memory can be operated with three different protocols: • Extended SPI standard SPI protocol upgraded with dual and quad operations • Dual I/O SPI • Quad I/O SPI The standard SPI protocol is extended and enhanced by dual and quad operations. In addition, the dual SPI and quad SPI protocols improve the data access time and throughput of a single I/O device by transmitting commands, addresses, and data across two or four data lines. XIP Mode XIP mode requires only an address no instruction to output data, improving random access time and eliminating the need to shadow code onto RAM for fast execution. All protocols support XIP operation. For flexibility, multiple XIP entry and exit methods are available. For applications that must enter XIP mode immediately after powering up, XIP mode can be set as the default mode through the nonvolatile configuration register bits. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 16Mb, Multiple I/O Serial Flash Memory Device Description Device Configurability The N25Q family offers additional features that are configured through the nonvolatile configuration register for default and/or nonvolatile settings. Volatile settings can be configured through the volatile and volatile-enhanced configuration registers. These configurable features include the following: • Number of dummy cycles for the fast READ commands • Output buffer impedance • SPI protocol types extended SPI, DIO-SPI, or QIO-SPI • Required XIP mode • Enabling/disabling HOLD RESET function • Enabling/disabling wrap mode Figure 1 Logic Diagram DQ0 C S# VPP/W#/DQ2 HOLD#/DQ3 VSS Note Reset functionality is available in devices with a dedicated part number. See Part Num- ber Ordering Information for more details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. Signal Assignments 16Mb, Multiple I/O Serial Flash Memory Signal Assignments Figure 2 SO8N, MLP8 TSOP Top View DQ1 2 W#/VPP/DQ2 3 VSS 4 8 VCC 7 HOLD#/DQ3 5 DQ0 Note Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for complete package names and details. Figure 3 8-Balls, XFCSP, 2mm x 2.8mm x 0.37mm Top View B HOLD#/DQ3 W#/VPP/DQ2 VSS Note Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for complete package names and details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 16Mb, Multiple I/O Serial Flash Memory Signal Descriptions Signal Descriptions The signal description table below is a comprehensive list of signals for the N25Q family devices. All signals listed may not be supported on this device. See Signal Assignments for information specific to this device. Table 1 Signal Descriptions Symbol C S# DQ2 DQ3 RESET# Type Input Input and I/O Output and I/O Input and I/O Input and I/O Control Input Clock Provides the timing of the serial interface. Commands, addresses, or data present at serial data inputs are latched on the rising edge of the clock. Data is shifted out on the falling edge of the clock. Chip select When S# is HIGH, the device is deselected and DQ1 is at High-Z. When in extended SPI mode, with the device deselected, DQ1 is tri-stated. Unless an internal PROGRAM, ERASE, or WRITE STATUS REGISTER cycle is in progress, the device enters standby power mode not deep power-down mode . Driving S# LOW enables the device, placing it in the active power mode. After power-up, a falling edge on S# is required prior to the start of any command. Serial data Transfers data serially into the device. It receives command codes, addresses, and the data to be programmed. Values are latched on the rising edge of the clock. DQ0 is used for input/output during the following operations DUAL OUTPUT FAST READ, QUAD OUTPUT FAST READ, DUAL INPUT/OUTPUT FAST READ, and QUAD INPUT/OUTPUT FAST READ. When used for output, data is shifted out on the falling edge of the clock. In DIO-SPI, DQ0 always acts as an input/output. In QIO-SPI, DQ0 always acts as an input/output, with the exception of the PROGRAM or ERASE cycle performed with VPP. The device temporarily enters the extended SPI protocol and then returns to QIO-SPI as soon as VPP goes LOW. Serial data:Transfers data serially out of the device. Data is shifted out on the falling edge of the clock. DQ1 is used for input/output during the following operations DUAL INPUT FAST PROGRAM, QUAD INPUT FAST PROGRAM, DUAL INPUT EXTENDED FAST PROGRAM, and QUAD INPUT EXTENDED FAST PROGRAM. When used for input, data is latched on the rising edge of the clock. In DIO-SPI, DQ1 always acts as an input/output. In QIO-SPI, DQ1 always acts as an input/output, with the exception of the PROGRAM or ERASE cycle performed with the enhanced program supply voltage VPP . In this case the device temporarily enters the extended SPI protocol and then returns to QIO-SPI as soon as VPP goes LOW. DQ2 When in QIO-SPI mode or in extended SPI mode using QUAD FAST READ commands, the signal functions as DQ2, providing input/output. All data input drivers are always enabled except when used as an output. Micron recommends customers drive the data signals normally to avoid unnecessary switching current and float the signals before the memory device drives data on them. DQ3 When in quad SPI mode or in extended SPI mode using quad FAST READ commands, the signal functions as DQ3, providing input/output. HOLD# is disabled and RESET# is disabled if the device is selected. RESET This is a hardware RESET# signal. When RESET# is driven HIGH, the memory is in the normal operating mode. When RESET# is driven LOW, the memory enters reset mode and output is High-Z. If RESET# is driven LOW while an internal WRITE, PROGRAM, or ERASE operation is in progress, data may be lost. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 16Mb, Multiple I/O Serial Flash Memory Signal Descriptions Table 1 Signal Descriptions Continued Symbol HOLD# VCC VSS DNU NC Type Control Input Control Input Power Power Ground HOLD Pauses any serial communications with the device without deselecting the device. DQ1 output is High-Z. DQ0 input and the clock are "Don't Care." To enable HOLD, the device must be selected with S# driven LOW. HOLD# is used for input/output during the following operations QUAD OUTPUT FAST READ, QUAD INPUT/OUTPUT FAST READ, QUAD INPUT FAST PROGRAM, and QUAD INPUT EXTENDED FAST PROGRAM. In QIO-SPI, HOLD# acts as an I/O DQ3 functionality , and the HOLD# functionality is disabled when the device is selected. When the device is deselected S# is HIGH in parts with RESET# functionality, it is possible to reset the device unless this functionality is not disabled by means of dedicated registers bits. The HOLD# functionality can be disabled using bit 4 of the NVCR or bit 4 of the VECR. Write protect W# can be used as a protection control input or in QIO-SPI operations. When in extended SPI with single or dual commands, the WRITE PROTECT function is selectable by the voltage range applied to the signal. If voltage range is low 0V to VCC , the signal acts as a write protection control input. The memory size protected against PROGRAM or ERASE operations is locked as specified in the status register block protect bits W# is used as an input/output DQ2 functionality during QUAD INPUT FAST READ and QUAD INPUT/OUTPUT FAST READ operations and in QIO-SPI. Supply voltage If VPP is in the voltage range of VPPH, the signal acts as an additional power supply, as defined in the AC Measurement Conditions table. During QIFP, QIEFP, and QIO-SPI PROGRAM/ERASE operations, it is possible to use the additional VPP power supply to speed up internal operations. However, to enable this functionality, it is necessary to set bit 3 of the VECR to In this case, VPP is used as an I/O until the end of the operation. After the last input data is shifted in, the application should apply VPP voltage to VPP within 200ms to speed up the internal operations. If the VPP voltage is not applied within 200ms, the PROGRAM/ERASE operations start at standard speed. The default value of VECR bit 3 is 1, and the VPP functionality for quad I/O modify operations is disabled. Device core power supply Source voltage. Ground Reference for the VCC supply voltage. Do not use. No connect. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 16Mb, Multiple I/O Serial Flash Memory Organization Memory Organization Memory Configuration and Block Diagram Each page of memory can be individually programmed. Bits are programmed from one through zero. The device is subsector, sector, or bulk-erasable, but not page-erasable. Bits are erased from zero through one. The memory is configured as 2,097,152 bytes 8 bits each 32 sectors 64KB each 512 subsectors 4KB each and 8192 pages 256 bytes each and 64 OTP bytes are located outside the main memory array. See Part Number Ordering Information for complete package names and details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 16Mb, Multiple I/O Serial Flash Memory Package Dimensions Figure 41 DFN-6 x 5mm MAX/ 0 MIN 6 TYP C B M C A B TYP 5 TYP 2x C B Pin one indicator 12° 0 MIN/ MAX TYP C Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 16Mb, Multiple I/O Serial Flash Memory Package Dimensions Figure 42 S08N-150mils MIN/ MAX MAX/ MIN MIN/ MAX 45° MIN/ MAX mm GAUGE PLANE 0o MIN/ 8o MAX MIN/ MAX MIN/ MAX Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. Figure 43 XFCSP-2x2.8mm 16Mb, Multiple I/O Serial Flash Memory Package Dimensions 8X Dimensions apply to solder balls post-reflow. Solder ball material SAC105 Sn, 1% Ag, Cu . 21 A B C D Seating plane A Ball A1 ID All dimensions are in millimeters. Subject to change while final package process completes. See Part Number Ordering Information for complete package names and details. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 16Mb, Multiple I/O Serial Flash Memory Part Number Ordering Information Part Number Ordering Information Table 40 Part Number Information Part Number Category Device type Density Technology Feature set Operating voltage Block structure Package RoHS-compliant Temperature and test flow Security features Shipping material Category Details N25Q = Serial NOR Flash memory, Multiple Input/Output Single, Dual, Quad I/O , XIP 016 = 16Mb A = 65nm 1 = Byte addressability HOLD pin Micron XIP 2 = Byte addressability HOLD pin Basic XIP 3 = Byte addressability RST# pin Micron XIP 4 = Byte addressability RST# pin Basic XIP 1 = VCC = to 2.0V E = Uniform 4KB, 32KB, and 64KB F4 = U-PDFN-8/4mm x 3mm MLP8 F6 = V-PDFN-8/6mm x 5mm MLP8 SC = SOP-8/150 mils SO8N 51 = XF-SCSP-8/2mm x 2.8mm XFCSP 4 = IT to +85°C Device tested with standard test flow A = Automotive temperature range, to +125°C AEC-Q100 grade 1 Device tested with high reliability certified test flow H = Automotive temperature range, to +85°C AEC-Q100 grade 3 Device tested with high reliability certified test flow 0 = Default E = Tray F = Tape and reel G = Tube Notes See the table below for additional information. Additional secure options are available upon customer request. Notes 1 2 Table 41 Package Details Micron SPI and JEDEC Package Name UF-PDFN-8/4mm x 3mm V-PDFN-8/6mm x 5mm SOP-8/150 mils Shortened Package Name DFN/4x3 DFN/6x5 SO8N Package Description Ultra thin, plastic small-outline, 8 terminal pads no leads , 4mm x 3mm Very thin, plastic small-outline, 8 terminal pads no leads , 6mm x 5mm Small-outline integrated circuit, 8 pins, narrow 150 mils M25P and M45PE Symbols N25Q Symbol M25P and M45PE Package Names MLP8, UFDFPN8 F6 MLP8, VDFPN8 SC SO8N, SO8 narrow 150 mils body width Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. 16Mb, Multiple I/O Serial Flash Memory Part Number Ordering Information Table 41 Package Details Continued Micron SPI and JEDEC Package Name Shortened Package Name XF-SCSP-8/2mm x 2.8mm XFCSP Package Description Wafer level, chip-scale package, 8 balls, 2mm x 2.8mm x 0.37mm M25P and M45PE Symbols N25Q Symbol M25P and M45PE Package Names Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved. • Updated part number in main title • Updated Sequence of Bytes During Wrap table in Nonvolatile and Volatile Registers • Updated Part Number Information table in Part Number Ordering Information • Corrected RESET ENABLE and RESET MEMORY command timing diagram • XFCSP package dimension changes • To Production status • Updated tSSE specification in AC Reset Conditions table • Initial release. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel 208-368-4000 Sales inquiries 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.

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16Mb, Multiple I/O Serial Flash Memory Features

Micron Serial NOR Flash Memory
1.8V, Multiple I/O, 4KB Sector Erase N25Q016A11E
• SPI-compatible serial bus interface
• 108 MHz MAX clock frequency
• single supply voltage
• Dual/quad I/O instruction provides increased
throughput up to 432 MB/s
• Supported protocols

Extended SPI, dual I/O, and quad I/O
• Execute-in-place XIP mode for all three protocols

Configurable via volatile or nonvolatile registers Enables memory to work in XIP mode directly af-
ter power-on
• PROGRAM/ERASE SUSPEND operations
• Continuous read of entire memory via a single com-
mand Fast read Quad or dual output fast read Quad or dual I/O fast read
• Flexible to fit application Configurable number of dummy cycles Output buffer configurable
• Software reset
• Hardware RESET function available upon customer request
• 64-byte, user-lockable, one-time programmable OTP dedicated area
• Erase capability Subsector erase 4KB uniform granularity blocks Subsector erase 32KB uniform granularity blocks Sector erase 64KB uniform granularity blocks
• Deep power-down mode 5µA TYP
• Write protection

Software write protection applicable to every 64KB sector via volatile lock bit

Hardware write protection protected area size defined by five nonvolatile bits BP0, BP1, BP2, and TB

Additional smart protections, available upon request
• Electronic signature JEDEC-standard 2-byte signature BB15h Two additional extended device ID EDID bytes to identify device factory options Unique ID code UID 14 read-only bytes
• Minimum 100,000 ERASE cycles per sector
• More than 20 years data retention
• Packages JEDEC standard, all RoHS compliant

F4 = U-PDFN-8/4mm x 3mm MLP8 F6 = V-PDFN-8/6mm x 5mm MLP8 SC = SOP2-8/150 mil SO8N 51 = XF-SCSP-8/2mm x 2.8mm XFCSP

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
16Mb, Multiple I/O Serial Flash Memory Features

Contents

Device Description 6 Features 6 3-Byte Address Modes 6 Operating Protocols 6 XIP Mode 6 Device Configurability 7

Signal Assignments 8 Signal Descriptions 9 Memory Organization 11

Memory Configuration and Block Diagram 11 Memory Map 12 Device Protection 13 Serial Peripheral Interface Modes 15 SPI Protocols 17 Nonvolatile and Volatile Registers 18 Status Register 19 Nonvolatile and Volatile Configuration Registers 20 Enhanced Volatile Configuration Register 23 Flag Status Register 24 Command Definitions 25 READ REGISTER and WRITE REGISTER Operations 27 READ STATUS REGISTER or FLAG STATUS REGISTER Command 27 READ NONVOLATILE CONFIGURATION REGISTER Command 28 READ VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command 28 WRITE STATUS REGISTER Command 28 WRITE NONVOLATILE CONFIGURATION REGISTER Command 29 WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command 29 READ LOCK REGISTER Command 30 WRITE LOCK REGISTER Command 31 CLEAR FLAG STATUS REGISTER Command 32 READ IDENTIFICATION Operations 33 READ ID and MULTIPLE I/O READ ID Commands 33 READ SERIAL FLASH DISCOVERY PARAMETER Command 34 READ MEMORY Operations 38 PROGRAM Operations 42 WRITE Operations 47 WRITE ENABLE Command 47 WRITE DISABLE Command 47 ERASE Operations 49 SUBSECTOR ERASE Command 49 SECTOR ERASE Command 49 BULK ERASE Command 50 PROGRAM/ERASE SUSPEND Command 51 PROGRAM/ERASE RESUME Command 53 RESET Operations 54 RESET ENABLE and RESET MEMORY Command 54 RESET Conditions 54 ONE TIME PROGRAMMABLE Operations 55 READ OTP ARRAY Command 55 PROGRAM OTP ARRAY Command 55

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.
16Mb, Multiple I/O Serial Flash Memory Features

XIP Mode 57 Activate or Terminate XIP Using Volatile Configuration Register 57 Activate or Terminate XIP Using Nonvolatile Configuration Register 57 Confirmation Bit Settings Required to Activate or Terminate XIP 58 Terminating XIP After a Controller and Memory Reset 58

Power Up and Power Down 60 Power Up and Power Down Requirements 60 Power Loss Recovery Sequence 61
Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.
16Mb, Multiple I/O Serial Flash Memory Features

List of Figures

Figure 1 Logic Diagram 7 Figure 2 SO8N, MLP8 TSOP Top View 8 Figure 3 8-Balls, XFCSP, 2mm x 2.8mm x 0.37mm Top View 8 Figure 4 Block Diagram 11 Figure 5 Bus Master and Memory Devices on the SPI Bus 16 Figure 6 SPI Modes 16 Figure 7 Internal Configuration Register 18 Figure 8 READ REGISTER Command 27 Figure 9 WRITE REGISTER Command 29 Figure 10 READ LOCK REGISTER Command 31 Figure 11 WRITE LOCK REGISTER Command 32 Figure 12 READ ID and MULTIPLE I/O Read ID Commands 34 Figure 13 READ Command 39 Figure 14 FAST READ Command 39 Figure 15 DUAL OUTPUT FAST READ 40 Figure 16 DUAL INPUT/OUTPUT FAST READ Command 40 Figure 17 QUAD OUTPUT FAST READ Command 41 Figure 18 QUAD INPUT/OUTPUT FAST READ Command 41 Figure 19 PAGE PROGRAM Command 43 Figure 20 DUAL INPUT FAST PROGRAM Command 44 Figure 21 EXTENDED DUAL INPUT FAST PROGRAM Command 44 Figure 22 QUAD INPUT FAST PROGRAM Command 45 Figure 23 EXTENDED QUAD INPUT FAST PROGRAM Command 46 Figure 24 WRITE ENABLE and WRITE DISABLE Command Sequence 48 Figure 25 SUBSECTOR and SECTOR ERASE Command 50 Figure 26 BULK ERASE Command 51 Figure 27 RESET ENABLE and RESET MEMORY Command 54 Figure 28 READ OTP Command 55 Figure 29 PROGRAM OTP Command 56 Figure 30 XIP Mode Directly After Power-On 58 Figure 31 Power-Up Timing 60 Figure 32 Reset AC Timing During PROGRAM or ERASE Cycle 63 Figure 33 Reset Enable 63 Figure 34 Serial Input Timing 63 Figure 35 Write Protect Setup and Hold During WRITE STATUS REGISTER Operation SRWD = 1 64 Figure 36 Hold Timing 64 Figure 37 Output Timing 65 Figure 38 VPPH Timing 65 Figure 39 AC Timing Input/Output Reference Levels 67 Figure 40 UFDFPN8-4x3 mm 71 Figure 41 DFN-6 x 5mm 72 Figure 42 S08N-150mils 73 Figure 43 XFCSP-2x2.8mm 74

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.
16Mb, Multiple I/O Serial Flash Memory Features

List of Tables

Table 1 Signal Descriptions 9 Table 2 Sectors 31 0 12 Table 3 Data Protection using Device Protocols 13 Table 4 Memory Sector Protection Truth Table 13 Table 5 Protected Area Sizes Upper Area 14 Table 6 Protected Area Sizes Lower Area 14 Table 7 SPI Modes 15 Table 8 Extended, Dual, and Quad SPI Protocols 17 Table 9 Status Register Bit Definitions 19 Table 10 Nonvolatile Configuration Register Bit Definitions 20 Table 11 Volatile Configuration Register Bit Definitions 21 Table 12 Sequence of Bytes During Wrap 22 Table 13 Supported Clock Frequencies 22 Table 14 Enhanced Volatile Configuration Register Bit Definitions 23 Table 15 Flag Status Register Bit Definitions 24 Table 16 Command Set 25 Table 17 Lock Register 30 Table 18 Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands 33 Table 19 Read ID Data Out 33 Table 20 Extended Device ID, First Byte 33 Table 21 Serial Flash Discovery Parameter Data Structure 35 Table 22 Parameter ID 36 Table 23 Command/Address/Data Lines for READ MEMORY Commands 38 Table 24 Data/Address Lines for PROGRAM Commands 42 Table 25 Suspend Parameters 52 Table 26 Operations Allowed/Disallowed During Device States 52 Table 27 Reset Command Set 54 Table 28 OTP Control Byte 64 56 Table 29 XIP Confirmation Bit 58 Table 30 Effects of Running XIP in Different Protocols 58 Table 31 Power-Up Timing and VWI Threshold 61 Table 32 AC RESET Conditions 62 Table 33 Absolute Ratings 66 Table 34 Operating Conditions 66 Table 35 Input/Output Capacitance 66 Table 36 AC Timing Input/Output Conditions 67 Table 37 DC Current Characteristics and Operating Conditions 68 Table 38 DC Voltage Characteristics and Operating Conditions 68 Table 39 AC Characteristics and Operating Conditions 69 Table 40 Part Number Information 75 Table 41 Package Details 75

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.
16Mb, Multiple I/O Serial Flash Memory Device Description

Device Description

The N25Q is the first high-performance multiple input/output serial Flash memory device manufactured on 65nm NOR technology. It features execute-in-place XIP functionality, advanced write protection mechanisms, and a high-speed SPI-compatible bus interface. The innovative, high-performance, dual and quad input/output instructions enable double or quadruple the transfer bandwidth for READ and PROGRAM operations.

The memory is organized as 32 64KB main sectors that are divided into two subsectors each 32KB , that are further divided into eight 4KB subsectors each, 512 4KB subsectors in total. The memory can be erased one 4KB subsector at a time, one 32KB subsector at a time, one 64KB sector at a time, or as a whole.

The memory can be write protected by software through volatile and nonvolatile protection features, depending on the application needs. The protection granularity is of 64KB sector granularity for volatile protections

The device has 64 one-time programmable OTP bytes that can be read and programmed with the READ OTP and PROGRAM OTP commands. These 64 bytes can also be permanently locked with a PROGRAM OTP command.

The device also has the ability to pause and resume PROGRAM and ERASE cycles by using dedicated PROGRAM/ERASE SUSPEND and RESUME instructions.
3-Byte Address Modes

The device features 3-byte address modes to access the memory.

Operating Protocols

The memory can be operated with three different protocols:
• Extended SPI standard SPI protocol upgraded with dual and quad operations
• Dual I/O SPI
• Quad I/O SPI

The standard SPI protocol is extended and enhanced by dual and quad operations. In addition, the dual SPI and quad SPI protocols improve the data access time and throughput of a single I/O device by transmitting commands, addresses, and data across two or four data lines.

XIP Mode

XIP mode requires only an address no instruction to output data, improving random access time and eliminating the need to shadow code onto RAM for fast execution.

All protocols support XIP operation. For flexibility, multiple XIP entry and exit methods are available. For applications that must enter XIP mode immediately after powering up, XIP mode can be set as the default mode through the nonvolatile configuration register bits.

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16Mb, Multiple I/O Serial Flash Memory Device Description

Device Configurability

The N25Q family offers additional features that are configured through the nonvolatile configuration register for default and/or nonvolatile settings. Volatile settings can be configured through the volatile and volatile-enhanced configuration registers. These configurable features include the following:
• Number of dummy cycles for the fast READ commands
• Output buffer impedance
• SPI protocol types extended SPI, DIO-SPI, or QIO-SPI
• Required XIP mode
• Enabling/disabling HOLD RESET function
• Enabling/disabling wrap mode

Figure 1 Logic Diagram

DQ0 C S#

VPP/W#/DQ2 HOLD#/DQ3

VSS Note Reset functionality is available in devices with a dedicated part number. See Part Num-
ber Ordering Information for more details.

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Signal Assignments
16Mb, Multiple I/O Serial Flash Memory Signal Assignments

Figure 2 SO8N, MLP8 TSOP Top View

DQ1 2

W#/VPP/DQ2 3 VSS 4
8 VCC 7 HOLD#/DQ3
5 DQ0
Note Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for complete package names and details.

Figure 3 8-Balls, XFCSP, 2mm x 2.8mm x 0.37mm Top View

B HOLD#/DQ3

W#/VPP/DQ2 VSS
Note Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for complete package names and details.

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16Mb, Multiple I/O Serial Flash Memory Signal Descriptions

Signal Descriptions

The signal description table below is a comprehensive list of signals for the N25Q family devices. All signals listed may not be supported on this device. See Signal Assignments for information specific to this device.

Table 1 Signal Descriptions

Symbol C S#

DQ2 DQ3 RESET#

Type Input

Input and I/O

Output and I/O

Input and I/O

Input and I/O Control Input

Clock Provides the timing of the serial interface. Commands, addresses, or data present at serial data inputs are latched on the rising edge of the clock. Data is shifted out on the falling edge of the clock.

Chip select When S# is HIGH, the device is deselected and DQ1 is at High-Z. When in extended SPI mode, with the device deselected, DQ1 is tri-stated. Unless an internal PROGRAM, ERASE, or WRITE STATUS REGISTER cycle is in progress, the device enters standby power mode not deep power-down mode . Driving S# LOW enables the device, placing it in the active power mode. After power-up, a falling edge on S# is required prior to the start of any command.

Serial data Transfers data serially into the device. It receives command codes, addresses, and the data to be programmed. Values are latched on the rising edge of the clock. DQ0 is used for input/output during the following operations DUAL OUTPUT FAST READ, QUAD OUTPUT FAST READ, DUAL INPUT/OUTPUT FAST READ, and QUAD INPUT/OUTPUT FAST READ. When used for output, data is shifted out on the falling edge of the clock. In DIO-SPI, DQ0 always acts as an input/output. In QIO-SPI, DQ0 always acts as an input/output, with the exception of the PROGRAM or ERASE cycle performed with VPP. The device temporarily enters the extended SPI protocol and then returns to QIO-SPI as soon as VPP goes LOW.

Serial data:Transfers data serially out of the device. Data is shifted out on the falling edge of the clock. DQ1 is used for input/output during the following operations DUAL INPUT FAST PROGRAM, QUAD INPUT FAST PROGRAM, DUAL INPUT EXTENDED FAST PROGRAM, and QUAD INPUT EXTENDED FAST PROGRAM. When used for input, data is latched on the rising edge of the clock. In DIO-SPI, DQ1 always acts as an input/output. In QIO-SPI, DQ1 always acts as an input/output, with the exception of the PROGRAM or ERASE cycle performed with the enhanced program supply voltage VPP . In this case the device temporarily enters the extended SPI protocol and then returns to QIO-SPI as soon as VPP goes LOW.

DQ2 When in QIO-SPI mode or in extended SPI mode using QUAD FAST READ commands, the signal functions as DQ2, providing input/output. All data input drivers are always enabled except when used as an output. Micron recommends customers drive the data signals normally to avoid unnecessary switching current and float the signals before the memory device drives data on them.

DQ3 When in quad SPI mode or in extended SPI mode using quad FAST READ commands, the signal functions as DQ3, providing input/output. HOLD# is disabled and RESET# is disabled if the device is selected.

RESET This is a hardware RESET# signal. When RESET# is driven HIGH, the memory is in the normal operating mode. When RESET# is driven LOW, the memory enters reset mode and output is High-Z. If RESET# is driven LOW while an internal WRITE, PROGRAM, or ERASE operation is in progress, data may be lost.

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16Mb, Multiple I/O Serial Flash Memory Signal Descriptions

Table 1 Signal Descriptions Continued

Symbol HOLD#

VCC VSS DNU NC

Type Control Input

Control Input

Power

Power Ground

HOLD Pauses any serial communications with the device without deselecting the device. DQ1 output is High-Z. DQ0 input and the clock are "Don't Care." To enable HOLD, the device must be selected with S# driven LOW. HOLD# is used for input/output during the following operations QUAD OUTPUT FAST READ, QUAD INPUT/OUTPUT FAST READ, QUAD INPUT FAST PROGRAM, and QUAD INPUT EXTENDED FAST PROGRAM. In QIO-SPI, HOLD# acts as an I/O DQ3 functionality , and the HOLD# functionality is disabled when the device is selected. When the device is deselected S# is HIGH in parts with RESET# functionality, it is possible to reset the device unless this functionality is not disabled by means of dedicated registers bits. The HOLD# functionality can be disabled using bit 4 of the NVCR or bit 4 of the VECR.

Write protect W# can be used as a protection control input or in QIO-SPI operations. When in extended SPI with single or dual commands, the WRITE PROTECT function is selectable by the voltage range applied to the signal. If voltage range is low 0V to VCC , the signal acts as a write protection control input. The memory size protected against PROGRAM or ERASE operations is locked as specified in the status register block protect bits W# is used as an input/output DQ2 functionality during QUAD INPUT FAST READ and QUAD INPUT/OUTPUT FAST READ operations and in QIO-SPI.

Supply voltage If VPP is in the voltage range of VPPH, the signal acts as an additional power supply, as defined in the AC Measurement Conditions table. During QIFP, QIEFP, and QIO-SPI PROGRAM/ERASE operations, it is possible to use the additional VPP power supply to speed up internal operations. However, to enable this functionality, it is necessary to set bit 3 of the VECR to In this case, VPP is used as an I/O until the end of the operation. After the last input data is shifted in, the application should apply VPP voltage to VPP within 200ms to speed up the internal operations. If the VPP voltage is not applied within 200ms, the PROGRAM/ERASE operations start at standard speed. The default value of VECR bit 3 is 1, and the VPP functionality for quad I/O modify operations is disabled.

Device core power supply Source voltage.

Ground Reference for the VCC supply voltage.

Do not use.

No connect.

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16Mb, Multiple I/O Serial Flash Memory Organization

Memory Organization

Memory Configuration and Block Diagram

Each page of memory can be individually programmed. Bits are programmed from one through zero. The device is subsector, sector, or bulk-erasable, but not page-erasable. Bits are erased from zero through one. The memory is configured as 2,097,152 bytes 8 bits each 32 sectors 64KB each 512 subsectors 4KB each and 8192 pages 256 bytes each and 64 OTP bytes are located outside the main memory array.
See Part Number Ordering Information for complete package names and details.

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16Mb, Multiple I/O Serial Flash Memory Package Dimensions

Figure 41 DFN-6 x 5mm

MAX/ 0 MIN
6 TYP

C B M C A B

TYP 5 TYP
2x C B

Pin one indicator
12°
0 MIN/ MAX

TYP C
Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details.

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16Mb, Multiple I/O Serial Flash Memory Package Dimensions

Figure 42 S08N-150mils

MIN/ MAX

MAX/ MIN

MIN/ MAX
45°

MIN/ MAX
mm GAUGE PLANE
0o MIN/ 8o MAX

MIN/ MAX

MIN/ MAX
Notes All dimensions are in millimeters. See Part Number Ordering Information for complete package names and details.

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Figure 43 XFCSP-2x2.8mm
16Mb, Multiple I/O Serial Flash Memory Package Dimensions
8X Dimensions apply to solder balls post-reflow. Solder ball material SAC105 Sn, 1% Ag, Cu .
21 A B C D

Seating plane A

Ball A1 ID
All dimensions are in millimeters. Subject to change while final package process completes. See Part Number Ordering Information for complete package names and details.

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16Mb, Multiple I/O Serial Flash Memory Part Number Ordering Information
Part Number Ordering Information

Table 40 Part Number Information

Part Number Category Device type Density Technology Feature set

Operating voltage Block structure Package RoHS-compliant

Temperature and test flow

Security features Shipping material

Category Details

N25Q = Serial NOR Flash memory, Multiple Input/Output Single, Dual, Quad I/O , XIP
016 = 16Mb

A = 65nm
1 = Byte addressability HOLD pin Micron XIP
2 = Byte addressability HOLD pin Basic XIP
3 = Byte addressability RST# pin Micron XIP
4 = Byte addressability RST# pin Basic XIP
1 = VCC = to 2.0V E = Uniform 4KB, 32KB, and 64KB

F4 = U-PDFN-8/4mm x 3mm MLP8 F6 = V-PDFN-8/6mm x 5mm MLP8 SC = SOP-8/150 mils SO8N 51 = XF-SCSP-8/2mm x 2.8mm XFCSP
4 = IT to +85°C Device tested with standard test flow A = Automotive temperature range, to +125°C AEC-Q100 grade 1 Device tested with high reliability certified test flow H = Automotive temperature range, to +85°C AEC-Q100 grade 3 Device tested with high reliability certified test flow
0 = Default

E = Tray F = Tape and reel G = Tube

Notes See the table below for additional information. Additional secure options are available upon customer request.

Notes 1 2

Table 41 Package Details

Micron SPI and JEDEC Package Name UF-PDFN-8/4mm x 3mm

V-PDFN-8/6mm x 5mm

SOP-8/150 mils

Shortened Package Name DFN/4x3

DFN/6x5

SO8N

Package Description

Ultra thin, plastic small-outline, 8 terminal pads no leads , 4mm x 3mm

Very thin, plastic small-outline, 8 terminal pads no leads , 6mm x 5mm

Small-outline integrated circuit, 8 pins, narrow 150 mils

M25P and M45PE Symbols

N25Q Symbol

M25P and M45PE Package Names

MLP8, UFDFPN8

F6 MLP8, VDFPN8

SC SO8N, SO8 narrow
150 mils body width

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16Mb, Multiple I/O Serial Flash Memory Part Number Ordering Information

Table 41 Package Details Continued

Micron SPI and JEDEC Package Name

Shortened Package Name

XF-SCSP-8/2mm x 2.8mm XFCSP

Package Description

Wafer level, chip-scale package, 8 balls, 2mm x 2.8mm x 0.37mm

M25P and M45PE Symbols

N25Q Symbol

M25P and M45PE Package Names

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.
• Updated part number in main title
• Updated Sequence of Bytes During Wrap table in Nonvolatile and Volatile Registers
• Updated Part Number Information table in Part Number Ordering Information
• Corrected RESET ENABLE and RESET MEMORY command timing diagram
• XFCSP package dimension changes
• To Production status
• Updated tSSE specification in AC Reset Conditions table
• Initial release.
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This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2012 Micron Technology, Inc. All rights reserved.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived N25Q016A11EF640FTR Datasheet file may be downloaded here without warranties.

Datasheet ID: N25Q016A11EF640FTR 648533