MT9VDDF3272Y-335G3

MT9VDDF3272Y-335G3 Datasheet

MT9VDDF3272 256MB MT9VDDF6472 512MB

Part	Datasheet
MT9VDDF3272Y-335G3	MT9VDDF3272Y-335G3 (pdf)

Related Parts	Information
MT9VDDF6472G-335D3	MT9VDDF6472G-335D3
MT9VDDF3272G-335G3	MT9VDDF3272G-335G3
MT9VDDF6472G-335F1	MT9VDDF6472G-335F1

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DDR SDRAM REGISTERED DIMM 256MB, 512MB x72, ECC, SR 184-PIN DDR SDRAM RDIMM MT9VDDF3272 256MB MT9VDDF6472 512MB For the latest data sheet, please refer to the Web site: • 184-pin, dual, in-line memory module DIMM • Fast data transfer rates PC1600, PC2100, or PC2700 • Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR SDRAM components • Registered Inputs with one-clock delay • Phase-lock loop PLL clock driver to reduce loading • Supports ECC error detection and correction • 256MB 32 Meg x 72 and 512MB 64 Meg x 72 • VDD = VDDQ = +2.5V • VDDSPD = +2.3V to +3.6V • 2.5V I/O SSTL_2 compatible • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • Internal, pipelined double data rate DDR architecture two data accesses per clock cycle • Bidirectional data strobe DQS transmitted/received with source-synchronous data capture • Differential clock inputs CK and CK# • Four internal device banks for concurrent operation • Programmable burst lengths 2, 4, or 8 • Auto precharge option • Auto Refresh and Self Refresh Modes • 7.8125µs maximum average periodic refresh interval • Serial Presence-Detect SPD with EEPROM • Programmable READ CAS latency • Gold edge contacts OPTIONS • Operating Temperature Range Commercial 0°C TA +70°C Industrial -40°C TA +85°C MARKING none I1 Table 1 Address Table Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing Figure 1 184-Pin DIMM MO-206 Low-Profile 1.125in. 28.58mm 256MB Low-Profile 1.125in. 28.58mm 512MB Very Low-Profile 0.72in. 18.29mm OPTIONS • Package 184-pin DIMM standard 184-pin DIMM lead-free 1 • Memory Clock, Speed, CAS Latency2 6ns 167 MHz , 333 MT/s, CL = 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL = 10ns 100 MHz , 200 MT/s, CL = 2 • PCB Low-Profile 1.125in. 28.58mm Very Low-Profile 0.72in. 18.29mm MARKING -335 -2621 -26A1 -265 -202 NOTE Contact Micron for product availability. CL = CAS READ Latency Registered mode will add one clock cycle to CL. 256MB 8K 4 BA0, BA1 256Mb 32 Meg x 8 1K 1 S0# 512MB 8K 4 BA0, BA1 512Mb 64 Meg x 8 2K A11 1 S0# 2004 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 256MB, 512MB x72, ECC, SR 184-PIN DDR SDRAM RDIMM Table 2 Part Numbers and Timing Parameters MODULE DENSITY CONFIGURATION MODULE MEMORY CLOCK/ The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page 256MB, 512MB x72, ECC, SR 184-PIN DDR SDRAM RDIMM Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or clocks, as shown in Figure 7, CAS Latency Diagram. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency Table, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure 6 Mode Register Definition Diagram BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M14 and M13 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register . M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 Burst Length M3 = 0 Reserved 2 4 8 Reserved M3 = 1 Reserved 2 4 8 Reserved Burst Type Sequential Interleaved M6 M5 M4 000 001 010 011 100 101 110 111 CAS Latency Reserved 2 Reserved M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - -- M6-M0 Valid Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. Table 6 Burst Definition Table BURST LENGTH STARTING COLUMN ADDRESS ORDER OF ACCESSES WITHIN A BURST TYPE = TYPE = SEQUENTIAL INTERLEAVED A1 A0 0-1-2-3 0-1-2-3 1-2-3-0 1-0-3-2 2-3-0-1 2-3-0-1 3-0-1-2 3-2-1-0

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DDR SDRAM REGISTERED DIMM
256MB, 512MB x72, ECC, SR 184-PIN DDR SDRAM RDIMM

MT9VDDF3272 256MB MT9VDDF6472 512MB

For the latest data sheet, please refer to the Web site:
• 184-pin, dual, in-line memory module DIMM
• Fast data transfer rates PC1600, PC2100, or PC2700
• Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR

SDRAM components
• Registered Inputs with one-clock delay
• Phase-lock loop PLL clock driver to reduce loading
• Supports ECC error detection and correction
• 256MB 32 Meg x 72 and 512MB 64 Meg x 72
• VDD = VDDQ = +2.5V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O SSTL_2 compatible
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs center-
aligned with data for WRITEs
• Internal, pipelined double data rate DDR
architecture two data accesses per clock cycle
• Bidirectional data strobe DQS transmitted/received
with source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 7.8125µs maximum average periodic refresh
interval
• Serial Presence-Detect SPD with EEPROM
• Programmable READ CAS latency
• Gold edge contacts

OPTIONS
• Operating Temperature Range Commercial 0°C TA +70°C Industrial -40°C TA +85°C

MARKING
none I1

Table 1 Address Table

Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing

Figure 1 184-Pin DIMM MO-206

Low-Profile 1.125in. 28.58mm 256MB

Low-Profile 1.125in. 28.58mm 512MB

Very Low-Profile 0.72in. 18.29mm

OPTIONS
• Package 184-pin DIMM standard 184-pin DIMM lead-free 1
• Memory Clock, Speed, CAS Latency2 6ns 167 MHz , 333 MT/s, CL = 7.5ns 133 MHz , 266 MT/s, CL = 2
7.5ns 133 MHz , 266 MT/s, CL = 2
7.5ns 133 MHz , 266 MT/s, CL = 10ns 100 MHz , 200 MT/s, CL = 2
• PCB Low-Profile 1.125in. 28.58mm Very Low-Profile 0.72in. 18.29mm

MARKING
-335 -2621 -26A1 -265 -202

NOTE Contact Micron for product availability.

CL = CAS READ Latency Registered mode will add one clock cycle to CL.
256MB
8K 4 BA0, BA1 256Mb 32 Meg x 8 1K
1 S0#
512MB
8K 4 BA0, BA1 512Mb 64 Meg x 8 2K A11
1 S0#
2004 Micron Technology, Inc. All rights reserved.

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
256MB, 512MB x72, ECC, SR 184-PIN DDR SDRAM RDIMM

Table 2 Part Numbers and Timing Parameters

MODULE DENSITY

CONFIGURATION MODULE MEMORY CLOCK/
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page
256MB, 512MB x72, ECC, SR 184-PIN DDR SDRAM RDIMM

Read Latency

The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or clocks, as shown in Figure 7, CAS Latency Diagram.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency Table, indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Figure 6 Mode Register Definition Diagram

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M14 and M13 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register .

M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11

Burst Length

M3 = 0 Reserved
2 4 8 Reserved

M3 = 1 Reserved
2 4 8 Reserved

Burst Type

Sequential

Interleaved

M6 M5 M4 000 001 010 011 100 101 110 111

CAS Latency Reserved 2 Reserved

M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - --

M6-M0 Valid

Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.

Table 6 Burst Definition Table

BURST LENGTH

STARTING COLUMN ADDRESS

ORDER OF ACCESSES WITHIN A BURST

TYPE =

TYPE =

SEQUENTIAL INTERLEAVED

A1 A0
0-1-2-3
0-1-2-3
1-2-3-0
1-0-3-2
2-3-0-1
2-3-0-1
3-0-1-2
3-2-1-0

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Datasheet ID: MT9VDDF3272Y-335G3 648505