MT8VDDT6464AY-335D3

MT8VDDT6464AY-335D3 Datasheet

MT8VDDT1664A 128MB MT8VDDT3264A 256MB MT8VDDT6464A 512MB

Part	Datasheet
MT8VDDT6464AY-335D3	MT8VDDT6464AY-335D3 (pdf)

Related Parts	Information
MT8VDDT3264AG-335G6	MT8VDDT3264AG-335G6
MT8VDDT6464AY-335F3	MT8VDDT6464AY-335F3
MT8VDDT6464AG-335F3	MT8VDDT6464AG-335F3
MT8VDDT3264AY-335G6	MT8VDDT3264AY-335G6
MT8VDDT3264AG-26AG4	MT8VDDT3264AG-26AG4
MT8VDDT3264AG-265GB	MT8VDDT3264AG-265GB
MT8VDDT6464AY-335F4	MT8VDDT6464AY-335F4
MT8VDDT6464AG-335F4	MT8VDDT6464AG-335F4
MT8VDDT6464AG-40BF4	MT8VDDT6464AG-40BF4
MT8VDDT1664AG-335DB	MT8VDDT1664AG-335DB
MT8VDDT3264AG-262G4	MT8VDDT3264AG-262G4

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DDR SDRAM UNBUFFERED DIMM • 184-pin dual in-line memory module DIMM • Fast data transfer rates PC2100 or PC2700 • Utilizes 266 MT/s and 333 MT/s DDR SDRAM components • 128MB 16 Meg x 64 , 256MB 32 Meg x 64 , and 512MB 64 Meg x 64 • VDD = VDDQ = +2.5V • VDDSPD = +2.3V to +3.6V • 2.5V I/O SSTL_2 compatible • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • Internal, pipelined double data rate DDR architecture two data accesses per clock cycle • Bidirectional data strobe DQS transmitted/ received with source-synchronous data capture • Differential clock inputs CK and CK# • Four internal device banks for concurrent operation • Programmable burst lengths 2, 4, or 8 • Auto precharge option • Auto Refresh and Self Refresh Modes • 15.625µs 128MB , 7.8125µs 256MB, 512MB maximum average periodic refresh interval • Serial Presence Detect SPD with EEPROM • Programmable READ CAS latency • Gold edge contacts 128MB, 256MB, 512MB x64, SR 184-PIN DDR SDRAM UDIMM MT8VDDT1664A 128MB MT8VDDT3264A 256MB MT8VDDT6464A 512MB For the latest data sheet, please refer to the Web site: Figure 1 184-Pin DIMM MO-206 Standard 1.25in. 31.75mm Low-Profile 1.15in. 29.21mm OPTIONS MARKING • Package 184-pin DIMM standard 184-pin DIMM lead-free 1 • Memory Clock/Speed, CAS Latency2 6ns 167 MHz , 333 MT/s, CL = 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL = • PCB -335 -2621 -26A1 -265 Standard 1.25in. 31.75mm Low-Profile 1.15in. 29.21mm See page 2 note See page 2 note NOTE Consult Micron for product availability. CL = CAS READ Latency Table 1 Address Table Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing 128MB 4K 4 BA0, BA1 128Mb 16 Meg x 8 1K 1 S0# 256MB 8K 4 BA0, BA1 256Mb 32 Meg x 8 1K 1 S0# 512MB 8K 4 BA0, BA1 512Mb 64 Meg x 8 2K A11 1 S0# 2004 Micron Technology, Inc. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 128MB, 256MB, 512MB x64, SR 184-PIN DDR SDRAM UDIMM Table 2 Part Numbers and Timing Parameters MT8VDDT1664AG-335__ MT8VDDT1664AY-335__ MT8VDDT1664AG-262__ MT8VDDT1664AY-262__ MT8VDDT1664AG-26A__ MT8VDDT1664AY-26A__ MT8VDDT1664AG-265__ MT8VDDT1664AY-265__ MT8VDDT3264AG-335__ MT8VDDT3264AY-335__ MT8VDDT3264AG-262__ MT8VDDT3264AY-262__ MT8VDDT3264AG-26A__ MT8VDDT3264AY-26A__ MT8VDDT3264AG-265__ MT8VDDT3264AY-265__ MT8VDDT6464AG-335__ MT8VDDT6464AY-335__ MT8VDDT6464AG-262__ MT8VDDT6464AY-262__ MT8VDDT6464AG-26A__ MT8VDDT6464AY-26A__ MT8VDDT6464AG-265__ MT8VDDT6464AY-265__ MODULE DENSITY 128MB 256MB 512MB CONFIGURATION The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 5, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by when the burst length is set to two, by when the burst length is set to four, and by when the burst length is set to eight where Ai is the most significant column address bit for a given configuration. See Note 5 of Figure 6, Burst Definition Table, on page The remaining least significant address bit s is are used to select the starting location within the block. The programmed burst length applies to both read and write bursts. Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or clocks, as shown in Figure 6, CAS Latency Diagram, on page If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency CL Table, on page 10, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. 128MB, 256MB, 512MB x64, SR 184-PIN DDR SDRAM UDIMM Figure 5 Mode Register Definition Diagram 128MB Module BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M13 and M12 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register . 256MB and 512MB Modules BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M14 and M13 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register . M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 Burst Length M3 = 0 Reserved 2 4 8 Reserved M3 = 1 Reserved 2 4 8 Reserved Burst Type Sequential Interleaved M6 M5 M4 000 001 010 011 100 101 110 111 CAS Latency Reserved 2 Reserved M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - -- M6-M0 Valid Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology. Inc. Table 6 Burst Definition Table STARTING BURST COLUMN LENGTH ADDRESS ORDER OF ACCESSES WITHIN A BURST TYPE = TYPE = SEQUENTIAL INTERLEAVED A1 A0

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DDR SDRAM

UNBUFFERED DIMM
• 184-pin dual in-line memory module DIMM
• Fast data transfer rates PC2100 or PC2700
• Utilizes 266 MT/s and 333 MT/s DDR SDRAM
components
• 128MB 16 Meg x 64 , 256MB 32 Meg x 64 , and
512MB 64 Meg x 64
• VDD = VDDQ = +2.5V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O SSTL_2 compatible
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs center-
aligned with data for WRITEs
• Internal, pipelined double data rate DDR
architecture two data accesses per clock cycle
• Bidirectional data strobe DQS transmitted/
received with source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 15.625µs 128MB , 7.8125µs 256MB, 512MB maximum average periodic refresh interval
• Serial Presence Detect SPD with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
128MB, 256MB, 512MB x64, SR 184-PIN DDR SDRAM UDIMM

MT8VDDT1664A 128MB MT8VDDT3264A 256MB MT8VDDT6464A 512MB

For the latest data sheet, please refer to the Web site:

Figure 1 184-Pin DIMM MO-206

Standard 1.25in. 31.75mm

Low-Profile 1.15in. 29.21mm

OPTIONS

MARKING
• Package
184-pin DIMM standard 184-pin DIMM lead-free 1
• Memory Clock/Speed, CAS Latency2 6ns 167 MHz , 333 MT/s, CL = 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL =
• PCB
-335 -2621 -26A1 -265

Standard 1.25in. 31.75mm Low-Profile 1.15in. 29.21mm

See page 2 note See page 2 note

NOTE Consult Micron for product availability. CL = CAS READ Latency

Table 1 Address Table

Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing
128MB
4K 4 BA0, BA1 128Mb 16 Meg x 8 1K
1 S0#
256MB
8K 4 BA0, BA1 256Mb 32 Meg x 8 1K
1 S0#
512MB
8K 4 BA0, BA1 512Mb 64 Meg x 8 2K A11
1 S0#
2004 Micron Technology, Inc.

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
128MB, 256MB, 512MB x64, SR 184-PIN DDR SDRAM UDIMM

Table 2 Part Numbers and Timing Parameters

MT8VDDT1664AG-335__ MT8VDDT1664AY-335__ MT8VDDT1664AG-262__ MT8VDDT1664AY-262__ MT8VDDT1664AG-26A__ MT8VDDT1664AY-26A__ MT8VDDT1664AG-265__ MT8VDDT1664AY-265__ MT8VDDT3264AG-335__ MT8VDDT3264AY-335__ MT8VDDT3264AG-262__ MT8VDDT3264AY-262__ MT8VDDT3264AG-26A__ MT8VDDT3264AY-26A__ MT8VDDT3264AG-265__ MT8VDDT3264AY-265__ MT8VDDT6464AG-335__ MT8VDDT6464AY-335__ MT8VDDT6464AG-262__ MT8VDDT6464AY-262__ MT8VDDT6464AG-26A__ MT8VDDT6464AY-26A__ MT8VDDT6464AG-265__ MT8VDDT6464AY-265__

MODULE DENSITY
128MB 256MB 512MB

CONFIGURATION
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page

Burst Length

Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 5, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by when the burst length is set to two, by when the burst length is set to four, and by when the burst length is set to eight where Ai is the most significant column address bit for a given configuration. See Note 5 of Figure 6, Burst Definition Table, on page The remaining least significant address bit s is are used to select the starting location within the block. The programmed burst length applies to both read and write bursts.

Read Latency

The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or clocks, as shown in Figure 6, CAS Latency Diagram, on page

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency CL Table, on page 10, indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.
128MB, 256MB, 512MB x64, SR 184-PIN DDR SDRAM UDIMM

Figure 5 Mode Register Definition Diagram
128MB Module

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M13 and M12 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register .
256MB and 512MB Modules

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M14 and M13 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register .

M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11

Burst Length

M3 = 0 Reserved
2 4 8 Reserved

M3 = 1 Reserved
2 4 8 Reserved

Burst Type

Sequential

Interleaved

M6 M5 M4 000 001 010 011 100 101 110 111

CAS Latency Reserved 2 Reserved

M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - --

M6-M0 Valid

Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology. Inc.

Table 6 Burst Definition Table

STARTING BURST COLUMN LENGTH ADDRESS

ORDER OF ACCESSES WITHIN A BURST

TYPE =

TYPE =

SEQUENTIAL INTERLEAVED

A1 A0

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Datasheet ID: MT8VDDT6464AY-335D3 648491