ADM7001X-AC-R-1

ADM7001X-AC-R-1 Datasheet

ADM7001/X

Part	Datasheet
ADM7001X-AC-R-1	ADM7001X-AC-R-1 (pdf)

Related Parts	Information
ADM7001ACT1	ADM7001ACT1
ADM7001X-AC-T-1	ADM7001X-AC-T-1

PDF Datasheet Preview
ADM7001/X Single Ethernet 10/100M PHY Communications Never stop thinking. Edition 2005-11-25 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Template template_A4_3.0.fm / 3 / 2005-01-17 ADM7001/X Data sheet Table of Contents Table of Contents Table of Contents 4 List of Figures 6 List of Tables 7 Product Overview 8 Overview 8 Package Information 8 Features 8 Block Diagram 10 Interface Description 11 Pin Diagram 11 Pin Description 11 Twisted Pair Interface, 5 Pins 13 Digital Ground/Power, 7 Pins 14 Ground and Power, 5 Pins 15 Clock Input, 2 Pins 16 MII/RMII/GPSI Interface, 16 pins 16 Reset Pin 22 Clock Signals, 6 Pins 22 LED Interface, 4 Pins 24 Regulator Control 25 Function Description 26 10/100M PHY Block 26 100Base-X Module 26 100Base-TX Receiver 26 100Base-TX Transmitter 30 100Base-FX Receiver 30 100Base-FX Transmitter 31 10Base-T Module 31 Operation Modes 31 Manchester Encoder/Decoder 31 Transmit Driver and Receiver 31 Smart Squelch 31 Carrier Sense 32 Collision Detection 32 Jabber Function 33 Link Test Function 33 Automatic Link Polarity Detection 33 Clock Synthesizer 33 Auto Negotiation 33 Auto Negotiation and Speed Configuration 34 MAC Interface 34 Reduced Media Independent Interface RMII 34 Receive Path for 100M 35 Receive Path for 10M 36 Transmit Path for 100M 36 Transmit Path for 10M 38 Media Independent Interface MII 38 Data Sheet ADM7001/X Data sheet Table of Contents Receive Path for MII 39 Transmit Path for MII 41 General Purpose Serial Interface GPSI 41 Receive Path for GPSI 42 Transmit Path for GPSI 42 LED Display 43 Management Register Access 44 Preamble Suppression 44 Reset Operation 44 Power Management 45 Voltage Regulator 46 Registers Description 48 Register Description 49 Electrical Characteristics 74 DC Characterization 74 Absolute Maximum Rating 74 Recommended Operating Conditions 74 DC Characteristics for V Operation 74 AC Characteristics 75 XI/OSCI Crystal/Oscillator Timing In MII Mode 75 RMII Timing 76 REFCLK Input Timing XI in RMII Mode 76 REFCLK Output Timing CLKO50 in RMII Mode 77 RMII Transmit Timing 77 RMII Receive Timing 78 MII Timing 79 RXCLK Clock Timing 79 MII Receive Timing 81 TXCLK Output Timing 82 MII Transmit Timing 82 GPSI Timing 83 GPSI Receive Timing 83 GPSI Transmit Timing 84 Serial Management Interface MDC/MDIO Timing 85 Power On Configuration Timing 86 Packaging 87 Data Sheet List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 ADM7001/X Block Diagram 10 Pin Diagram 11 100Base-X Block Diagram and Data Path 27 10Base-T Block Diagram and Data Path 32 RMII Signal Diagram 35 RMII Reception Without Error 35 RMII Reception with False Carrier 100M Only 36 RMII Reception with Symbol Error 36 10M RMII Receive Diagram 36 100M RMII Transmit Diagram 37 10M RMII Transmit Diagram 38 MII Signal Diagram 39 MII Receive Without Error 39 MII Receive With False Carrier 40 MII Receive With Symbol Error 100M Only 40 MII Transmission 41 MII Transmit with Collision Half Duplex Only 41 GPSI Signal Diagram 42 GPSI Receive Diagram 42 GPSI Transmit Diagram 43 SMII Read Operation 44 SMII Write Operation 45 Medium Detect Power Management Flow Chart 46 Power and Ground Filtering 47 Crystal/Oscillator Timing 75 REFCLK Input Timing 76 REFCLK Output Timing 77 RMII Transmit Timing 78 RMII Receive Timing 78 RXCLK Output Timing 79 MII Receive Timing 81 TXCLK Output Timing 82 MII Transmit Timing 83 GPSI Receive Timing 84 GPSI Transmit Timing 84 Serial Management Interface MDC/MDIO Timing 85 Power On Configuration Timing 86 ADM7001/X,Low Profile Quad Flat Package LQFP 87 1 contact Infineon for the updated ordering information Package LQFP-48-1 Ordering Number Q67801H 2A1 Main features: • IEEE compatible 10Base-T and 100Base-T physical layer interface and ANSI X3.263 TP-PMD compatible transceiver. • Single chip, integrated physical layer and transceivers for 10Base-T and 100BASE-TX function. • Medium Independent Interface MII , Reduced MII RMII and General Purpose Serial Interface GPSI for high port count switch. • Built-in 10 Mbit transmit filter. • 10 Mbit PLL, exceeding tolerances for both preamble and data jitter. • 100 Mbit PLL, combined with the digital adaptive equalizer and performance up to 120 meters for UTP • 125 MHz Clock Generator and Timing Recovery. • Integrated Base Line Wander Correction. • Carrier Integrity Monitor function supported. • Supports FEFI when Auto Negotiation disabled. • Supports Auto MDIX function for Plug-and-Play • IEEE 802.3u Clause 28 compliant auto negotiation for full 10 Mbit/s and 100 Mbit/s control. • Supports programmable LED for different Switch Application and Power On LED Self Test. • Supports Cable Length Indication both in MII Register and LED Programmable • Supports PECL interface for fiber connection. • Supports TP vs. FX Medium Converter function. • Supports Fault Propagation function for medium converter. • Supports 10K Bytes Jumbo Packet with Clock Skew 150 ppm. Data Sheet • Built-in Clock Generator and Power On Reset Signal to save system cost. • 48 LQFP without regulator. • Supports Power saving function. • Supports Parallel LED output. ADM7001/X Data sheet Product Overview Data Sheet Block Diagram ADM7001/X Data sheet Product Overview Figure 1 ADM7001/X Block Diagram Data Sheet Interface Description Pin Diagram ADM7001/X Data sheet Interface Description PHYAD4/RXD0 PYYAD3/RXD1 PHYAD2/RXD2 PHYAD1/RXD3 MDC MDIO RESET_N VCC33IN XI XO TEST1 GNDIK VCCO_25 GNDIK RXDV/CRSDV/DIS_AMDIX RMII_EN/RX_CLK ISOLATE/RXER GNDO VCCIK_25 TXER TXCLK TXEN TXD0 TXD1 ADM7001L/T 48 Pin VCC25OUT CORE TXP TXN GNDPLL VCCPLL_25 TEST0 GNDTR SD/FXEN RXP VCCA_25 PWRDOWN_N ANEN/COLLED DUPFUL/DUPLED SPD100/SPDLED LNKACT PHYAD0/INTR VCCO_2.5 GNDO CRS COL/GPSI TXD3 TXD2 Figure 2 Pin Diagram Pin Description Note For those pins, which have multiple functions, pin name is separated by slash If not specified, all signals are default to digital signals. Please refer to Table 1Pin Type Descriptions' for an explanation of pin abbreviations.

PDF Datasheet Preview

ADM7001/X

Single Ethernet 10/100M PHY

Communications

Never stop thinking.

Edition 2005-11-25

Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Template template_A4_3.0.fm / 3 / 2005-01-17

ADM7001/X Data sheet

Table of Contents

Table of Contents

Table of Contents 4

List of Figures 6

List of Tables 7

Product Overview 8 Overview 8

Package Information 8 Features 8 Block Diagram 10

Interface Description 11 Pin Diagram 11 Pin Description 11

Twisted Pair Interface, 5 Pins 13 Digital Ground/Power, 7 Pins 14 Ground and Power, 5 Pins 15 Clock Input, 2 Pins 16 MII/RMII/GPSI Interface, 16 pins 16 Reset Pin 22 Clock Signals, 6 Pins 22 LED Interface, 4 Pins 24 Regulator Control 25

Function Description 26 10/100M PHY Block 26
100Base-X Module 26 100Base-TX Receiver 26 100Base-TX Transmitter 30 100Base-FX Receiver 30 100Base-FX Transmitter 31 10Base-T Module 31 Operation Modes 31 Manchester Encoder/Decoder 31 Transmit Driver and Receiver 31 Smart Squelch 31 Carrier Sense 32 Collision Detection 32 Jabber Function 33 Link Test Function 33 Automatic Link Polarity Detection 33 Clock Synthesizer 33 Auto Negotiation 33 Auto Negotiation and Speed Configuration 34 MAC Interface 34 Reduced Media Independent Interface RMII 34 Receive Path for 100M 35 Receive Path for 10M 36 Transmit Path for 100M 36 Transmit Path for 10M 38 Media Independent Interface MII 38

Data Sheet

ADM7001/X Data sheet

Table of Contents

Receive Path for MII 39 Transmit Path for MII 41 General Purpose Serial Interface GPSI 41 Receive Path for GPSI 42 Transmit Path for GPSI 42 LED Display 43 Management Register Access 44 Preamble Suppression 44 Reset Operation 44 Power Management 45 Voltage Regulator 46

Registers Description 48

Register Description 49

Electrical Characteristics 74 DC Characterization 74

Absolute Maximum Rating 74 Recommended Operating Conditions 74

DC Characteristics for V Operation 74 AC Characteristics 75

XI/OSCI Crystal/Oscillator Timing In MII Mode 75 RMII Timing 76

REFCLK Input Timing XI in RMII Mode 76 REFCLK Output Timing CLKO50 in RMII Mode 77 RMII Transmit Timing 77 RMII Receive Timing 78 MII Timing 79 RXCLK Clock Timing 79 MII Receive Timing 81 TXCLK Output Timing 82 MII Transmit Timing 82 GPSI Timing 83 GPSI Receive Timing 83 GPSI Transmit Timing 84 Serial Management Interface MDC/MDIO Timing 85 Power On Configuration Timing 86

Packaging 87

Data Sheet

List of Figures

Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38

ADM7001/X Block Diagram 10 Pin Diagram 11 100Base-X Block Diagram and Data Path 27 10Base-T Block Diagram and Data Path 32 RMII Signal Diagram 35 RMII Reception Without Error 35 RMII Reception with False Carrier 100M Only 36 RMII Reception with Symbol Error 36 10M RMII Receive Diagram 36 100M RMII Transmit Diagram 37 10M RMII Transmit Diagram 38 MII Signal Diagram 39 MII Receive Without Error 39 MII Receive With False Carrier 40 MII Receive With Symbol Error 100M Only 40 MII Transmission 41 MII Transmit with Collision Half Duplex Only 41 GPSI Signal Diagram 42 GPSI Receive Diagram 42 GPSI Transmit Diagram 43 SMII Read Operation 44 SMII Write Operation 45 Medium Detect Power Management Flow Chart 46 Power and Ground Filtering 47 Crystal/Oscillator Timing 75 REFCLK Input Timing 76 REFCLK Output Timing 77 RMII Transmit Timing 78 RMII Receive Timing 78 RXCLK Output Timing 79 MII Receive Timing 81 TXCLK Output Timing 82 MII Transmit Timing 83 GPSI Receive Timing 84 GPSI Transmit Timing 84 Serial Management Interface MDC/MDIO Timing 85 Power On Configuration Timing 86 ADM7001/X,Low Profile Quad Flat Package LQFP 87
1 contact Infineon for the updated ordering information

Package LQFP-48-1
Ordering Number Q67801H 2A1

Main features:
• IEEE compatible 10Base-T and 100Base-T physical layer interface and ANSI X3.263 TP-PMD compatible transceiver.
• Single chip, integrated physical layer and transceivers for 10Base-T and 100BASE-TX function.
• Medium Independent Interface MII , Reduced MII RMII and General Purpose Serial Interface GPSI for high
port count switch.
• Built-in 10 Mbit transmit filter.
• 10 Mbit PLL, exceeding tolerances for both preamble and data jitter.
• 100 Mbit PLL, combined with the digital adaptive equalizer and performance up to 120 meters for UTP
• 125 MHz Clock Generator and Timing Recovery.
• Integrated Base Line Wander Correction.
• Carrier Integrity Monitor function supported.
• Supports FEFI when Auto Negotiation disabled.
• Supports Auto MDIX function for Plug-and-Play
• IEEE 802.3u Clause 28 compliant auto negotiation for full 10 Mbit/s and 100 Mbit/s control.
• Supports programmable LED for different Switch Application and Power On LED Self Test.
• Supports Cable Length Indication both in MII Register and LED Programmable
• Supports PECL interface for fiber connection.
• Supports TP vs. FX Medium Converter function.
• Supports Fault Propagation function for medium converter.
• Supports 10K Bytes Jumbo Packet with Clock Skew 150 ppm.

Data Sheet
• Built-in Clock Generator and Power On Reset Signal to save system cost.
• 48 LQFP without regulator.
• Supports Power saving function.
• Supports Parallel LED output.

ADM7001/X Data sheet

Product Overview

Data Sheet

Block Diagram

ADM7001/X Data sheet

Product Overview

Figure 1 ADM7001/X Block Diagram

Data Sheet

Interface Description

Pin Diagram

ADM7001/X Data sheet

Interface Description

PHYAD4/RXD0 PYYAD3/RXD1 PHYAD2/RXD2 PHYAD1/RXD3

MDC MDIO RESET_N VCC33IN XI XO TEST1 GNDIK

VCCO_25 GNDIK

RXDV/CRSDV/DIS_AMDIX

RMII_EN/RX_CLK

ISOLATE/RXER GNDO

VCCIK_25 TXER

TXCLK

TXEN

TXD0

TXD1

ADM7001L/T 48 Pin

VCC25OUT CORE TXP TXN

GNDPLL

VCCPLL_25

TEST0

GNDTR SD/FXEN RXP

VCCA_25

PWRDOWN_N ANEN/COLLED DUPFUL/DUPLED SPD100/SPDLED LNKACT PHYAD0/INTR VCCO_2.5 GNDO CRS COL/GPSI TXD3 TXD2

Figure 2 Pin Diagram

Pin Description

Note For those pins, which have multiple functions, pin name is separated by slash If not specified, all signals are default to digital signals. Please refer to Table 1Pin Type Descriptions' for an explanation of pin abbreviations.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ADM7001X-AC-R-1 Datasheet file may be downloaded here without warranties.

Datasheet ID: ADM7001X-AC-R-1 637593