MT8VDDT3264HG-335G3

MT8VDDT3264HG-335G3 Datasheet

MT8VDDT1664H 128MB MT8VDDT3264H 256MB MT8VDDT6464H 512MB

Part	Datasheet
MT8VDDT3264HG-335G3	MT8VDDT3264HG-335G3 (pdf)

Related Parts	Information
MT8VDDT6464HG-335D1	MT8VDDT6464HG-335D1
MT8VDDT3264HY-335G3	MT8VDDT3264HY-335G3
MT8VDDT1664HG-265B2	MT8VDDT1664HG-265B2
MT8VDDT1664HG-335B2	MT8VDDT1664HG-335B2
MT8VDDT1664HG-26AB2	MT8VDDT1664HG-26AB2

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128MB, 256MB, 512MB x64, SR 200-PIN DDR SODIMM DDR SDRAM SMALLOUTLINE DIMM MT8VDDT1664H 128MB MT8VDDT3264H 256MB MT8VDDT6464H 512MB For the latest data sheet, please refer to the Web site: • 200-pin, small-outline, dual in-line memory module SODIMM • Fast data transfer rates PC2100 or PC2700 • Utilizes 266 MT/s and 333 MT/s DDR SDRAM components • 128MB 16 Meg x 64 , 256MB 32 Meg x 64 , or 512MB 64 Meg x 64 • VDD = VDDQ = +2.5V • VDDSPD = +2.3V to +3.6V • 2.5V I/O SSTL_2 compatible • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • Internal, pipelined double data rate DDR architecture two data accesses per clock cycle • Bidirectional data strobe DQS transmitted/received with source-synchronous data capture • Differential clock inputs CK and CK# • Four internal device banks for concurrent operation • Programmable burst lengths 2, 4, or 8 • Auto precharge option • Serial Presence Detect SPD with EEPROM • Programmable READ CAS latency • Auto Refresh and Self Refresh Modes • 15.625µs 128MB , 7.8125µs 256MB, 512MB maximum average periodic refresh interval • Gold edge contacts Figure 1 200-Pin SODIMM MO-224 1.25in. 31.75mm OPTIONS • Package 200-pin SODIMM standard 200-pin SODIMM lead-free 1 • Memory Clock, Speed, CAS Latency2 6ns 166 MHz , 333 MT/s, CL = 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL = • PCB 1.25in. 31.75mm MARKING -335 -2621 -26A1 -265 NOTE Contact Micron for product availability. CL = CAS READ Latency Table 1 Address Table Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing 128MB 4K 4 BA0, BA1 128Mb 16 Meg x 8 1K 1 S0# 256MB 8K 4 BA0, BA1 256Mb 32 Meg x 8 1K 1 S0# 512MB 8K 4 BA0, BA1 512Mb 64 Meg x 8 2K A11 1 S0# 2004 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 128MB, 256MB, 512MB x64, SR 200-PIN DDR SODIMM Table 2 Part Numbers and Timing Parameters MODULE CONFIGURATION MODULE MEMORY CLOCK/ LATENCY DENSITY The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Figure 6, Burst Definition Table, on page Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or clocks, as shown in Figure 5, CAS Latency Diagram. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency CL Table, on page 9, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. 128MB, 256MB, 512MB x64, SR 200-PIN DDR SODIMM Figure 4 Mode Register Definition Diagram 128MB Module Address Bus BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M13 and M12 BA1and BA0 must be “0, 0” to select the base mode register vs. the extended mode register . 256MB, 512MB Module Address Bus BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M14 and M13 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register . M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 Burst Length M3 = 0 Reserved 2 4 8 Reserved M3 = 1 Reserved 2 4 8 Reserved Burst Type Sequential Interleaved M6 M5 M4 000 001 010 011 100 101 110 111 CAS Latency Reserved 2 Reserved M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - -- M6-M0 Valid Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. Table 6 Burst Definition Table STARTING BURST COLUMN LENGTH ADDRESS ORDER OF ACCESSES WITHIN A BURST TYPE = TYPE = SEQUENTIAL INTERLEAVED A1 A0 0-1-2-3 0-1-2-3 1-2-3-0 1-0-3-2

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128MB, 256MB, 512MB x64, SR 200-PIN DDR SODIMM

DDR SDRAM SMALLOUTLINE DIMM

MT8VDDT1664H 128MB MT8VDDT3264H 256MB MT8VDDT6464H 512MB

For the latest data sheet, please refer to the Web
site:
• 200-pin, small-outline, dual in-line memory module SODIMM
• Fast data transfer rates PC2100 or PC2700
• Utilizes 266 MT/s and 333 MT/s DDR SDRAM
components
• 128MB 16 Meg x 64 , 256MB 32 Meg x 64 , or
512MB 64 Meg x 64
• VDD = VDDQ = +2.5V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O SSTL_2 compatible
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs center-
aligned with data for WRITEs
• Internal, pipelined double data rate DDR
architecture two data accesses per clock cycle
• Bidirectional data strobe DQS transmitted/received
with source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths 2, 4, or 8
• Auto precharge option
• Serial Presence Detect SPD with EEPROM
• Programmable READ CAS latency
• Auto Refresh and Self Refresh Modes
• 15.625µs 128MB , 7.8125µs 256MB, 512MB
maximum average periodic refresh interval
• Gold edge contacts

Figure 1 200-Pin SODIMM MO-224
1.25in. 31.75mm

OPTIONS
• Package 200-pin SODIMM standard 200-pin SODIMM lead-free 1
• Memory Clock, Speed, CAS Latency2 6ns 166 MHz , 333 MT/s, CL = 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL =
• PCB 1.25in. 31.75mm

MARKING
-335 -2621 -26A1 -265

NOTE Contact Micron for product availability. CL = CAS READ Latency

Table 1 Address Table

Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing
128MB
4K 4 BA0, BA1 128Mb 16 Meg x 8 1K
1 S0#
256MB
8K 4 BA0, BA1 256Mb 32 Meg x 8 1K
1 S0#
512MB
8K 4 BA0, BA1 512Mb 64 Meg x 8 2K A11
1 S0#
2004 Micron Technology, Inc. All rights reserved.

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
128MB, 256MB, 512MB x64, SR 200-PIN DDR SODIMM

Table 2 Part Numbers and Timing Parameters

MODULE CONFIGURATION MODULE

MEMORY CLOCK/

LATENCY

DENSITY
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Figure 6, Burst Definition Table, on page

Read Latency

The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or clocks, as shown in Figure 5, CAS Latency Diagram.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency CL Table, on page 9, indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.
128MB, 256MB, 512MB x64, SR 200-PIN DDR SODIMM

Figure 4 Mode Register Definition Diagram
128MB Module Address Bus

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M13 and M12 BA1and BA0 must be “0, 0” to select the base mode register vs. the extended mode register .
256MB, 512MB Module Address Bus

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M14 and M13 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register .

M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11

Burst Length

M3 = 0 Reserved
2 4 8 Reserved

M3 = 1 Reserved
2 4 8 Reserved

Burst Type

Sequential

Interleaved

M6 M5 M4 000 001 010 011 100 101 110 111

CAS Latency Reserved 2 Reserved

M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - --

M6-M0 Valid

Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.

Table 6 Burst Definition Table

STARTING BURST COLUMN LENGTH ADDRESS

ORDER OF ACCESSES WITHIN A BURST

TYPE =

TYPE =

SEQUENTIAL INTERLEAVED

A1 A0
0-1-2-3
0-1-2-3
1-2-3-0
1-0-3-2

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Datasheet ID: MT8VDDT3264HG-335G3 648488