MT4VDDT3232UY-6K1

MT4VDDT3232UY-6K1 Datasheet

MT4VDDT1632U 64MB MT4VDDT3232U 128MB

Part	Datasheet
MT4VDDT3232UY-6K1	MT4VDDT3232UY-6K1 (pdf)

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DDR SDRAM DIMM MODULE • 100-pin, dual in-line memory module DIMM • Fast data transfer rate PC2100 and PC2700 • Utilizes 266 MT/s or 333 MT/s DDR SDRAM components • 64MB 16 Meg x 32 and 128MB 32 Meg x 32 • VDD = VDDQ = +2.5V • 2.5V I/O SSTL_2 compatible • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • Internal, pipelined double data rate DDR architecture two data accesses per clock cycle • Bidirectional data strobe DQS transmitted/ received with source-synchronous data capture • Differential clock inputs CK and CK# • Four internal device banks for concurrent operation • Programmable burst lengths 2, 4, or 8 • Auto precharge option • Serial Presence Detect SPD with EEPROM • Programmable READ CAS latency • Auto Refresh and Self Refresh Modes 15.625µs 64MB , 7.8125µs 128MB maximum average periodic refresh interval 64MB, 128MB x32 100-PIN DDR DIMM MT4VDDT1632U 64MB MT4VDDT3232U 128MB For the latest data sheet, please refer to the Micronâ Web site: Figure 1 100-Pin DIMM MO-161 OPTIONS • Package 100-pin DIMM gold • Frequency/CAS Latency 6ns/167 MHz 333MT/s CL = 7.5ns/133 MHz 266 MT/s CL = MARKING -6 -75 Table 1 Address Table MT4VDDT1632U MT4VDDT3232U Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing 4K 8K 4 BA0, BA1 16 Meg x 8 1K 1 S0# 8K 4 BA0, BA1 32 Meg x 8 1K 1 S0# Table 2 Part Numbers and Timing Parameters MODULE DENSITY CONFIGURATION MODULE MEMORY CLOCK/ LATENCY BANDWIDTH DATA BIT RATE CL - tRCD - tRP MT4VDDT1632UG-6__ MT4VDDT1632UG-75__ MT4VDDT3232UG-6__ MT4VDDT3232UG-75__ 64MB 128MB 16 Meg x 32 16 Meg x 32 Meg x 32 Meg x 32 GB/s GB/s GB/s GB/s 6ns/333 MT/s 7.5ns/266 MT/s 6ns/333 MT/s 7.5ns/266 MT/s NOTE: Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002, Micron Technology Inc. AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS. ADVANCE 64MB, 128MB x32 100-PIN DDR DIMM Table 3 Pin Assignment 100-Pin DIMM Front Table 4 Pin Assignment 100-Pin DIMM Back PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or clocks, as shown in Figure 5, CAS Latency Diagram, on page If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency CL Table, on page 8, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. ADVANCE 64MB, 128MB x32 100-PIN DDR DIMM Figure 4 Mode Register Definition Diagram 64MB Module Address Bus BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M13 and M12 BA1and BA0 must be “0, 0” to select the base mode register vs. the extended mode register . 128MB Module Address Bus BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M14 and M13 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register . M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 Burst Length M3 = 0 M3 = 1 Reserved Reserved Reserved Reserved Reserved Burst Type Sequential Interleaved M6 M5 M4 000 001 010 011 100 101 110 111 CAS Latency Reserved 2 Reserved M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - -- M6-M0 Valid Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002, Micron Technology Inc. Table 6 Burst Definition Table STARTING BURST COLUMN ORDER OF ACCESSES WITHIN LENGTH ADDRESS A BURST TYPE = TYPE =

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DDR SDRAM

DIMM MODULE
• 100-pin, dual in-line memory module DIMM
• Fast data transfer rate PC2100 and PC2700
• Utilizes 266 MT/s or 333 MT/s DDR SDRAM
components
• 64MB 16 Meg x 32 and 128MB 32 Meg x 32
• VDD = VDDQ = +2.5V
• 2.5V I/O SSTL_2 compatible
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs center-
aligned with data for WRITEs
• Internal, pipelined double data rate DDR
architecture two data accesses per clock cycle
• Bidirectional data strobe DQS transmitted/
received with source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths 2, 4, or 8
• Auto precharge option
• Serial Presence Detect SPD with EEPROM
• Programmable READ CAS latency
• Auto Refresh and Self Refresh Modes 15.625µs 64MB , 7.8125µs 128MB maximum average periodic refresh interval
64MB, 128MB x32 100-PIN DDR DIMM

MT4VDDT1632U 64MB MT4VDDT3232U 128MB

For the latest data sheet, please refer to the Micronâ Web site:

Figure 1 100-Pin DIMM MO-161

OPTIONS
• Package 100-pin DIMM gold
• Frequency/CAS Latency 6ns/167 MHz 333MT/s CL = 7.5ns/133 MHz 266 MT/s CL =

MARKING
-6 -75

Table 1 Address Table

MT4VDDT1632U MT4VDDT3232U

Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing
4K 8K 4 BA0, BA1 16 Meg x 8 1K
1 S0#
8K 4 BA0, BA1 32 Meg x 8 1K
1 S0#

Table 2 Part Numbers and Timing Parameters

MODULE DENSITY

CONFIGURATION MODULE MEMORY CLOCK/

LATENCY

BANDWIDTH DATA BIT RATE CL - tRCD - tRP

MT4VDDT1632UG-6__ MT4VDDT1632UG-75__ MT4VDDT3232UG-6__ MT4VDDT3232UG-75__
64MB 128MB
16 Meg x 32 16 Meg x 32 Meg x 32 Meg x 32

GB/s GB/s GB/s GB/s
6ns/333 MT/s 7.5ns/266 MT/s 6ns/333 MT/s 7.5ns/266 MT/s

NOTE:

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002, Micron Technology Inc.

AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

ADVANCE
64MB, 128MB x32 100-PIN DDR DIMM

Table 3 Pin Assignment 100-Pin DIMM Front

Table 4 Pin Assignment 100-Pin DIMM Back

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page

Read Latency

The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or clocks, as shown in Figure 5, CAS Latency Diagram, on page

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency CL Table, on page 8, indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

ADVANCE
64MB, 128MB x32 100-PIN DDR DIMM

Figure 4 Mode Register Definition Diagram
64MB Module Address Bus

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M13 and M12 BA1and BA0 must be “0, 0” to select the base mode register vs. the extended mode register .
128MB Module Address Bus

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M14 and M13 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register .

M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11

Burst Length

M3 = 0

M3 = 1

Reserved

Reserved

Reserved

Reserved

Reserved

Burst Type

Sequential

Interleaved

M6 M5 M4 000 001 010 011 100 101 110 111

CAS Latency Reserved 2 Reserved

M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - --

M6-M0 Valid

Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002, Micron Technology Inc.

Table 6 Burst Definition Table

STARTING

BURST COLUMN ORDER OF ACCESSES WITHIN

LENGTH ADDRESS

A BURST

TYPE =

TYPE =

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Datasheet ID: MT4VDDT3232UY-6K1 648476