MT47H512M4THN-3:E TR

MT47H512M4THN-3:E TR Datasheet

MT47H512M4 32 Meg x 4 x 8 Banks x 2 Ranks MT47H256M8 16 Meg x 8 x 8 Banks x 2 Ranks

Part	Datasheet
MT47H512M4THN-3:E TR	MT47H512M4THN-3:E TR (pdf)

Related Parts	Information
MT47H512M4THN-37E:E TR	MT47H512M4THN-37E:E TR

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2Gb x4, x8 TwinDie DDR2 SDRAM Functionality TwinDie DDR2 SDRAM MT47H512M4 32 Meg x 4 x 8 Banks x 2 Ranks MT47H256M8 16 Meg x 8 x 8 Banks x 2 Ranks For the latest component data sheet, refer to Micron’s Web site: Functionality The 2Gb TwinDie DDR2 SDRAM uses Micron’s 1Gb DDR2 monolithic die and, therefore, has similar functionality. This TwinDie data sheet is intended to provide a general description, package dimensions, and the ballout only. Refer to the Micron 1Gb DDR2 data sheet for complete information regarding individual die initialization, register definition, command descriptions, and die operation. • Uses 1Gb Micron die • Two ranks includes dual CS#, ODT, and CKE balls • Each rank has 8 internal banks for concurrent operation • VDD = VDDQ = +1.8V ±0.1V • JEDEC-standard 63-ball ballout • Low-profile package size 1.35mm MAX thickness Options • Configuration 32 Meg x 4 x 8 banks x 2 ranks 16 Meg x 8 x 8 banks x 2 ranks • FBGA package lead-free 63-ball FBGA 9mm x 11.5mm • Timing cycle time1 2.5ns CL = 5 DDR2-800 2.5ns CL = 6 DDR2-800 3.0ns CL = 5 DDR2-667 3.75ns CL = 4 DDR2-533 • Self refresh Standard • Operating temperature Commercial 0°C TC 85°C Notes CL = CAS READ latency Marking 512M4 256M8 -25E -25 -3 -37E None None :E, :G Table 1 Key Timing Parameters Speed Data Rate MT/s tRCD Grade CL = 6 CL = 5 CL = 4 CL = 3 -25E -37E tRC ns tRFC ns Table 2 Addressing Parameter Refresh count Row address Bank address Configuration Column address Rank address 256 Meg x 8 8K 16K A[13:0] 8 BA[2:0] 16 Meg x 8 x 8 x 2 1K A[9:0] 2 CS#[1:0] 512 Meg x 4 8K 16K A[13:0]

PDF Datasheet Preview

2Gb x4, x8 TwinDie DDR2 SDRAM Functionality

TwinDie DDR2 SDRAM

MT47H512M4 32 Meg x 4 x 8 Banks x 2 Ranks MT47H256M8 16 Meg x 8 x 8 Banks x 2 Ranks

For the latest component data sheet, refer to Micron’s Web site:

Functionality

The 2Gb TwinDie DDR2 SDRAM uses Micron’s 1Gb DDR2 monolithic die and, therefore, has similar functionality. This TwinDie data sheet is intended to provide a general description, package dimensions, and the ballout only. Refer to the Micron 1Gb DDR2 data sheet for complete information regarding individual die initialization, register definition, command descriptions, and die operation.
• Uses 1Gb Micron die
• Two ranks includes dual CS#, ODT, and CKE balls
• Each rank has 8 internal banks for concurrent
operation
• VDD = VDDQ = +1.8V ±0.1V
• JEDEC-standard 63-ball ballout
• Low-profile package size 1.35mm MAX thickness

Options
• Configuration 32 Meg x 4 x 8 banks x 2 ranks 16 Meg x 8 x 8 banks x 2 ranks
• FBGA package lead-free 63-ball FBGA 9mm x 11.5mm
• Timing cycle time1 2.5ns CL = 5 DDR2-800 2.5ns CL = 6 DDR2-800 3.0ns CL = 5 DDR2-667 3.75ns CL = 4 DDR2-533
• Self refresh Standard
• Operating temperature Commercial 0°C TC 85°C

Notes CL = CAS READ latency

Marking
512M4 256M8
-25E -25 -3 -37E

None

None :E, :G

Table 1 Key Timing Parameters

Speed

Data Rate MT/s
tRCD

Grade

CL = 6

CL = 5

CL = 4

CL = 3
-25E
-37E
tRC ns
tRFC ns

Table 2 Addressing

Parameter Refresh count Row address Bank address Configuration Column address Rank address
256 Meg x 8
8K 16K A[13:0]
8 BA[2:0] 16 Meg x 8 x 8 x 2
1K A[9:0] 2 CS#[1:0]
512 Meg x 4
8K 16K A[13:0]

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Datasheet ID: MT47H512M4THN-3:ETR 648454