MT46V64M16P-6T IT:A

MT46V64M16P-6T IT:A Datasheet

MT46V256M4 64 Meg x 4 x 4 Banks MT46V128M8 32 Meg x 8 x 4 Banks MT46V64M16 16 Meg x 16 x 4 Banks

Part	Datasheet
MT46V64M16P-6T IT:A	MT46V64M16P-6T IT:A (pdf)

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DDR SDRAM MT46V256M4 64 Meg x 4 x 4 Banks MT46V128M8 32 Meg x 8 x 4 Banks MT46V64M16 16 Meg x 16 x 4 Banks 1Gb x4, x8, x16 DDR SDRAM Features • VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V DDR400 • Bidirectional data strobe DQS transmitted/ received with data, that is, source-synchronous data capture x16 has two one per byte • Internal, pipelined double-data-rate DDR architecture two data accesses per clock cycle • Differential clock inputs CK and CK# • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • DLL to align DQ and DQS transitions with CK • Four internal banks for concurrent operation • Data mask DM for masking write data x16 has two one per byte • Programmable burst lengths BL 2, 4, or 8 • Auto refresh and self refresh modes • Longer-lead TSOP for improved reliability OCPL • 2.5V I/O SSTL_2 compatible • Concurrent auto precharge option is supported • tRAS lockout supported tRAP = tRCD Options Marking • Configuration 256 Meg x 4 64 Meg x 4 x 4 banks 128 Meg x 8 32 Meg x 8 x 4 banks 64 Meg x 16 Meg x 16 x 4 banks • Plastic package OCPL 66-pin TSOP 400-mil width, 0.65mm pin pitch 66-pin TSOP Pb-free 400-mil width, 0.65mm pin pitch • Timing cycle time 5.0ns CL = 3 DDR400B 6.0ns CL = DDR333B 2 7.5ns CL = DDR266B 2 • Temperature rating Commercial 0°C to +70°C Industrial to +85°C 256M4 128M8 64M16 -5B1 -6T -75 None IT :A Notes Not recommended for new designs. See Table 3 on page 2 for module compatibility. Table 1: Key Timing Parameters CL = CAS READ latency data-out window is MIN clock rate with 50 percent duty cycle at CL = Speed Grade -5B -6T -75 CL = 2 133 100 Clock Rate MHz CL = 167 133 CL = 3 200 n/a n/a Data-Out Window 1.6ns 2.0ns 2.5ns Access Window ±0.70ns ±0.70ns ±0.75ns Skew +0.40ns +0.45ns +0.50ns Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved. 1Gb x4, x8, x16 DDR SDRAM Features Table 2 Addressing Parameter Configuration Refresh count Row address Bank address Column address 256 Meg x 4 64 Meg x 4 x 4 banks 8K 16K 4 BA0, BA1 4K A11, A12 128 Meg x 8 32 Meg x 8 x 4 banks 8K The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table Table 28 Burst Definition Burst Length 2 4 Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-0-1-2-3 1-0-3-2-3-0-1 3-2-1-0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved. 1Gb x4, x8, x16 DDR SDRAM Operations CAS Latency CL The CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2, or 3 -5B only clocks, as shown in Figure Reserved states should not be used, as unknown operation or incompatibility with future versions may result. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 29 on page 49 indicates the operating frequencies at which each CL setting can be used. Figure 22 CAS Latency CK# CK Command T0 READ T1 NOP CL = 2 CK# CK Command T0 READ DQS DQ NOP CL = CK# CK Command T0 READ T1 NOP T2 NOP CL = 3 Note: Transitioning Data Don’t Care BL = 4 in the cases shown with nominal tAC, tDQSCK, and tDQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved. 1Gb x4, x8, x16 DDR SDRAM Operations Table 29 CAS Latency Speed -5B -6T -75 CL = 2 75 f 133 75 f 133 75 f 100 Allowable Operating Clock Frequency MHz

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DDR SDRAM

MT46V256M4 64 Meg x 4 x 4 Banks MT46V128M8 32 Meg x 8 x 4 Banks MT46V64M16 16 Meg x 16 x 4 Banks
1Gb x4, x8, x16 DDR SDRAM Features
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V DDR400
• Bidirectional data strobe DQS transmitted/ received with data, that is, source-synchronous data capture x16 has two one per byte
• Internal, pipelined double-data-rate DDR architecture two data accesses per clock cycle
• Differential clock inputs CK and CK#
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask DM for masking write data
x16 has two one per byte
• Programmable burst lengths BL 2, 4, or 8
• Auto refresh and self refresh modes
• Longer-lead TSOP for improved reliability OCPL
• 2.5V I/O SSTL_2 compatible
• Concurrent auto precharge option is supported
• tRAS lockout supported tRAP = tRCD

Options

Marking
• Configuration 256 Meg x 4 64 Meg x 4 x 4 banks 128 Meg x 8 32 Meg x 8 x 4 banks 64 Meg x 16 Meg x 16 x 4 banks
• Plastic package OCPL 66-pin TSOP 400-mil width, 0.65mm pin pitch 66-pin TSOP Pb-free 400-mil width, 0.65mm pin pitch
• Timing cycle time 5.0ns CL = 3 DDR400B 6.0ns CL = DDR333B 2 7.5ns CL = DDR266B 2
• Temperature rating Commercial 0°C to +70°C Industrial to +85°C
256M4 128M8 64M16
-5B1 -6T -75

None IT :A

Notes Not recommended for new designs. See Table 3 on page 2 for module compatibility.

Table 1:

Key Timing Parameters CL = CAS READ latency data-out window is MIN clock rate with 50 percent duty cycle at CL =

Speed Grade -5B -6T -75

CL = 2 133 100

Clock Rate MHz

CL = 167 133

CL = 3 200 n/a n/a

Data-Out Window
1.6ns 2.0ns 2.5ns

Access Window
±0.70ns ±0.70ns ±0.75ns

Skew
+0.40ns +0.45ns +0.50ns

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved.
1Gb x4, x8, x16 DDR SDRAM Features

Table 2 Addressing

Parameter Configuration Refresh count Row address Bank address Column address
256 Meg x 4
64 Meg x 4 x 4 banks 8K
16K 4 BA0, BA1 4K A11, A12
128 Meg x 8
32 Meg x 8 x 4 banks 8K
The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table

Table 28 Burst Definition

Burst Length 2 4

Starting Column Address

Order of Accesses Within a Burst

Type = Sequential

Type = Interleaved
0-1-0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
0-1-0-1-2-3 1-0-3-2-3-0-1 3-2-1-0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved.
1Gb x4, x8, x16 DDR SDRAM Operations

CAS Latency CL

The CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2, or 3 -5B only clocks, as shown in Figure Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 29 on page 49 indicates the operating frequencies at which each CL setting can be used.

Figure 22 CAS Latency

CK# CK

Command

T0 READ

T1 NOP

CL = 2

CK# CK

Command

T0 READ

DQS DQ

NOP CL =

CK# CK

Command

T0 READ

T1 NOP

T2 NOP

CL = 3

Note:

Transitioning Data

Don’t Care

BL = 4 in the cases shown with nominal tAC, tDQSCK, and tDQSQ.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved.
1Gb x4, x8, x16 DDR SDRAM Operations

Table 29 CAS Latency

Speed -5B -6T -75

CL = 2 75 f 133 75 f 133 75 f 100

Allowable Operating Clock Frequency MHz

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Datasheet ID: MT46V64M16P-6TIT:A 648444