MT46H8M16LFCF-75 IT

MT46H8M16LFCF-75 IT Datasheet

MT46H8M16LF 2 Meg x 16 x 4 Banks

Part	Datasheet
MT46H8M16LFCF-75 IT	MT46H8M16LFCF-75 IT (pdf)

Related Parts	Information
MT46H8M16LFCF-75	MT46H8M16LFCF-75
MT46H8M16LFCF-10 IT	MT46H8M16LFCF-10 IT
MT46H8M16LFCF-10 TR	MT46H8M16LFCF-10 TR
MT46H8M16LFCF-10	MT46H8M16LFCF-10
MT46H8M16LFCF-10 IT TR	MT46H8M16LFCF-10 IT TR

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128Mb 8 Meg x 16 Mobile DDR SDRAM Features Mobile DDR SDRAM MT46H8M16LF 2 Meg x 16 x 4 Banks For the latest data sheet, refer to Micron’s Web site: • VDD/VDDQ = +1.8V ±0.1V • Bidirectional data strobe per byte of data DQS • Internal, pipelined double data rate DDR architecture two data accesses per clock cycle • Differential clock inputs CK and CK# • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • Four internal banks for concurrent operation • Data masks DM for masking write mask per byte • Programmable burst lengths 2, 4, or 8 • Concurrent auto precharge option is supported • Auto refresh and self refresh modes • 1.8V LVCMOS-compatible inputs • On-chip temperature sensor to control refresh rate • Partial array self refresh PASR • Selectable output drive DS • Clock stop capability Options • VDD/VDDQ • 1.8V/1.8V • Configuration • 8 Meg x 16 2 Meg x 16 x 4 banks • Plastic package • 60-Ball VFBGA lead-free 8mm x 10mm • Timing cycle time • 7.5ns CL = 3 • 10ns CL = 3 • Operating temperature range • Commercial 0° to +70°C • Industrial -40°C to +85°C Marking H 8M16 -75 -10 None IT Figure 1 60-Ball VFBGA Assignment Top View VSS DQ15 VSSQ VDDQ DQ13 DQ14 VSSQ DQ11 DQ12 VDDQ DQ9 DQ10 VSSQ UDQS DQ8 VSS UDM NC A9 A11 NC VDDQ DQ0 VDD DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 TEST1 DQ7 LDQS VDDQ NC LDM VDD WE# CAS# RAS# CS# BA0 BA1 A10/AP A0 Notes:1.D9 should be connected to VSS or VSSQ in normal operations. Table 1 Configuration Addressing Architecture Configuration Refresh count Row addressing Bank addressing Column addressing 8 Meg x 16 2 Meg x 16 x 4 4K 4K 4 BA0, BA1 512K Table 2: Accesses within a given burst may be programmed to be either sequential or interleaved this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address. See Table 5 on page 11 for more information. The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 3 clocks, as shown in Figure 3 on page For CL = 3, if the READ command is registered at clock edge n, then the data will nominally be available at n + 2 clocks + tAC . For CL = 2, if the READ command is registered at clock edge n, then the data will be nominally be available at n + 1 clock + tAC . Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure 3 Standard Mode Register Definition BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus Should be programmed to “0” to ensure compatibility with future devices. M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Operating Mode CAS Latency BT Burst Length Mode Register M13 M12 Mode Register Definintion 0 Base Mode Register 0 1 Reserved 1 0 Extended Mode Register 1 Resereved M11 M10 M9 M8 M7 Valid Operating Mode Normal Operation All other states reserved Burst Length M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 M3 = 0 Reserved 2 4 8 Reserved M3 = 1 Reserved 2 4 8 Reserved M6 M5 M4 000 001 010 011 100 101 110 111 CAS Latency Reserved 2 3 Reserved Burst Type Sequential Interleaved Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. 128Mb 8 Meg x 16 Mobile DDR SDRAM Register Definition Table 5 Burst Definition Burst Length Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-0 0-1-2-3 1-0-3-2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Figure 4: CAS Latency CK# CK

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128Mb 8 Meg x 16 Mobile DDR SDRAM Features

Mobile DDR SDRAM

MT46H8M16LF 2 Meg x 16 x 4 Banks

For the latest data sheet, refer to Micron’s Web site:
• VDD/VDDQ = +1.8V ±0.1V
• Bidirectional data strobe per byte of data DQS
• Internal, pipelined double data rate DDR
architecture two data accesses per clock cycle
• Differential clock inputs CK and CK#
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs center-
aligned with data for WRITEs
• Four internal banks for concurrent operation
• Data masks DM for masking write mask
per byte
• Programmable burst lengths 2, 4, or 8
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs
• On-chip temperature sensor to control refresh rate
• Partial array self refresh PASR
• Selectable output drive DS
• Clock stop capability

Options
• VDD/VDDQ
• 1.8V/1.8V
• Configuration
• 8 Meg x 16 2 Meg x 16 x 4 banks
• Plastic package
• 60-Ball VFBGA lead-free 8mm x 10mm
• Timing cycle time
• 7.5ns CL = 3
• 10ns CL = 3
• Operating temperature range
• Commercial 0° to +70°C
• Industrial -40°C to +85°C

Marking

H 8M16
-75 -10 None IT

Figure 1 60-Ball VFBGA Assignment Top View

VSS DQ15 VSSQ

VDDQ DQ13 DQ14

VSSQ DQ11 DQ12

VDDQ DQ9 DQ10

VSSQ UDQS DQ8

VSS UDM NC

A9 A11 NC

VDDQ DQ0 VDD

DQ1 DQ2 VSSQ

DQ3 DQ4 VDDQ DQ5 DQ6 TEST1

DQ7 LDQS VDDQ

NC LDM VDD

WE# CAS# RAS#

CS# BA0 BA1

A10/AP A0

Notes:1.D9 should be connected to VSS or VSSQ in normal operations.

Table 1 Configuration Addressing

Architecture

Configuration Refresh count Row addressing Bank addressing Column addressing
8 Meg x 16
2 Meg x 16 x 4 4K
4K 4 BA0, BA1 512K

Table 2:
Accesses within a given burst may be programmed to be either sequential or interleaved this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address. See Table 5 on page 11 for more information.

The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 3 clocks, as shown in Figure 3 on page For CL = 3, if the READ command is registered at clock edge n, then the data will nominally be available at n + 2 clocks + tAC . For CL = 2, if the READ command is registered at clock edge n, then the data will be nominally be available at n + 1 clock + tAC . Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Figure 3 Standard Mode Register Definition

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus

Should be programmed to “0” to ensure compatibility with future devices.

M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0
13 12 11 10 9 8 7 6 5 4 3 2 1 0

Operating Mode CAS Latency BT Burst Length

Mode Register

M13 M12 Mode Register Definintion 0 Base Mode Register 0 1 Reserved 1 0 Extended Mode Register 1 Resereved

M11 M10 M9 M8 M7

Valid

Operating Mode Normal Operation All other states reserved

Burst Length

M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11

M3 = 0 Reserved
2 4 8 Reserved

M3 = 1 Reserved
2 4 8 Reserved

M6 M5 M4 000 001 010 011 100 101 110 111

CAS Latency Reserved 2 3 Reserved

Burst Type

Sequential

Interleaved

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.
128Mb 8 Meg x 16 Mobile DDR SDRAM Register Definition

Table 5 Burst Definition

Burst Length

Starting Column Address

Order of Accesses Within a Burst

Type = Sequential

Type = Interleaved
0-1-0
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
0-1-0
0-1-2-3 1-0-3-2-3-0-1 3-2-1-0
0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0

Figure 4:

CAS Latency

CK# CK

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Datasheet ID: MT46H8M16LFCF-75IT 648441