MT46H16M32LFCX-5:B
MT46H16M32LFCX-5:B Datasheet
MT46H32M16LF 8 Meg x 16 x 4 Banks MT46H16M32LF 4 Meg x 32 x 4 Banks
| Part | Datasheet |
|---|---|
MT46H16M32LFCX-5:B |
MT46H16M32LFCX-5:B (pdf) |
| Related Parts | Information |
|---|---|
MT46H16M32LFCM-6 IT TR |
MT46H16M32LFCM-6 IT TR |
MT46H32M16LFCK-6 TR |
MT46H32M16LFCK-6 TR |
MT46H32M16LFCK-6 IT TR |
MT46H32M16LFCK-6 IT TR |
MT46H16M32LFCM-6 TR |
MT46H16M32LFCM-6 TR |
MT46H16M32LFCM-75 IT |
MT46H16M32LFCM-75 IT |
MT46H32M16LFBF-5:B TR |
MT46H32M16LFBF-5:B TR |
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MT46H32M16LFBF-6 IT:B TR |
MT46H32M16LFBF-6 IT:B TR |
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MT46H32M16LFBF-6:B TR |
MT46H32M16LFBF-6:B TR |
MT46H16M32LFCM-5:B TR |
MT46H16M32LFCM-5:B TR |
MT46H16M32LFCM-6:B TR |
MT46H16M32LFCM-6:B TR |
MT46H16M32LFCM-6 IT:B TR |
MT46H16M32LFCM-6 IT:B TR |
MT46H16M32LFCX-6:B TR |
MT46H16M32LFCX-6:B TR |
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MT46H32M16LFBF-5 IT:B TR |
MT46H32M16LFBF-5 IT:B TR |
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MT46H32M16LFBF-6 AT:B |
MT46H32M16LFBF-6 AT:B |
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MT46H32M16LFBF-6 AT:B TR |
MT46H32M16LFBF-6 AT:B TR |
MT46H16M32LFCX-6 IT:B TR |
MT46H16M32LFCX-6 IT:B TR |
MT46H16M32LFCX-5:B TR |
MT46H16M32LFCX-5:B TR |
MT46H16M32LFCX-6 IT:B |
MT46H16M32LFCX-6 IT:B |
MT46H16M32LFCX-6:B |
MT46H16M32LFCX-6:B |
MT46H16M32LFCM-5 IT:B TR |
MT46H16M32LFCM-5 IT:B TR |
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MT46H16M32LFCG-6 IT:B |
MT46H16M32LFCG-6 IT:B |
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MT46H32M16LFBF-5 IT:B |
MT46H32M16LFBF-5 IT:B |
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MT46H16M32LFCG-6 IT:B TR |
MT46H16M32LFCG-6 IT:B TR |
MT46H16M32LFCM-5 IT:B |
MT46H16M32LFCM-5 IT:B |
MT46H16M32LFCM-6 L IT:B |
MT46H16M32LFCM-6 L IT:B |
MT46H16M32LFCM-6 L IT:B TR |
MT46H16M32LFCM-6 L IT:B TR |
MT46H16M32LFCX-5 IT:B |
MT46H16M32LFCX-5 IT:B |
MT46H16M32LFCX-5 IT:B TR |
MT46H16M32LFCX-5 IT:B TR |
| PDF Datasheet Preview |
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| 512Mb x16, x32 Mobile LPDDR SDRAM Features Mobile Low-Power DDR SDRAM MT46H32M16LF 8 Meg x 16 x 4 Banks MT46H16M32LF 4 Meg x 32 x 4 Banks • VDD/VDDQ = • 1.2V I/O option VDDQ = • Bidirectional data strobe per byte of data DQS • Internal, pipelined double data rate DDR architec- ture two data accesses per clock cycle • Differential clock inputs CK and CK# • Commands entered on each positive CK edge • DQS edge-aligned with data for READs;center- aligned with data for WRITEs • 4 internal banks for concurrent operation • Data masks DM for masking write mask per byte • Programmable burst lengths BL 2, 4, 8, or 16 • Concurrent auto precharge option is supported • Auto refresh and self refresh modes • 1.8V LVCMOS-compatible inputs • On-chip temp sensor to control self refresh rate • Partial-array self refresh PASR • Deep power-down DPD • Status read register SRR • Selectable output drive strength DS • Clock stop capability • 64ms refresh Table 1 Key Timing Parameters CL = 3 Speed Grade -5 -54 -6 -75 Clock Rate MHz 200 185 166 133 Access Time 5.0ns 5.0ns 5.0ns 6.0ns Options Marking • VDD/VDDQ 1.8V/1.8V 1.8V/1.2V1 • Configuration 32 Meg x 16 8 Meg x 16 x 4 banks 16 Meg x 32 4 Meg x 32 x 4 banks • Row-size option JEDEC-standard option Reduced page-size option1 • Plastic green package 60-ball VFBGA 8mm x 9mm 2 90-ball VFBGA 10mm x 13mm 3 90-ball VFBGA 9mm x 13mm 3 • Timing cycle time 5ns CL = 3 5.4ns CL = 3 6ns CL = 3 7.5ns CL = 3 • Power Standard IDD2/IDD6 Low-power IDD2/IDD61 • Operating temperature range Commercial to Industrial to 32M16 16M32 LF LG BF CM CX -5 -54 -6 -75 None L None IT :B Contact factory for availability. Only available for x16 configuration. Only available for x32 configuration. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 512Mb x16, x32 Mobile LPDDR SDRAM Features Table 2 Configuration Addressing 512 Architecture Configuration Refresh count Row addressing Column addressing 32 Meg x 16 8 Meg x 16 x 4 banks 8K A[12:0] A[9:0] 16 Meg x 32 4 Meg x 32 x 4 banks 8K A[12:0] A[8:0] Reduced Page-Size Option 16 Meg x 32 4 Meg x 32 x 4 banks 8K A[13:0] A[7:0] Figure 1 512Mb Mobile LPDDR Part Numbering The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address. Table 21 Burst Definition Table Burst Length Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. 512Mb x16, x32 Mobile LPDDR SDRAM Standard Mode Register Table 21 Burst Definition Table Continued Burst Length Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0 1-0-3-2-5-4-7-6-9-8-B-A-D-C-F-E 2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1 2-3-0-1-6-7-4-5-A-B-8-9-E-F-C-D 3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2 3-2-1-0-7-6-5-4-B-A-9-8-F-E-D-C 4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3 4-5-6-7-0-1-2-3-C-D-E-F-8-9-A-B 5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4 5-4-7-6-1-0-3-2-D-C-F-E-9-8-B-A 6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5 6-7-4-5-2-3-0-1-E-F-C-D-A-B-8-9 7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0-F-E-D-C-B-A-9-8 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8 9-8-B-A-D-C-F-E-1-0-3-2-5-4-7-6 A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9 A-B-8-9-E-F-C-D-2-3-0-1-6-7-4-5 |
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