MT41J512M4HX-125:D

MT41J512M4HX-125:D Datasheet

MT41J512M4 64 Meg x 4 x 8 Banks MT41J256M8 32 Meg x 8 x 8 Banks MT41J128M16 16 Meg x 16 x 8 Banks

Part	Datasheet
MT41J512M4HX-125:D	MT41J512M4HX-125:D (pdf)

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MT41J128M16HA-125:D	MT41J128M16HA-125:D
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MT41J512M4HX-15E:D	MT41J512M4HX-15E:D
MT41J512M4HX-187E:D	MT41J512M4HX-187E:D
MT41J128M16HA-187E:D	MT41J128M16HA-187E:D
MT41J128M16HA-15E:D	MT41J128M16HA-15E:D
MT41J256M8HX-15E IT:D	MT41J256M8HX-15E IT:D
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MT41J256M8HX-125:D	MT41J256M8HX-125:D
MT41J256M8HX-15E:D	MT41J256M8HX-15E:D
MT41J128M16HA-15E IT:D	MT41J128M16HA-15E IT:D

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2Gb x4, x8, x16 DDR3 SDRAM Features DDR3 SDRAM MT41J512M4 64 Meg x 4 x 8 Banks MT41J256M8 32 Meg x 8 x 8 Banks MT41J128M16 16 Meg x 16 x 8 Banks • VDD = VDDQ = 1.5V ±0.075V • 1.5V center-terminated push/pull I/O • Differential bidirectional data strobe • 8n-bit prefetch architecture • Differential clock inputs CK, CK# • 8 internal banks • Nominal and dynamic on-die termination ODT for data, strobe, and mask signals • Programmable CAS READ latency CL • Posted CAS additive latency AL • Programmable CAS WRITE latency CWL based on tCK • Fixed burst length BL of 8 and burst chop BC of 4 via the mode register set [MRS] • Selectable BC4 or BL8 on-the-fly OTF • Self refresh mode • TC of 0°C to 95°C 64ms, 8192 cycle refresh at 0°C to 85°C 32ms, 8192 cycle refresh at 85°C to 95°C • Self refresh temperature SRT • Write leveling • Multipurpose register • Output driver calibration Options1 • Configuration 512 Meg x 4 256 Meg x 8 128 Meg x 16 • Timing cycle time 938ps CL = 14 DDR3-2133 1.071ns CL = 13 DDR3-1866 1.25ns CL = 11 DDR3-1600 1.5ns CL = 9 DDR3-1333 1.87ns CL = 7 DDR3-1066 • Operating temperature Commercial 0°C TC +95°C Industrial TC +95°C Marking 512M4 256M8 128M16 DA HX HA JT -093 -107 -125 -15E -187E None IT :D/:H/:J/:K/ :M Note: Not all options listed can be combined to define an offered product. Use the part catalog search on for available offerings. Table 1 Key Timing Parameters Speed Grade -0931, 2, 3, 4 -1071, 2, 3 -1251, 2, -15E1, -187E Data Rate MT/s 2133 1866 1600 1333 1066 Target tRCD-tRP-CL 14-14-14 13-13-13 11-11-11 9-9-9 7-7-7 Backward compatible to 1066, CL = 7 -187E . Backward compatible to 1333, CL = 9 -15E . Backward compatible to 1600, CL = 11 Backward compatible to 1866, CL = 13 tRCD ns tRP ns CL ns Micron Technology, Inc. reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 2Gb x4, x8, x16 DDR3 SDRAM Features Table 2 Addressing Parameter Configuration Refresh count Row addressing Bank addressing Column addressing Page size 512 Meg x 4 64 Meg x 4 x 8 banks 8K 32K A[14:0] 8 BA[2:0] 2K A[11, 9:0] 256 Meg x 8 32 Meg x 8 x 8 banks 8K 32K A[14:0] 8 BA[2:0] 1K A[9:0] 128 Meg x 16 Meg x 16 x 8 banks Accesses within a given burst may be programmed to either a sequential or an interleaved order. The burst type is selected via MR0[3] see Figure 51 page The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address. DDR3 only supports 4-bit burst chop and 8-bit burst access modes. Full interleave address ordering is supported for READs, while WRITEs are restricted to nibble BC4 or word BL8 boundaries. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved. 2Gb x4, x8, x16 DDR3 SDRAM Mode Register 0 MR0 Table 77 Burst Order Burst Length READ/ WRITE READ WRITE READ WRITE Starting Column Address A[2, 1, 0] 000 001 010 011 100 101 110 111 0VV 1VV 000 001 010 011 100 101 110 111 VVV Burst Type = Sequential Decimal 0, 1, 2, 3, Z, Z, Z, Z 1, 2, 3, 0, Z, Z, Z, Z 2, 3, 0, 1, Z, Z, Z, Z 3, 0, 1, 2, Z, Z, Z, Z 4, 5, 6, 7, Z, Z, Z, Z 5, 6, 7, 4, Z, Z, Z, Z 6, 7, 4, 5, Z, Z, Z, Z 7, 4, 5, 6, Z, Z, Z, Z 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 Burst Type = Interleaved Decimal 0, 1, 2, 3, Z, Z, Z, Z 1, 0, 3, 2, Z, Z, Z, Z 2, 3, 0, 1, Z, Z, Z, Z 3, 2, 1, 0, Z, Z, Z, Z 4, 5, 6, 7, Z, Z, Z, Z 5, 4, 7, 6, Z, Z, Z, Z 6, 7, 4, 5, Z, Z, Z, Z 7, 6, 5, 4, Z, Z, Z, Z 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7 Notes 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 3, 4 1, 3, 4 Internal READ and WRITE operations start at the same point in time for BC4 as they do for BL8. Z = Data and strobe output drivers are in tri-state. V = A valid logic level 0 or 1 , but the respective input buffer ignores level-on input pins. X = “Don’t Care.” DLL RESET DLL RESET is defined by MR0[8] see Figure 51 page Programming MR0[8] to 1 activates the DLL RESET function. MR0[8] is self-clearing, meaning it returns to a value of 0 after the DLL RESET function has been initiated. Anytime the DLL RESET function is initiated, CKE must be HIGH and the clock held stable for 512 tDLLK clock cycles before a READ command can be issued. This is to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in invalid output timing specifications, such as tDQSCK timings. Write Recovery WRITE recovery time is defined by MR0[11:9] see Figure 51 page Write recovery values of 5, 6, 7, 8, 10, 12, or 14 may be used by programming MR0[11:9]. The user is Micron Technology, Inc. reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved. 2Gb x4, x8, x16 DDR3 SDRAM Mode Register 0 MR0 required to program the correct value of write recovery, which is calculated by dividing tWR ns by tCK ns and rounding up a noninteger value to the next integer WR cycles = roundup tWR [ns]/tCK [ns] . Precharge Power-Down Precharge PD The precharge power-down PD bit applies only when precharge power-down mode is being used. When MR0[12] is set to 0, the DLL is off during precharge power-down, providing a lower standby current mode however, tXPDLL must be satisfied when exiting. When MR0[12] is set to 1, the DLL continues to run during precharge power-down mode to enable a faster exit of precharge power-down mode however, tXP must be satisfied when exiting see Power-Down Mode page CAS Latency CL The CL is defined by MR0[6:4], as shown in Figure 51 page CAS latency is the delay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The CL can be set to 5, 6, 7, 8, 9, 10, 11, 12, 13 or DDR3 SDRAM do not support half-clock latencies. Examples of CL = 6 and CL = 8 are shown below. If an internal READ command is registered at clock edge n, and the CAS latency is m clocks, the data will be available nominally coincident with clock edge n + m.Table 52 page 72 through Table 55 page 75 indicate the CLs supported at various operating frequencies. Figure 52 READ Latency Command READ AL = 0, CL = 6 DQS, DQS# n+1 n+2 n+3 n+4 CK# CK Command T0 READ

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2Gb x4, x8, x16 DDR3 SDRAM Features

DDR3 SDRAM

MT41J512M4 64 Meg x 4 x 8 Banks MT41J256M8 32 Meg x 8 x 8 Banks MT41J128M16 16 Meg x 16 x 8 Banks
• VDD = VDDQ = 1.5V ±0.075V
• 1.5V center-terminated push/pull I/O
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs CK, CK#
• 8 internal banks
• Nominal and dynamic on-die termination ODT
for data, strobe, and mask signals
• Programmable CAS READ latency CL
• Posted CAS additive latency AL
• Programmable CAS WRITE latency CWL based on
tCK
• Fixed burst length BL of 8 and burst chop BC of 4
via the mode register set [MRS]
• Selectable BC4 or BL8 on-the-fly OTF
• Self refresh mode
• TC of 0°C to 95°C
64ms, 8192 cycle refresh at 0°C to 85°C 32ms, 8192 cycle refresh at 85°C to 95°C
• Self refresh temperature SRT
• Write leveling
• Multipurpose register
• Output driver calibration

Options1
• Configuration 512 Meg x 4 256 Meg x 8 128 Meg x 16
• Timing cycle time 938ps CL = 14 DDR3-2133 1.071ns CL = 13 DDR3-1866 1.25ns CL = 11 DDR3-1600 1.5ns CL = 9 DDR3-1333 1.87ns CL = 7 DDR3-1066
• Operating temperature Commercial 0°C TC +95°C Industrial TC +95°C

Marking
512M4 256M8 128M16

DA HX

HA JT
-093 -107 -125 -15E -187E

None IT
:D/:H/:J/:K/ :M

Note:

Not all options listed can be combined to define an offered product. Use the part catalog search on for available offerings.

Table 1 Key Timing Parameters

Speed Grade -0931, 2, 3, 4 -1071, 2, 3 -1251, 2, -15E1, -187E

Data Rate MT/s 2133 1866 1600 1333 1066

Target tRCD-tRP-CL 14-14-14 13-13-13 11-11-11 9-9-9 7-7-7

Backward compatible to 1066, CL = 7 -187E . Backward compatible to 1333, CL = 9 -15E . Backward compatible to 1600, CL = 11 Backward compatible to 1866, CL = 13
tRCD ns
tRP ns

CL ns

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
2Gb x4, x8, x16 DDR3 SDRAM Features

Table 2 Addressing

Parameter Configuration Refresh count Row addressing Bank addressing Column addressing Page size
512 Meg x 4 64 Meg x 4 x 8 banks
8K 32K A[14:0]
8 BA[2:0] 2K A[11, 9:0]
256 Meg x 8 32 Meg x 8 x 8 banks
8K 32K A[14:0]
8 BA[2:0] 1K A[9:0]
128 Meg x 16 Meg x 16 x 8 banks
Accesses within a given burst may be programmed to either a sequential or an interleaved order. The burst type is selected via MR0[3] see Figure 51 page The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address. DDR3 only supports 4-bit burst chop and 8-bit burst access modes. Full interleave address ordering is supported for READs, while WRITEs are restricted to nibble BC4 or word BL8 boundaries.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.
2Gb x4, x8, x16 DDR3 SDRAM Mode Register 0 MR0

Table 77 Burst Order

Burst Length

READ/ WRITE READ

WRITE READ

WRITE

Starting Column Address

A[2, 1, 0] 000 001 010 011 100 101 110 111 0VV 1VV 000 001 010 011 100 101 110 111 VVV

Burst Type = Sequential Decimal
0, 1, 2, 3, Z, Z, Z, Z 1, 2, 3, 0, Z, Z, Z, Z 2, 3, 0, 1, Z, Z, Z, Z 3, 0, 1, 2, Z, Z, Z, Z 4, 5, 6, 7, Z, Z, Z, Z 5, 6, 7, 4, Z, Z, Z, Z 6, 7, 4, 5, Z, Z, Z, Z 7, 4, 5, 6, Z, Z, Z, Z 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7

Burst Type = Interleaved Decimal
0, 1, 2, 3, Z, Z, Z, Z 1, 0, 3, 2, Z, Z, Z, Z 2, 3, 0, 1, Z, Z, Z, Z 3, 2, 1, 0, Z, Z, Z, Z 4, 5, 6, 7, Z, Z, Z, Z 5, 4, 7, 6, Z, Z, Z, Z 6, 7, 4, 5, Z, Z, Z, Z 7, 6, 5, 4, Z, Z, Z, Z 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7

Notes 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2
1, 3, 4 1, 3, 4

Internal READ and WRITE operations start at the same point in time for BC4 as they do for BL8.

Z = Data and strobe output drivers are in tri-state. V = A valid logic level 0 or 1 , but the respective input buffer ignores level-on input
pins. X = “Don’t Care.”

DLL RESET

DLL RESET is defined by MR0[8] see Figure 51 page Programming MR0[8] to 1 activates the DLL RESET function. MR0[8] is self-clearing, meaning it returns to a value of 0 after the DLL RESET function has been initiated.

Anytime the DLL RESET function is initiated, CKE must be HIGH and the clock held stable for 512 tDLLK clock cycles before a READ command can be issued. This is to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in invalid output timing specifications, such as tDQSCK timings.

Write Recovery

WRITE recovery time is defined by MR0[11:9] see Figure 51 page Write recovery values of 5, 6, 7, 8, 10, 12, or 14 may be used by programming MR0[11:9]. The user is

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.
2Gb x4, x8, x16 DDR3 SDRAM Mode Register 0 MR0
required to program the correct value of write recovery, which is calculated by dividing tWR ns by tCK ns and rounding up a noninteger value to the next integer WR cycles = roundup tWR [ns]/tCK [ns] .

Precharge Power-Down Precharge PD

The precharge power-down PD bit applies only when precharge power-down mode is being used. When MR0[12] is set to 0, the DLL is off during precharge power-down, providing a lower standby current mode however, tXPDLL must be satisfied when exiting. When MR0[12] is set to 1, the DLL continues to run during precharge power-down mode to enable a faster exit of precharge power-down mode however, tXP must be satisfied when exiting see Power-Down Mode page

CAS Latency CL

The CL is defined by MR0[6:4], as shown in Figure 51 page CAS latency is the delay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The CL can be set to 5, 6, 7, 8, 9, 10, 11, 12, 13 or DDR3 SDRAM do not support half-clock latencies.

Examples of CL = 6 and CL = 8 are shown below. If an internal READ command is registered at clock edge n, and the CAS latency is m clocks, the data will be available nominally coincident with clock edge n + m.Table 52 page 72 through Table 55 page 75 indicate the CLs supported at various operating frequencies.

Figure 52 READ Latency

Command

READ

AL = 0, CL = 6

DQS, DQS#
n+1 n+2 n+3 n+4

CK# CK

Command

T0 READ

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Datasheet ID: MT41J512M4HX-125:D 648389