MT41J256M8HX-15E AAT:D

MT41J256M8HX-15E AAT:D Datasheet

MT41J256M4 32 Meg x 4 x 8 Banks MT41J128M8 16 Meg x 8 x 8 Banks MT41J64M16 8 Meg x 16 x 8 Banks

Part	Datasheet
MT41J256M8HX-15E AAT:D	MT41J256M8HX-15E AAT:D (pdf)

Related Parts	Information
MT41J256M8HX-15E AIT:D	MT41J256M8HX-15E AIT:D
MT41J128M16HA-15E AIT:D	MT41J128M16HA-15E AIT:D
MT41J128M16HA-15E AAT:D	MT41J128M16HA-15E AAT:D
MT41J64M16LA-187E:B TR	MT41J64M16LA-187E:B TR
MT41J64M16LA-15E:B TR	MT41J64M16LA-15E:B TR
MT41J128M8HX-15E:D TR	MT41J128M8HX-15E:D TR
MT41J256M4HX-15E:D TR	MT41J256M4HX-15E:D TR

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DDR3 SDRAM MT41J256M4 32 Meg x 4 x 8 Banks MT41J128M8 16 Meg x 8 x 8 Banks MT41J64M16 8 Meg x 16 x 8 Banks 1Gb x4, x8, x16 DDR3 SDRAM Features • VDD = VDDQ = +1.5V ±0.075V • 1.5V center-terminated push/pull I/O • Differential bidirectional data strobe • 8n-bit prefetch architecture • Differential clock inputs CK, CK# • 8 internal banks • Nominal and dynamic on-die termination ODT for data, strobe, and mask signals • CAS READ latency CL 5, 6, 7, 8, 9, 10, or 11 • POSTED CAS ADDITIVE latency AL 0, CL - 1, CL - 2 • CAS WRITE latency CWL 5, 6, 7, 8, based on tCK • Fixed burst length BL of 8 and burst chop BC of 4 via the mode register set [MRS] • Selectable BC4 or BL8 on-the-fly OTF • Self refresh mode • TC of 0oC to 95oC 64ms, 8,192 cycle refresh at 0oC to 85oC 32ms at 85oC to 95oC • Clock frequency range of MHz • Self refresh temperature SRT • Automatic self refresh ASR • Write leveling • Multipurpose register • Output driver calibration Options Marking • Configuration 256 Meg x 4 128 Meg x 8 64 Meg x 16 • Timing - cycle time 1.25ns CL = 11 DDR3-1600 1.25ns CL = 10 DDR3-1600 1.25ns CL = 9 DDR3-1600 1.5ns CL = 10 DDR3-1333 1.5ns CL = 9 DDR3-1333 1.5ns CL = 8 DDR3-1333 1.87ns CL = 8 DDR3-1066 1.87ns CL = 7 DDR3-1066 2.5ns CL = 6 DDR3-800 2.5ns CL = 5 DDR3-800 256M4 128M8 64M16 JP HX BY -125 -125E -125F -15 -15E -15F -187 -187E -25 -25E :B/:D/:F Table 1 Key Timing Parameters Speed Grade -125 -125E -125F -15 -15E -15F -187 -187E -25 -25E Data Rate MT/s Target tRCD-tRP-CL 1600 1333 11-11-11 10-10-10 9-9-9 10-10-10 9-9-9 8-8-8 1066 8-8-8 1066 800 7-7-7 6-6-6 5-5-5 tRCD ns 15 12 15 tRP ns 15 12 15 CL ns 15 12 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 1Gb x4, x8, x16 DDR3 SDRAM Features Table 2 Addressing Parameter Configuration Refresh count Row addressing Bank addressing Column addressing 256 Meg x 4 Accesses within a given burst may be programmed to either a sequential or an interleaved order. The burst type is selected via MR0[3], as shown in Figure The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 68 on page DDR3 only supports 4-bit burst chop and 8-bit burst access modes. Full interleave address ordering is supported for READs, while WRITEs are restricted to nibble BC4 or word BL8 boundaries. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved. 1Gb x4, x8, x16 DDR3 SDRAM Operations Table 68 Burst Order Burst Length 4 chop READ/ WRITE READ WRITE READ WRITE Starting Column Address A[2, 1, 0] 000 001 010 011 100 101 110 111 0VV 1VV 000 001 010 011 100 101 110 111 VVV Burst Type = Sequential Decimal 0, 1, 2, 3, Z, Z, Z, Z 1, 2, 3, 0, Z, Z, Z, Z 2, 3, 0, 1, Z, Z, Z, Z 3, 0, 1, 2, Z, Z, Z, Z 4, 5, 6, 7, Z, Z, Z, Z 5, 6, 7, 4, Z, Z, Z, Z 6, 7, 4, 5, Z, Z, Z, Z 7, 4, 5, 6, Z, Z, Z, Z 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 Burst Type = Interleaved Decimal 0, 1, 2, 3, Z, Z, Z, Z 1, 0, 3, 2, Z, Z, Z, Z 2, 3, 0, 1, Z, Z, Z, Z 3, 2, 1, 0, Z, Z, Z, Z 4, 5, 6, 7, Z, Z, Z, Z 5, 4, 7, 6, Z, Z, Z, Z 6, 7, 4, 5, Z, Z, Z, Z 7, 6, 5, 4, Z, Z, Z, Z 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7 Notes 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 3, 4 1, 3, 4 Internal READ and WRITE operations start at the same point in time for BC4 as they do for BL8. Z = Data and strobe output drivers are in tristate. V = A valid logic level 0 or 1 , but the respective input buffer ignores level-on input pins. X = “Don’t Care.” DLL RESET DLL RESET is defined by MR0[8] see Figure 54 on page Programming MR0[8] to “1” activates the DLL RESET function. MR0[8] is self-clearing, meaning it returns to a value of “0” after the DLL RESET function has been initiated. Anytime the DLL RESET function is initiated, CKE must be HIGH and the clock held stable for 512 tDLLK clock cycles before a READ command can be issued. This is to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in invalid output timing specifications, such as tDQSCK timings. Write Recovery WRITE recovery time is defined by MR0[11:9] see Figure 54 on page Write recovery values of 5, 6, 7, 8, 10, or 12 may be used by programming MR0[11:9]. The user is required to program the correct value of write recovery and is calculated by dividing tWR ns by tCK ns and rounding up a noninteger value to the next integer WR cycles = roundup tWR [ns]/tCK [ns] . Micron Technology, Inc., reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved. 1Gb x4, x8, x16 DDR3 SDRAM Operations Precharge Power-Down Precharge PD The precharge PD bit applies only when precharge power-down mode is being used. When MR0[12] is set to “0,” the DLL is off during precharge power-down providing a lower standby current mode however, tXPDLL must be satisfied when exiting. When MR0[12] is set to “1,” the DLL continues to run during precharge power-down mode to enable a faster exit of precharge power-down mode however, tXP must be satisfied when exiting see "Power-Down Mode" on page CAS Latency CL The CL is defined by MR0[6:4], as shown in Figure 54 on page CAS latency is the delay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The CL can be set to 5, 6, 7, 8, 9, or DDR3 SDRAM do not support half-clock latencies. Examples of CL = 6 and CL = 8 are shown in Figure If an internal READ command is registered at clock edge n, and the CAS latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 49 on page 63 through Table 51 on page 65 indicate the CLs supported at various operating frequencies. Figure 55 READ Latency Command READ AL = 0, CL = 6 DQS, DQS# n+1 n+2 n+3 n+4 CK# CK Command DQS, DQS# DQ READ

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DDR3 SDRAM

MT41J256M4 32 Meg x 4 x 8 Banks MT41J128M8 16 Meg x 8 x 8 Banks MT41J64M16 8 Meg x 16 x 8 Banks
1Gb x4, x8, x16 DDR3 SDRAM Features
• VDD = VDDQ = +1.5V ±0.075V
• 1.5V center-terminated push/pull I/O
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs CK, CK#
• 8 internal banks
• Nominal and dynamic on-die termination ODT for
data, strobe, and mask signals
• CAS READ latency CL 5, 6, 7, 8, 9, 10, or 11
• POSTED CAS ADDITIVE latency AL 0, CL - 1, CL - 2
• CAS WRITE latency CWL 5, 6, 7, 8, based on tCK
• Fixed burst length BL of 8 and burst chop BC of 4
via the mode register set [MRS]
• Selectable BC4 or BL8 on-the-fly OTF
• Self refresh mode
• TC of 0oC to 95oC
64ms, 8,192 cycle refresh at 0oC to 85oC 32ms at 85oC to 95oC
• Clock frequency range of MHz
• Self refresh temperature SRT
• Automatic self refresh ASR
• Write leveling
• Multipurpose register
• Output driver calibration

Options

Marking
• Configuration 256 Meg x 4 128 Meg x 8 64 Meg x 16
• Timing - cycle time 1.25ns CL = 11 DDR3-1600 1.25ns CL = 10 DDR3-1600 1.25ns CL = 9 DDR3-1600 1.5ns CL = 10 DDR3-1333 1.5ns CL = 9 DDR3-1333 1.5ns CL = 8 DDR3-1333 1.87ns CL = 8 DDR3-1066 1.87ns CL = 7 DDR3-1066 2.5ns CL = 6 DDR3-800 2.5ns CL = 5 DDR3-800
256M4 128M8 64M16

JP HX BY
-125 -125E -125F
-15 -15E -15F -187 -187E -25 -25E :B/:D/:F

Table 1 Key Timing Parameters

Speed Grade
-125 -125E -125F
-15 -15E -15F -187 -187E -25 -25E

Data Rate MT/s Target tRCD-tRP-CL
1600 1333
11-11-11 10-10-10
9-9-9 10-10-10
9-9-9 8-8-8
1066
8-8-8
1066 800
7-7-7 6-6-6 5-5-5
tRCD ns
15 12 15
tRP ns
15 12 15

CL ns
15 12 15

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
1Gb x4, x8, x16 DDR3 SDRAM Features

Table 2 Addressing

Parameter

Configuration Refresh count Row addressing Bank addressing Column addressing
256 Meg x 4
Accesses within a given burst may be programmed to either a sequential or an interleaved order. The burst type is selected via MR0[3], as shown in Figure The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 68 on page DDR3 only supports 4-bit burst chop and 8-bit burst access modes. Full interleave address ordering is supported for READs, while WRITEs are restricted to nibble BC4 or word BL8 boundaries.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.
1Gb x4, x8, x16 DDR3 SDRAM Operations

Table 68 Burst Order

Burst Length 4 chop

READ/ WRITE READ

WRITE READ

WRITE

Starting Column Address

A[2, 1, 0]
000 001 010 011 100 101 110 111 0VV 1VV 000 001 010 011 100 101 110 111 VVV

Burst Type = Sequential Decimal
0, 1, 2, 3, Z, Z, Z, Z 1, 2, 3, 0, Z, Z, Z, Z 2, 3, 0, 1, Z, Z, Z, Z 3, 0, 1, 2, Z, Z, Z, Z 4, 5, 6, 7, Z, Z, Z, Z 5, 6, 7, 4, Z, Z, Z, Z 6, 7, 4, 5, Z, Z, Z, Z 7, 4, 5, 6, Z, Z, Z, Z 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7

Burst Type = Interleaved Decimal
0, 1, 2, 3, Z, Z, Z, Z 1, 0, 3, 2, Z, Z, Z, Z 2, 3, 0, 1, Z, Z, Z, Z 3, 2, 1, 0, Z, Z, Z, Z 4, 5, 6, 7, Z, Z, Z, Z 5, 4, 7, 6, Z, Z, Z, Z 6, 7, 4, 5, Z, Z, Z, Z 7, 6, 5, 4, Z, Z, Z, Z 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7

Notes
1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 3, 4 1, 3, 4

Internal READ and WRITE operations start at the same point in time for BC4 as they do for BL8.

Z = Data and strobe output drivers are in tristate. V = A valid logic level 0 or 1 , but the respective input buffer ignores level-on input pins. X = “Don’t Care.”

DLL RESET

DLL RESET is defined by MR0[8] see Figure 54 on page Programming MR0[8] to “1” activates the DLL RESET function. MR0[8] is self-clearing, meaning it returns to a value of “0” after the DLL RESET function has been initiated.

Anytime the DLL RESET function is initiated, CKE must be HIGH and the clock held stable for 512 tDLLK clock cycles before a READ command can be issued. This is to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in invalid output timing specifications, such as tDQSCK timings.

Write Recovery

WRITE recovery time is defined by MR0[11:9] see Figure 54 on page Write recovery
values of 5, 6, 7, 8, 10, or 12 may be used by programming MR0[11:9]. The user is required to program the correct value of write recovery and is calculated by dividing tWR ns by tCK ns and rounding up a noninteger value to the next integer WR cycles = roundup tWR [ns]/tCK [ns] .

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.
1Gb x4, x8, x16 DDR3 SDRAM Operations

Precharge Power-Down Precharge PD

The precharge PD bit applies only when precharge power-down mode is being used. When MR0[12] is set to “0,” the DLL is off during precharge power-down providing a lower standby current mode however, tXPDLL must be satisfied when exiting. When MR0[12] is set to “1,” the DLL continues to run during precharge power-down mode to enable a faster exit of precharge power-down mode however, tXP must be satisfied when exiting see "Power-Down Mode" on page

CAS Latency CL

The CL is defined by MR0[6:4], as shown in Figure 54 on page CAS latency is the delay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The CL can be set to 5, 6, 7, 8, 9, or DDR3 SDRAM do not support half-clock latencies.

Examples of CL = 6 and CL = 8 are shown in Figure If an internal READ command is registered at clock edge n, and the CAS latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 49 on page 63 through Table 51 on page 65 indicate the CLs supported at various operating frequencies.

Figure 55 READ Latency

Command

READ

AL = 0, CL = 6

DQS, DQS#
n+1 n+2 n+3 n+4

CK# CK Command

DQS, DQS# DQ

READ

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Datasheet ID: MT41J256M8HX-15EAAT:D 648388