MB86613SPFV-G-BND
MB86613SPFV-G-BND Datasheet
MB86613S IEEE1394 Open HCI Controller
| Part | Datasheet |
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MB86613SPFV-G-BND |
MB86613SPFV-G-BND (pdf) |
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| MB86613S IEEE1394 Open HCI Controller Product Specification Provisional Fujitsu Limited Fujitsu VLSI Ltd. Introduction Related Documents Overview 1 1394 Serial Bus Controller Block - Compliant with IEEE1394- 1995 and P1394a draft2.0 - Integrates PHY and LINK layers into single- chip. - 1394 port number 1 port - Transfer Data Rate S100, S200, and S400 - On- chip PLL 400MHz for PHY and 50MHz for Link core. - Cycle- Master Function - On- chip Bus Management CSRs - 6- pin cable supported - On- chip transceiver and comparator - On- chip another comparator for detecting the cable power - On- chip 6KB FIFO : a Asynchronous Transmit- FIFO 1.5KB b Isochronous Transmit- FIFO 1.5KB c Asynchronous/Isochronous Receive- FIFO 3.0KB - On- chip context program work memory 128B x 3 PCI Bus Controller Block : - 100- pin plastic LQFP package - Two power supply systems +5V and +3.3V Block Diagram PCI/DMA Block DMAC PCI I/F Slave AR/IR- CPC OHCI Block Physical- Request Unit PRU AT- ContextProgram Controller AT- CPC IT- ContextProgram Controller IT- CPC Work Memory 128B x 3 FIFO 6KB Open HCI Registers 2048B Link- Rx Link- Tx 1394 Block LINK Core 1394 bus manager serial ROM I/F Fig. Block Diagram of MB86613S 2 Block Description PCI Block PCI block consists of the following components 1 PCI Interface: OHCI Block OHCI block includes the powerful DMA engines for ContextProgram Control, work memory, FIFO, and LINKTx, - Rx sections 1 ContextProgramController CPC : This controller is ContextProgram Processor Unit that analyzes the context programs stored in the system memory. For Receive state, the on- chip R- CPC transfers the OHCI packet stored in the FIFO to the system memory via PCI interface. For Transmit state, the on- chip AT- , and IT- CPC transmit the packet stored in the system memory to the FIFO. This section also includes a PHY Request Unit PRU which works for automatically decoding the physical request packet if received. ContextProgram Work Memory CP Work This block is work RAM area used for storing IT- , AT- , and, Receive- context program to be processed, and also storing header information on received physical request packet. The area is formed by 128B x 3 units of SRAM. Open HCI Registers This block contains total 2048- byte register set as defined in the Open HCI standard. For the register map, see Section 3 in this document. FIFO Fig. descriptor’s Byte Ordering for Transmitting quadlet write request packet EEPROM Figure shows the EEPROM address map. The EEPROM needs to contain the vendor ID and the chip ID to be loaded to the Global Unique ID register of the OHCI register, in addition to the data to be loaded to the subsystem ID, subsystem vendor ID of PCI configuration register, the CAP pointer of the power management and CIS pointer of Cadr Bus. After the device hardware reset, the data in the EEPROM is loaded into PCI configuration register or OHCI register. 87 “0000” GUIDLo LSB Table7- 1 GUIDLo MSB GUIDHi LSB GUIDHi MSB CARDBUS CIS Pointer LSB CARDBUS CIS Pointer MSB Subsystem Vendor ID Subsystem ID Fig. EEPROM Address Map Table 7- 1 Adr00h bit description Bit ---15 Field Name reset -------------- ---- PWE_EN description at this bit reduces the power consumption during idle no 1394 connection . OHCImode Setting “0” at this bit enables OHCI1.0 mode Setting “1” at this bit enables OHCI1.1 mode. PCI_PME# Setting ”1” at this bit enables the PCI PME# signal. VENDOR_ID Setting ”0” at this bit shows Fujitsu Vendor ID. Normally set to DEBUG_MODE 1b Setting ”1” at this bit enables to access the debug register and EEPROM configuration write through PCI configuration register. Normally set to BYTE_SWAP Setting ”1” at this bit performs the byte swapping for the data of the 1394 configuration ROM access. Normally set to BIOS_EN Setting ”1” at this bit sets the ExpantionROMBaseAddress, rom_enable bit. MB86613S does not support Expantion ROM, This bit is set to Please write “0” to the reserved bits of Adr 00h. |
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