MT36VDDF25672Y-335D2

MT36VDDF25672Y-335D2 Datasheet

MT36VDDF12872 1GB MT36VDDF25672 2GB

Part	Datasheet
MT36VDDF25672Y-335D2	MT36VDDF25672Y-335D2 (pdf)

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DDR SDRAM REGISTERED DIMM 1GB, 2GB x72, ECC, DR 184-PIN DDR RDIMM MT36VDDF12872 1GB MT36VDDF25672 2GB For the latest data sheet, please refer to the Web site: • 184-pin, dual in-line memory module DIMM • Fast data transfer rates PC1600, PC2100, or PC 2700 • Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR SDRAM components • Registered Inputs with one-clock delay • Phase-lock loop PLL clock driver to reduce loading • Supports ECC error detection and correction • 1GB 128 Meg x 72 , 2GB, 256 Meg x 72 • VDD = VDDQ = +2.5V VDDSPD = +2.3V to +3.6V • 2.5V I/O SSTL_2 compatible • Commands entered on each positive CK edge • DQS edge-aligned with data for READs; centeraligned with data for WRITEs • Internal, pipelined double data rate DDR architecture two data accesses per clock cycle • Bidirectional data strobe DQS transmitted/ received with source-synchronous data capture • Differential clock inputs CK and CK# • Four internal device banks for concurrent operation • Programmable burst lengths 2, 4, or 8 • Auto precharge option • Auto Refresh and Self Refresh Modes • 7.8125µs maximum average periodic refresh interval • Serial Presence Detect SPD with EEPROM • Programmable READ CAS latency • Gold edge contacts Table 1 Address Table Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing 8K 4 BA0, BA1 256Mb 64 Meg x 4 2K A11 2 S0#, S1# 8K 4 BA0, BA1 512Mb 128 Meg x 4 4K A11, A12 2 S0#, S1# Figure 1 184-Pin DIMM MO-206 Standard 1.7in. 43.18mm Low-Profile 1GB 1.2in. 30.48mm Low Profile 2GB 1.2in. 30.48mm OPTIONS MARKING • Package 184-pin DIMM standard 184-pin DIMM lead-free 1 • Memory Clock, Speed, CAS Latency2 6ns 166MHz , 333 MT/s, CL = 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL = 2 -335 -2621 -26A1 7.5ns 133 MHz , 266 MT/s, CL = -265 10ns 100 MHz , 200 MT/s, CL = 2 -202 • PCB Standard 1.7in. 43.18mm See page 2 note Low-Profile 1.2in. 30.48mm See page 2 note NOTE Contact Micron for product availability. CL = CAS READ Latency registered mode will add one clock cycle to CL. 2004 Micron Technology, Inc. All rights reserved. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Figure 8, Burst Definition Table, on page Figure 7 Mode Register Definition Diagram BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M14 and M13 BA1 and BA0 must be 0, 0 to select the base mode register vs. the extended mode register . M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 Burst Length M3 = 0 Reserved 2 4 8 Reserved M3 = 1 Reserved 2 4 8 Reserved Burst Type Sequential Interleaved M6 M5 M4 000 001 010 011 100 101 110 111 CAS Latency Reserved 2 Reserved M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - -- M6-M0 Valid Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. Table 8 Burst Definition Table BURST LENGTH STARTING COLUMN ADDRESS ORDER OF ACCESSES WITHIN A BURST TYPE = TYPE = SEQUENTIAL INTERLEAVED A1 A0 0-1-2-3 0-1-2-3 1-2-3-0 1-0-3-2 2-3-0-1 2-3-0-1 3-0-1-2 3-2-1-0 A2 A1 A0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

PDF Datasheet Preview

DDR SDRAM REGISTERED DIMM
1GB, 2GB x72, ECC, DR 184-PIN DDR RDIMM

MT36VDDF12872 1GB MT36VDDF25672 2GB

For the latest data sheet, please refer to the Web site:
• 184-pin, dual in-line memory module DIMM
• Fast data transfer rates PC1600, PC2100, or PC 2700
• Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR

SDRAM components
• Registered Inputs with one-clock delay
• Phase-lock loop PLL clock driver to reduce loading
• Supports ECC error detection and correction
• 1GB 128 Meg x 72 , 2GB, 256 Meg x 72
• VDD = VDDQ = +2.5V VDDSPD = +2.3V to +3.6V
• 2.5V I/O SSTL_2 compatible
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs;
centeraligned with data for WRITEs
• Internal, pipelined double data rate DDR
architecture two data accesses per clock cycle
• Bidirectional data strobe DQS transmitted/
received with source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 7.8125µs maximum average periodic refresh interval
• Serial Presence Detect SPD with EEPROM
• Programmable READ CAS latency
• Gold edge contacts

Table 1 Address Table

Refresh Count Row Addressing Device Bank Addressing Device Configuration

Column Addressing

Module Rank Addressing
8K 4 BA0, BA1
256Mb 64 Meg x 4 2K

A11 2 S0#, S1#
8K 4 BA0, BA1
512Mb 128 Meg x 4
4K A11, A12 2 S0#, S1#

Figure 1 184-Pin DIMM MO-206

Standard 1.7in. 43.18mm

Low-Profile 1GB 1.2in. 30.48mm Low Profile 2GB 1.2in. 30.48mm

OPTIONS

MARKING
• Package
184-pin DIMM standard
184-pin DIMM lead-free 1
• Memory Clock, Speed, CAS Latency2
6ns 166MHz , 333 MT/s, CL = 7.5ns 133 MHz , 266 MT/s, CL = 2 7.5ns 133 MHz , 266 MT/s, CL = 2
-335 -2621 -26A1
7.5ns 133 MHz , 266 MT/s, CL =
-265
10ns 100 MHz , 200 MT/s, CL = 2
-202
• PCB

Standard 1.7in. 43.18mm

See page 2 note

Low-Profile 1.2in. 30.48mm

See page 2 note

NOTE Contact Micron for product availability. CL = CAS READ Latency registered mode will add one clock cycle to CL.
2004 Micron Technology, Inc. All rights reserved.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Figure 8, Burst Definition Table, on page

Figure 7 Mode Register Definition Diagram

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M14 and M13 BA1 and BA0 must be 0, 0 to select the base mode register vs. the extended mode register .

M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11

Burst Length

M3 = 0 Reserved
2 4 8 Reserved

M3 = 1 Reserved
2 4 8 Reserved

Burst Type

Sequential

Interleaved

M6 M5 M4 000 001 010 011 100 101 110 111

CAS Latency Reserved 2 Reserved

M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - --

M6-M0 Valid

Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.

Table 8 Burst Definition Table

BURST LENGTH

STARTING COLUMN ADDRESS

ORDER OF ACCESSES WITHIN A BURST

TYPE =

TYPE =

SEQUENTIAL INTERLEAVED

A1 A0
0-1-2-3
0-1-2-3
1-2-3-0
1-0-3-2
2-3-0-1
2-3-0-1
3-0-1-2
3-2-1-0

A2 A1 A0
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

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Datasheet ID: MT36VDDF25672Y-335D2 648384