MT36LSDT12872G-13ED2

MT36LSDT12872G-13ED2 Datasheet

MT36LSDT12872 1GB MT36LSDT25672 2GB

Part	Datasheet
MT36LSDT12872G-13ED2	MT36LSDT12872G-13ED2 (pdf)

Related Parts	Information
MT36LSDF12872G-133D1	MT36LSDF12872G-133D1
MT36LSDF12872G-13ED1	MT36LSDF12872G-13ED1
MT36LSDT25672G-13EC2	MT36LSDT25672G-13EC2

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1GB, 2GB x72, ECC, DR 168-Pin SDRAM RDIMM Features Synchronous DRAM Module MT36LSDT12872 1GB MT36LSDT25672 2GB For the latest data sheet, refer to Micron’s Web site: • 168-pin, dual in-line memory module DIMM • PC100- and PC133-compliant • Registered inputs with one-clock delay • Phase-lock loop PLL clock driver to reduce loading • Utilizes 125 MHz and 133 MHz SDRAM components • Supports ECC error detection and correction • 1GB 128 Meg x 72 and 2GB 256 Meg x 72 • Single +3.3V power supply • Fully synchronous all signals registered on positive edge of PLL clock • Internal pipelined operation column address can be changed every clock cycle • Internal SDRAM banks for hiding row access/ precharge • Programmable burst lengths 1, 2, 4, 8, or full page • Auto precharge, includes concurrent auto precharge • Auto refresh mode • Self refresh mode 64ms, 4,096-cycle refresh • LVTTL-compatible inputs and outputs • Serial presence-detect SPD • Gold edge contacts Table 1: Timing Parameters CL = CAS READ latency Module Marking -13E -133 Clock 133 MHz 133 MHz Access Time CL = 2 5.4ns CL = 3 5.4ns Setup Time Hold Time Figure 1 168-Pin DIMM MO-161 Standard 1.70in. 43.18mm Low-Profile 1.20in. 30.48mm Options • Package 168-pin DIMM standard 168-pin DIMM lead-free • Frequency/CAS Latency2 133 MHz/CL = 2 133 MHz/CL = 3 • PCB Standard 1.70in 43.18mm Low-Profile 1.20in. 30.48mm Marking -13E -133 See note on page 2 See note on page 2 Notes Contact Micron for product availability. Registered mode adds one clock cycle to CL. Table 2 Address Table Parameter Refresh Count Device Banks Device Configuration Row Addressing Column Addressing Module Ranks 8K 4 BA0, BA1 256Mb 64 Meg x 4 8K 2K A11 2 S0#, S2# S1#, S3# 8K 4 BA0, BA1 512Mb 128 Meg x 4 8K 4K A11, A12 2 S0#, S2# S1#, S3# Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 1GB, 2GB x72, ECC, DR 168-Pin SDRAM RDIMM Features Table 3 Part Numbers MT36LSDT12872G-13E__ MT36LSDT12872Y-13E__ MT36LSDT12872G-133__ MT36LSDT12872Y-133__ MT36LSDT25672G-13E__ MT36LSDT25672Y-13E__ MT36LSDT25672G-133__ MT36LSDT25672Y-133__ The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6 on page The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQ will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at T0 and the latency is programmed to two clocks, the DQ will start driving after T1 and the data will be valid by T2, as shown in the Figure 5 on page Table 7 on page 12, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved. 1GB, 2GB x72, ECC, DR 168-Pin SDRAM RDIMM Mode Register Definition Operating Mode The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both read and write bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via applies to both read and write bursts when M9 = 1, the programmed burst length applies to read bursts, but write accesses are single-location non burst accesses. Table 7 CAS Latency Table Registered mode adds one clock cycle to CAS latency Speed -13E -133 Allowable Operating Clock Frequency MHz CAS Latency = 2 133 100 CAS Latency = 3 143 133 Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved. 1GB, 2GB x72, ECC, DR 168-Pin SDRAM RDIMM Commands Commands Table 8 provides a quick reference of available commands. This is followed by a written description of each command. For a more detailed description of commands and operations refer to the 256Mb or 512Mb SDRAM component data sheets. Table 8: SDRAM Command and DQMB Operation Truth Table CKE is HIGH for all commands shown except Self Refresh Name Function COMMAND INHIBIT NOP NO OPERATION NOP ACTIVE Select bank and activate row READ Select bank and column, and start READ burst WRITE Select bank and column, and start WRITE burst TERMINATE PRECHARGE Deactivate row in bank or banks AUTO REFRESH or SELF REFRESH Enter self refresh mode LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z CS# RAS# CAS# WE# DQMB ADDR DQs Notes X Bank/Row X H L/H7 Bank/Col X L/H7 Bank/Col Valid Active Code X Op-Code X Active 7 High-Z 7 Notes provide device row address. BA0, BA1 determine which device bank is made active. A11 1GB or A11, A12 2GB provide device column address A10 HIGH enables the auto precharge feature nonpersistent , while A10 LOW disables the auto precharge feature BA0, BA1 determine which device bank is being read from or written to. A10 LOW BA0, BA1 determine which device bank is being precharged. A10 HIGH both device banks are precharged and BA0, BA1 are “Don’t Care.” This command is Auto Refresh if CKE is HIGH, Self Refresh if CKE is LOW. Internal refresh counter controls row addressing all inputs and I/Os are “Don’t Care” except for CKE. define the op-code written to the Mode Register, and should be driven low. Activates or deactivates the DQs during WRITEs zero-clock delay and READs two-clock delay . Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved. 1GB, 2GB x72, ECC, DR 168-Pin SDRAM RDIMM Absolute Maximum Ratings

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1GB, 2GB x72, ECC, DR 168-Pin SDRAM RDIMM Features

Synchronous DRAM Module

MT36LSDT12872 1GB MT36LSDT25672 2GB

For the latest data sheet, refer to Micron’s Web site:
• 168-pin, dual in-line memory module DIMM
• PC100- and PC133-compliant
• Registered inputs with one-clock delay
• Phase-lock loop PLL clock driver to reduce loading
• Utilizes 125 MHz and 133 MHz SDRAM
components
• Supports ECC error detection and correction
• 1GB 128 Meg x 72 and 2GB 256 Meg x 72
• Single +3.3V power supply
• Fully synchronous all signals registered on positive
edge of PLL clock
• Internal pipelined operation column address can
be changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge
• Auto refresh mode
• Self refresh mode 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Serial presence-detect SPD
• Gold edge contacts

Table 1:

Timing Parameters CL = CAS READ latency

Module Marking
-13E -133

Clock 133 MHz 133 MHz

Access Time

CL = 2 5.4ns

CL = 3
5.4ns

Setup Time

Hold Time

Figure 1 168-Pin DIMM MO-161

Standard 1.70in. 43.18mm

Low-Profile 1.20in. 30.48mm

Options
• Package 168-pin DIMM standard 168-pin DIMM lead-free
• Frequency/CAS Latency2 133 MHz/CL = 2 133 MHz/CL = 3
• PCB Standard 1.70in 43.18mm Low-Profile 1.20in. 30.48mm

Marking
-13E -133

See note on page 2 See note on page 2

Notes Contact Micron for product availability. Registered mode adds one clock cycle to CL.

Table 2 Address Table

Parameter

Refresh Count Device Banks Device Configuration Row Addressing Column Addressing Module Ranks
8K 4 BA0, BA1 256Mb 64 Meg x 4 8K 2K A11 2 S0#, S2# S1#, S3#
8K 4 BA0, BA1 512Mb 128 Meg x 4 8K 4K A11, A12 2 S0#, S2# S1#, S3#

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
1GB, 2GB x72, ECC, DR 168-Pin SDRAM RDIMM Features

Table 3 Part Numbers

MT36LSDT12872G-13E__ MT36LSDT12872Y-13E__ MT36LSDT12872G-133__ MT36LSDT12872Y-133__ MT36LSDT25672G-13E__ MT36LSDT25672Y-13E__ MT36LSDT25672G-133__ MT36LSDT25672Y-133__
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6 on page

The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQ will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at T0 and the latency is programmed to two clocks, the DQ will start driving after T1 and the data will be valid by T2, as shown in the Figure 5 on page Table 7 on page 12, indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB x72, ECC, DR 168-Pin SDRAM RDIMM Mode Register Definition

Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both read and write bursts.

Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via applies to both read and write bursts when M9 = 1, the programmed burst length applies to read bursts, but write accesses are single-location non burst accesses.

Table 7 CAS Latency Table Registered mode adds one clock cycle to CAS latency

Speed -13E -133

Allowable Operating Clock Frequency MHz

CAS Latency = 2 133 100

CAS Latency = 3 143 133

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB x72, ECC, DR 168-Pin SDRAM RDIMM Commands

Commands

Table 8 provides a quick reference of available commands. This is followed by a written description of each command. For a more detailed description of commands and operations refer to the 256Mb or 512Mb SDRAM component data sheets.

Table 8:

SDRAM Command and DQMB Operation Truth Table CKE is HIGH for all commands shown except Self Refresh

Name Function

COMMAND INHIBIT NOP NO OPERATION NOP ACTIVE Select bank and activate row READ Select bank and column, and start READ burst WRITE Select bank and column, and start WRITE burst TERMINATE PRECHARGE Deactivate row in bank or banks AUTO REFRESH or SELF REFRESH Enter self refresh mode LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z

CS# RAS# CAS# WE# DQMB ADDR DQs Notes

X Bank/Row X

H L/H7 Bank/Col X

L/H7 Bank/Col Valid

Active

Code

X Op-Code X

Active 7

High-Z 7

Notes provide device row address. BA0, BA1 determine which device bank is made active.

A11 1GB or A11, A12 2GB provide device column address A10 HIGH enables the auto precharge feature nonpersistent , while A10 LOW disables the auto precharge feature BA0, BA1 determine which device bank is being read from or written to.

A10 LOW BA0, BA1 determine which device bank is being precharged. A10 HIGH both device banks are precharged and BA0, BA1 are “Don’t Care.”

This command is Auto Refresh if CKE is HIGH, Self Refresh if CKE is LOW. Internal refresh counter controls row addressing all inputs and I/Os are “Don’t Care”
except for CKE. define the op-code written to the Mode Register, and should be driven low. Activates or deactivates the DQs during WRITEs zero-clock delay and READs two-clock
delay .

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB x72, ECC, DR 168-Pin SDRAM RDIMM Absolute Maximum Ratings

More datasheets: KF347 | JW075A1 | JW050A | JW100A | JW150A1 | JW100A1 | JW050A1 | MT36LSDF12872G-133D1 | MT36LSDF12872G-13ED1 | MT36LSDT25672G-13EC2

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Datasheet ID: MT36LSDT12872G-13ED2 648382