MT36LSDF12872Y-133D1
MT36LSDF12872Y-133D1 Datasheet
MT36LSDF6472 512MB MT36LSDF12872 1GB
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MT36LSDF12872Y-133D1 |
MT36LSDF12872Y-133D1 (pdf) |
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| 512MB, 1GB x72, ECC, DR 168-Pin SDRAM RDIMM Features Synchronous DRAM Module MT36LSDF6472 512MB MT36LSDF12872 1GB For the latest data sheet, refer to Micron’s Web site: • 168-pin, dual in-line memory module DIMM • PC133-compliant • Registered inputs with one-clock delay • Phase-lock loop PLL clock driver to reduce loading • Utilizes 133 MHz SDRAM components • Supports ECC error detection and correction • 512MB 64 Meg x 72 and 1GB 128 Meg x 72 • Single +3.3V power supply • Fully synchronous all signals registered on positive edge of PLL clock • Internal pipelined operation column address can be changed every clock cycle • Internal SDRAM banks for hiding row access/ precharge • Programmable burst lengths 1, 2, 4, 8, or full page • Auto precharge, includes concurrent auto precharge • Auto refresh mode • Self refresh mode 64ms, 4,096-cycle refresh 512MB or 8,192-cycle refresh 1GB • LVTTL-compatible inputs and outputs • Serial presence-detect SPD • Gold edge contacts Figure 1 168-Pin DIMM MO-161 Height Standard 1.70in. 43.18mm Options • Package 168-pin DIMM standard 168-pin DIMM lead-free 1 • Standard or low-profile PCB • Frequency/CAS latency2 133 MHz/CL = 23 133 MHz/CL = 3 • PCB height Standard 1.70in. 43.18mm Marking G Y See note on page 2 -13E -133 See page 2 note Table 1: Timing Parameters CL = CAS READ latency Access Time Module Clock Marking Frequency CL = 2 CL = 3 -13E -133 133 MHz 5.4ns 133 MHz 5.4ns Setup Time Hold Time Notes:1. Contact Micron for product availability. Registered mode adds one clock cycle to CL. Available on the 1GB device only. Table 2 Address Table Parameter Refresh count Device banks Device configuration Row addressing Column addressing Module ranks 512MB 4K 4 BA0, BA1 128Mb 32 Meg x 4 4K 2K A11 2 S0#, S2# S1#, S3# 1GB 8K 4 BA0, BA1 256Mb 64 Meg x 4 8K 2K A11 2 S0#, S2# S1#, S3# Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 512MB, 1GB x72, ECC, DR 168-Pin SDRAM RDIMM Features Table 3 Part Numbers Part Number MT36LSDF6472G-133__ MT36LSDF6472Y-133__ MT36LSDF12872G-13E__ MT36LSDF12872Y-13E__ MT36LSDF12872G-133__ MT36LSDF12872Y-133__ Note: The ordering of accesses within a burst is determined by BL, the burst type, and the starting column address, as shown in Table 6 on page CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQ will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at T0 and the latency is programmed to two clocks, the DQ will start driving after T1 and the data will be valid by T2, as shown in Figure Table 7 on page 12 indicates the operating frequencies at which each CL setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed BL applies to both read and write bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB x72, ECC, DR 168-Pin SDRAM RDIMM Commands Write Burst Mode When M9 = 0, BL programmed via applies to both READ and WRITE bursts when M9 = 1, the programmed BL applies to READ bursts, but write accesses are singlelocation nonburst accesses. Table 7: CAS Latency Table Input register adds one clock in registered mode Speed -13E -133 Allowable Operating Clock Frequency MHz CL = 2 133 100 CL = 3 143 133 Commands Table 8, provides a quick reference of available commands. This is followed by a written description of each command. For a more detailed description of commands and operations, refer to 128Mb or 256Mb SDRAM component data sheet. Table 8: SDRAM Command and DQMB Operation Truth Table CKE is HIGH for all commands shown except SELF REFRESH Name Function CS# RAS# CAS# WE# DQMB ADDR DQ Notes COMMAND INHIBIT NOP NO OPERATION NOP ACTIVE Select bank and activate row X Bank/Row X READ Select bank and column, and start READ burst H L/H7 Bank/Col X WRITE Select bank and column, and start WRITE burst L/H7 Bank/Col Valid 2 BURST TERMINATE Active PRECHARGE Deactivate row in bank or banks Code AUTO REFRESH or SELF REFRESH Enter self refresh mode L X 4, 5 LOAD MODE REGISTER X Op-Code X Write enable/output enable Active 7 Write inhibit/output High-Z |
| More datasheets: 35621000029 | 35613150029 | 35612000029 | 35605000029 | 35611000029 | 35602000029 | 35606300029 | 35611250029 | 35611600029 | 35618000029 |
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