MT18VDDF12872HY-40BF1

MT18VDDF12872HY-40BF1 Datasheet

MT18VDDF12872H 1GB

Part	Datasheet
MT18VDDF12872HY-40BF1	MT18VDDF12872HY-40BF1 (pdf)

Related Parts	Information
MT18VDDF12872HG-40BF1	MT18VDDF12872HG-40BF1
MT18VDDF12872HG-40BD1	MT18VDDF12872HG-40BD1

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DDR SDRAM SMALLOUTLINE DIMM 1GB x72, ECC, DR PC3200 200-PIN DDR SODIMM MT18VDDF12872H 1GB For the latest data sheet, please refer to the site: • 200-pin, small-outline, dual in-line memory module SODIMM • Fast data transfer rates PC3200 • Utilizes 400 MT/s DDR SDRAM components • Supports ECC error detection and correction • 1GB 128 Meg x 72 • VDD = VDDQ = +2.6V • VDDSPD = +2.3V to +3.6V • 2.5V I/O SSTL_2 compatible • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • Internal, pipelined double data rate DDR architecture two data accesses per clock cycle • Bidirectional data strobe DQS transmitted/ received with source-synchronous data capture • Differential clock inputs CK and CK# • Four internal device banks for concurrent operation • Programmable burst lengths 2, 4, or 8 • Auto precharge option • Auto Refresh and Self Refresh Modes • 7.8125µs maximum average periodic refresh interval • Serial Presence Detect SPD with EEPROM • Programmable READ CAS latency • Gold edge contacts Figure 1 200-Pin SODIMM MO-224 Height 1.25in. 31.75mm OPTIONS • Package 200-pin SODIMM standard 200-pin SODIMM lead-free 1 • Frequency/CAS Latency2 200 MHz 400 MT/s CL = 3 • PCB Height 1.25in. 31.75mm MARKING -40B NOTE Contact Micron regarding product availability. CL = CAS READ latency. Table 1 Address Table Refresh Count Device Row Addressing Device Bank Addressing Device Configuration Device Column Addressing Module Rank Addressing 8K 4 BA0, BA1 512Mb 64 Meg x 8 2K A11 2 S0#, S1# 2004 Micron Technology, Inc. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 1GB x72, ECC, DR PC3200 200-PIN DDR SODIMM Table 2 Part Numbers and Timing Parameters MODULE CONFIGURATION MODULE MEMORY CLOCK/ LATENCY DENSITY BANDWIDTH DATA RATE CL - tRCD - tRP MT18VDDF12872HG-40B__ 128 Meg x 72 GB/s 5ns/400 MT/s MT18VDDF12872HY-40B__ 128 Meg x 72 GB/s 5ns/400 MT/s 3-3-3-3-3 NOTE: Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2, or 3clocks, as shown in Figure 5, CAS Latency Diagram, on page 1GB x72, ECC, DR PC3200 200-PIN DDR SODIMM If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. The CAS Latency Table indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure 4 Mode Register Definition Diagram BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M14 and M13 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register . Burst Length M2 M1 M0 M3 = 0 0 Reserved 1 0 Reserved 1 0 1 Reserved 1 0 Reserved 1 Reserved Burst Type Sequential Interleaved M6 M5 M4 000 001 010 011 100 101 110 111 CAS Latency Reserved 2 3 Reserved M13 M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - - -- M6-M0 Valid Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. Table 6 Burst Definition Table BURST LENGTH STARTING COLUMN ADDRESS ORDER OF ACCESSES WITHIN A BURST TYPE = TYPE = SEQUENTIAL INTERLEAVED A1 A0 0-1-2-3 0-1-2-3 1-2-3-0 1-0-3-2 2-3-0-1 2-3-0-1 3-0-1-2

PDF Datasheet Preview

DDR SDRAM SMALLOUTLINE DIMM
1GB x72, ECC, DR PC3200 200-PIN DDR SODIMM

MT18VDDF12872H 1GB

For the latest data sheet, please refer to the site:
• 200-pin, small-outline, dual in-line memory module SODIMM
• Fast data transfer rates PC3200
• Utilizes 400 MT/s DDR SDRAM components
• Supports ECC error detection and correction
• 1GB 128 Meg x 72
• VDD = VDDQ = +2.6V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O SSTL_2 compatible
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs center-
aligned with data for WRITEs
• Internal, pipelined double data rate DDR
architecture two data accesses per clock cycle
• Bidirectional data strobe DQS transmitted/
received with source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 7.8125µs maximum average periodic refresh interval
• Serial Presence Detect SPD with EEPROM
• Programmable READ CAS latency
• Gold edge contacts

Figure 1 200-Pin SODIMM MO-224

Height 1.25in. 31.75mm

OPTIONS
• Package 200-pin SODIMM standard 200-pin SODIMM lead-free 1
• Frequency/CAS Latency2 200 MHz 400 MT/s CL = 3
• PCB Height 1.25in. 31.75mm

MARKING
-40B

NOTE Contact Micron regarding product availability. CL = CAS READ latency.

Table 1 Address Table

Refresh Count Device Row Addressing Device Bank Addressing Device Configuration Device Column Addressing Module Rank Addressing
8K 4 BA0, BA1 512Mb 64 Meg x 8 2K A11 2 S0#, S1#
2004 Micron Technology, Inc.

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
1GB x72, ECC, DR PC3200 200-PIN DDR SODIMM

Table 2 Part Numbers and Timing Parameters

MODULE CONFIGURATION MODULE MEMORY CLOCK/

LATENCY

DENSITY

BANDWIDTH DATA RATE

CL - tRCD - tRP

MT18VDDF12872HG-40B__
128 Meg x 72

GB/s
5ns/400 MT/s

MT18VDDF12872HY-40B__
128 Meg x 72

GB/s
5ns/400 MT/s
3-3-3-3-3

NOTE:

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page

Read Latency

The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2, or 3clocks, as shown in Figure 5, CAS Latency Diagram, on page
1GB x72, ECC, DR PC3200 200-PIN DDR SODIMM

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. The CAS Latency Table indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Figure 4 Mode Register Definition Diagram

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M14 and M13 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register .

Burst Length

M2 M1 M0 M3 = 0
0 Reserved
1 0 Reserved
1 0 1 Reserved
1 0 Reserved
1 Reserved

Burst Type

Sequential

Interleaved

M6 M5 M4 000 001 010 011 100 101 110 111

CAS Latency Reserved 2 3 Reserved

M13 M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - - --

M6-M0 Valid

Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc.

Table 6 Burst Definition Table

BURST LENGTH

STARTING COLUMN ADDRESS

ORDER OF ACCESSES WITHIN A BURST

TYPE =

TYPE =

SEQUENTIAL INTERLEAVED

A1 A0
0-1-2-3
0-1-2-3
1-2-3-0
1-0-3-2
2-3-0-1
2-3-0-1
3-0-1-2

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Datasheet ID: MT18VDDF12872HY-40BF1 648352