MT18VDDF12872DG-40BD3

MT18VDDF12872DG-40BD3 Datasheet

MT18VDDF6472 512MB MT18VDDF12872 1GB

Part	Datasheet
MT18VDDF12872DG-40BD3	MT18VDDF12872DG-40BD3 (pdf)

Related Parts	Information
MT18VDDF6472DY-335G2	MT18VDDF6472DY-335G2
MT18VDDF12872DY-335F1	MT18VDDF12872DY-335F1
MT18VDDF12872DG-40BF1	MT18VDDF12872DG-40BF1
MT18VDDF6472DG-265G2	MT18VDDF6472DG-265G2
MT18VDDF6472DG-335G2	MT18VDDF6472DG-335G2

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DDR SDRAM REGISTERED DIMM 512MB, 1GB x72, ECC, SR PC3200 184-PIN DDR SDRAM RDIMM MT18VDDF6472 512MB MT18VDDF12872 1GB For the latest data sheet, please refer to the Web site: • 184-pin, dual in-line memory module DIMM • Fast data transfer rates PC3200 • Utilizes 400 MT/s DDR SDRAM components • Registered inputs with one-clock delay • Phase-lock loop PLL clock driver to reduce loading • Supports ECC error detection and correction • 512MB 64 Meg x 72 and 1GB 128 Meg x 72 • VDD = VDDQ = +2.6V • VDDSPD = +2.3V to +3.6V • 2.5V I/O SSTL_2 compatible • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • Internal, pipelined double data rate DDR architecture two data accesses per clock cycle • Bidirectional data strobe DQS transmitted/received with source-synchronous data capture • Differential clock inputs CK and CK# • Four internal device banks for concurrent operation • Programmable burst lengths 2, 4, or 8 • Auto precharge option • Auto Refresh and Self Refresh modes • 7.8125µs maximum average periodic refresh interval • Serial Presence Detect SPD with EEPROM • Programmable READ CAS latency • Gold edge contacts Figure 1 184-Pin DIMM MO-206 Low-Profile 1.125in. 28.58mm Very Low Profile 0.72in. 18.29mm OPTIONS • Operating Temperature Range Commercial 0°C TA +70°C • Package 184-pin DIMM standard 184-pin DIMM lead-free 1 • Memory Clock, Speed, CAS Latency2 5ns 200 MHz , 400 MT/s, CL = 3 • PCB 1.125in 28.58mm MARKING none G Y -40B NOTE Contact Micron for availability of products. CL = CAS latency registered Mode adds one clock cycle to CL. Table 1 Address Table Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing 512MB 8K 4 BA0, BA1 256Mb 64 Meg x 4 2K A11 1 S0# 8K 4 BA0, BA1 512Mb 128 Meg x 4 4K A11, A12 1 S0# 2004 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 512MB, 1GB x72, ECC, SR PC3200 184-PIN DDR SDRAM RDIMM Table 2 Part Numbers and Timing Parameters MODULE DENSITY CONFIGURATION MODULE MEMORY CLOCK/ LATENCY BANDWIDTH DATA RATE CL - tRCD - tRP MT18VDDF6472G-40B__ MT18VDDF6472Y-40B__ MT18VDDF12872G-40B__ MT18VDDF12872Y-40B__ 512MB 64 Meg x 72 64 Meg x 72 128 Meg x 72 128 Meg x 72 The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 3, or 2 clocks, as shown in Figure 6, CAS Latency Diagram, on page If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. The CAS Latency Table indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used, because unknown operation or incompatibility with future versions may result. Figure 5 Mode Register Definition Diagram BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length * M14 and M13 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register . M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 Burst Length M3 = 0 Reserved 2 4 8 Reserved M3 = 1 Reserved 2 4 8 Reserved Burst Type Sequential Interleaved M6 M5 M4 000 001 010 011 100 101 110 111 CAS Latency Reserved 2 3 Reserved M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - -- M6-M0 Valid Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB x72, ECC, SR PC3200 184-PIN DDR SDRAM RDIMM Table 6 Burst Definition Table BURST LENGTH STARTING COLUMN ADDRESS ORDER OF ACCESSES WITHIN A BURST TYPE = TYPE = SEQUENTIAL INTERLEAVED A1 A0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 A2 A1 A0 0-1-2-3 1-0-3-2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

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DDR SDRAM REGISTERED DIMM
512MB, 1GB x72, ECC, SR PC3200 184-PIN DDR SDRAM RDIMM

MT18VDDF6472 512MB MT18VDDF12872 1GB

For the latest data sheet, please refer to the Web site:
• 184-pin, dual in-line memory module DIMM
• Fast data transfer rates PC3200
• Utilizes 400 MT/s DDR SDRAM components
• Registered inputs with one-clock delay
• Phase-lock loop PLL clock driver to reduce loading
• Supports ECC error detection and correction
• 512MB 64 Meg x 72 and 1GB 128 Meg x 72
• VDD = VDDQ = +2.6V
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O SSTL_2 compatible
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs center-
aligned with data for WRITEs
• Internal, pipelined double data rate DDR
architecture two data accesses per clock cycle
• Bidirectional data strobe DQS transmitted/received
with source-synchronous data capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh modes
• 7.8125µs maximum average periodic refresh
interval
• Serial Presence Detect SPD with EEPROM
• Programmable READ CAS latency
• Gold edge contacts

Figure 1 184-Pin DIMM MO-206

Low-Profile 1.125in. 28.58mm

Very Low Profile 0.72in. 18.29mm

OPTIONS
• Operating Temperature Range Commercial 0°C TA +70°C
• Package 184-pin DIMM standard 184-pin DIMM lead-free 1
• Memory Clock, Speed, CAS Latency2 5ns 200 MHz , 400 MT/s, CL = 3
• PCB 1.125in 28.58mm

MARKING
none G Y
-40B

NOTE Contact Micron for availability of products.

CL = CAS latency registered Mode adds one clock cycle to CL.

Table 1 Address Table

Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing
512MB
8K 4 BA0, BA1 256Mb 64 Meg x 4 2K A11
1 S0#
8K 4 BA0, BA1 512Mb 128 Meg x 4 4K A11, A12
1 S0#
2004 Micron Technology, Inc. All rights reserved.

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
512MB, 1GB x72, ECC, SR PC3200 184-PIN DDR SDRAM RDIMM

Table 2 Part Numbers and Timing Parameters

MODULE DENSITY

CONFIGURATION MODULE MEMORY CLOCK/

LATENCY

BANDWIDTH DATA RATE

CL - tRCD - tRP

MT18VDDF6472G-40B__ MT18VDDF6472Y-40B__ MT18VDDF12872G-40B__ MT18VDDF12872Y-40B__
512MB
64 Meg x 72 64 Meg x 72 128 Meg x 72 128 Meg x 72
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page

Read Latency

The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 3, or 2 clocks, as shown in Figure 6, CAS Latency Diagram, on page

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. The CAS Latency Table indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used, because unknown operation or incompatibility with future versions may result.

Figure 5 Mode Register Definition Diagram

BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register Mx 0* 0* Operating Mode CAS Latency BT Burst Length
* M14 and M13 BA1 and BA0 must be “0, 0” to select the base mode register vs. the extended mode register .

M2 M1 M0 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11

Burst Length

M3 = 0 Reserved
2 4 8 Reserved

M3 = 1 Reserved
2 4 8 Reserved

Burst Type

Sequential

Interleaved

M6 M5 M4 000 001 010 011 100 101 110 111

CAS Latency Reserved 2 3 Reserved

M12 M11 M10 M9 M8 M7 0 00 0 10 - - - - --

M6-M0 Valid

Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2004 Micron Technology, Inc. All rights reserved.
512MB, 1GB x72, ECC, SR PC3200 184-PIN DDR SDRAM RDIMM

Table 6 Burst Definition Table

BURST LENGTH

STARTING COLUMN ADDRESS

ORDER OF ACCESSES WITHIN A BURST

TYPE =

TYPE =

SEQUENTIAL INTERLEAVED

A1 A0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2

A2 A1 A0
0-1-2-3 1-0-3-2-3-0-1 3-2-1-0
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

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Datasheet ID: MT18VDDF12872DG-40BD3 648349