CSPU877ABVG

CSPU877ABVG Datasheet

IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

Part	Datasheet
CSPU877ABVG	CSPU877ABVG (pdf)

Related Parts	Information
CSPU877ANLG	CSPU877ANLG
CSPU877ABVG8	CSPU877ABVG8
CSPU877ANLG8	CSPU877ANLG8

PDF Datasheet Preview
IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER IDTCSPU877A FEATURES: • 1 to 10 differential clock distribution • Optimized for clock distribution in DDR2 Double Data Rate SDRAM applications • Operating frequency 125MHz to 340MHz • Very low skew • Very low jitter • 1.8V AVDD and 1.8V VDDQ • CMOS control signal input • Test mode enables buffers while disabling PLL • Low current power-down mode • Tolerant of Spread Spectrum input clock • Available in 52-Ball VFBGA and 40-pin VFQFPN packages APPLICATIONS: • Meets or exceeds JEDEC standard for registered DDR2 clock driver • Along with SSTU32864/65/66, DDR2 register, provides complete solution for DDR2 DIMMs DESCRIPTION: The CSPU877A is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair CLK, CLK to 10 differential output pairs Y [0:9], Y [0:9] and one differential pair of feedback clock output FBOUT, FBOUT . External feedback pins FBIN, FBIN for synchronization of the outputs to the input reference is provided. OE, OS, and AVDD control the power-down and test mode logic. When AVDD is grounded, the PLL is turned off and bypassed for test mode purposes. When the differential clock inputs CLK, CLK are both at logic low, this device will enter a low power-down mode. In this mode, the receivers are disabled, the PLL is turned off, and the output clock drivers are disabled, resulting in a current consumption device of less than 500uA. The CSPU877A requires no external components and has been optimised for very low phase error, skew, and jitter, while maintaining frequency and duty cycle over the operating voltage and temperature range. The CSPU877A, designed for use in both module assemblies and system motherboard based solutions, provides an optimum high-performance clock source. The CSPU877A is available in Commercial Temperature Range 0°C to +70°C . See Ordering Information for details. FUNCTIONAL BLOCK DIAGRAM OE OS AVDD LD or OE POWER DOWN AND LD, OS, or OE TEST MODE LOGIC PLL BYPASS 10KΩ - 100KΩ FBIN NOTE The Logic Detect LD powers down the device when a logic LOW is applied to both CLK and CLK. The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 1 c 2006 Integrated Device Technology, Inc. Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 FBOUT OCTOBER 2006 DSC-6495/8 IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PIN CONFIGURATION COMMERCIAL TEMPERATURE RANGE 6 Y6 Y7 FBIN FBOUT Y8 5 Y5 GND OS VDDQ OE VDDQ GND Y9 4 Y5 GND NB VDDQ NB VDDQ NB GND Y9 3 Y0 GND NB VDDQ NB VDDQ NB GND Y4 2 Y0 GND VDDQ GND Y4 Y2 CLK AGND AVDD Y3 VFBGA TOP VIEW 52 BALL VFBGA PACKAGE LAYOUT 0.65mm TOP VIEW A BCDE FGH J K E FGH IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PIN CONFIGURATION, CONT. VDDQ VDDQ VDDQ VDDQ AGND AVDD ORDERING INFORMATION IDTCSPU Device Type Package Process COMMERCIAL TEMPERATURE RANGE Blank 0°C to +70°C Commercial BV BVG NL Very Fine Pitch Ball Grid Array Very Fine Pitch Ball Grid Array - Green Thermally Enhanced Plastic Very Fine Pitch Quad Flat Pack No Lead Package VFQFPN - Green 877A 1.8V PLL Differential 1:10 SDRAM Clock Driver CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support:

PDF Datasheet Preview

IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

COMMERCIAL TEMPERATURE RANGE
1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

IDTCSPU877A

FEATURES:
• 1 to 10 differential clock distribution
• Optimized for clock distribution in DDR2 Double Data Rate

SDRAM applications
• Operating frequency 125MHz to 340MHz
• Very low skew
• Very low jitter
• 1.8V AVDD and 1.8V VDDQ
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 52-Ball VFBGA and 40-pin VFQFPN packages

APPLICATIONS:
• Meets or exceeds JEDEC standard for registered DDR2 clock driver
• Along with SSTU32864/65/66, DDR2 register, provides complete solution for DDR2 DIMMs

DESCRIPTION:

The CSPU877A is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair CLK, CLK to 10 differential output pairs Y [0:9], Y [0:9] and one differential pair of feedback clock output FBOUT, FBOUT . External feedback pins FBIN, FBIN for synchronization of the outputs to the input reference is provided. OE, OS, and AVDD control the power-down and test mode logic. When AVDD is grounded, the PLL is turned off and bypassed for test mode purposes. When the differential clock inputs CLK, CLK are both at logic low, this device will enter a low power-down mode. In this mode, the receivers are disabled, the PLL is turned off, and the output clock drivers are disabled, resulting in a current consumption device of less than 500uA.

The CSPU877A requires no external components and has been optimised for very low phase error, skew, and jitter, while maintaining frequency and duty cycle over the operating voltage and temperature range. The CSPU877A, designed for use in both module assemblies and system motherboard based solutions, provides an optimum high-performance clock source.
The CSPU877A is available in Commercial Temperature Range 0°C to +70°C . See Ordering Information for details.

FUNCTIONAL BLOCK DIAGRAM

OE OS

AVDD

LD or OE

POWER

DOWN

AND LD, OS, or OE TEST

MODE LOGIC

PLL BYPASS
10KΩ - 100KΩ

FBIN

NOTE The Logic Detect LD powers down the device when a logic LOW is applied to both CLK and CLK.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE 1
c 2006 Integrated Device Technology, Inc.

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8

FBOUT

OCTOBER 2006

DSC-6495/8

IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

PIN CONFIGURATION

COMMERCIAL TEMPERATURE RANGE
6 Y6 Y7 FBIN FBOUT Y8
5 Y5 GND OS VDDQ OE VDDQ GND Y9 4 Y5 GND NB VDDQ NB VDDQ NB GND Y9
3 Y0 GND NB VDDQ NB VDDQ NB GND Y4 2 Y0 GND VDDQ GND Y4

Y2 CLK AGND AVDD Y3

VFBGA TOP VIEW
52 BALL VFBGA PACKAGE LAYOUT
0.65mm

TOP VIEW

A BCDE FGH J K

E FGH

IDTCSPU877A 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

PIN CONFIGURATION, CONT.

VDDQ

VDDQ

VDDQ

VDDQ

AGND

AVDD
ORDERING INFORMATION

IDTCSPU

Device Type Package Process

COMMERCIAL TEMPERATURE RANGE

Blank 0°C to +70°C Commercial

BV BVG NL

Very Fine Pitch Ball Grid Array Very Fine Pitch Ball Grid Array - Green Thermally Enhanced Plastic Very Fine Pitch Quad Flat Pack No Lead Package VFQFPN - Green
877A 1.8V PLL Differential 1:10 SDRAM Clock Driver

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support:

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CSPU877ABVG Datasheet file may be downloaded here without warranties.

Datasheet ID: CSPU877ABVG 636932