MT18LSDF6472G-133D1
MT18LSDF6472G-133D1 Datasheet
MT18LSDF6472 512MB
| Part | Datasheet |
|---|---|
MT18LSDF6472G-133D1 |
MT18LSDF6472G-133D1 (pdf) |
| PDF Datasheet Preview |
|---|
| 512MB x72, ECC, SR 168-PIN SDRAM RDIMM Features Synchronous DRAM Module MT18LSDF6472 512MB For the latest data sheet, refer to Micron’s Web site: • 168-pin, dual in-line memory module DIMM • PC133-compliant • Registered inputs with one-clock delay • Phase-lock loop PLL clock driver to reduce loading • Utilizes 133 MHz SDRAM components • Supports ECC error detection and correction • 512MB 64 Meg x 72 • Single +3.3V power supply • Fully synchronous all signals registered on positive edge of PLL clock • Internal pipelined operation column address can be changed every clock cycle • Internal SDRAM banks for hiding row access/ precharge • Programmable burst lengths 1, 2, 4, 8, or full page • Auto precharge, includes concurrent auto precharge • Auto refresh mode • Self refresh mode 64ms, 8,192-cycle refresh • LVTTL-compatible inputs and outputs • Serial presence-detect SPD • Gold edge contacts Table 1: Timing Parameters CL = CAS READ latency Module Marking -13E -133 Clock Frequency 133 MHz 133 MHz Access Time CL = 2 5.4ns CL = 3 5.4ns Setup Time Hold Time Figure 1 168-Pin DIMM MO-161 Standard 1.05in. 26.67mm Low-Profile 0.90in. 22.86mm Options • Package 168-pin DIMM standard 168-pin DIMM lead-free • Frequency/CAS Latency2 133 MHz/CL = 2 133 MHz/CL = 3 • PCB Standard 1.05in. 26.67mm Low-Profile 0.9in. 22.86mm 1 Marking -13E -133 See note page 2 See note page 2 Notes:1. Contact Micron for product availability. Registered mode adds one clock cycle to CL. Table 2 Address Table Parameter Refresh count Device banks Device configuration Row addressing Column addressing Module ranks 512MB 8K 4 BA0, BA1 256Mb 64 Meg x 4 8K 2K A11 1 S0#, S2# Micron Technology, Inc., reserves the right to change products or specifications without notice. 2001 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 512MB x72, ECC, SR 168-PIN SDRAM RDIMM Features Table 3 Part Numbers Module Density The ordering of accesses within a burst is determined by BL, the burst type and the starting column address, as shown in Table Accesses within a given burst may be programmed to be either sequential or interleaved this is referred to as the burst type and is selected via bit M3. Figure 4 Mode Register Definition Diagram A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 11 10 9 8 7 Reserved WB Op Mode 6 54 3 CAS Latency BT 2 10 Burst Length Mode Register Mx Program M12, M11, M10 = “0, 0, 0” to ensure compatibility with future devices. Write Burst Mode Programmed Burst Length Single Location Access M6-M0 Operating Mode Defined Standard Operation All other states reserved M2 M1 M0 000 001 010 011 100 101 110 111 Burst Length M3 = 0 1 2 4 8 Reserved Full Page M3 = 1 2 4 8 Reserved Burst Type Sequential Interleaved M6 M5 M4 00 0 01 0 01 1 10 0 10 1 11 0 11 1 CAS Latency Reserved 2 3 Reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. 2001 Micron Technology, Inc. All rights reserved. 512MB x72, ECC, SR 168-PIN SDRAM RDIMM Mode Register Definition Table 6: Burst Definition Table Burst Length Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 8 Full Page n= location 0-y 0-1-0 |
| More datasheets: MX29LV800CBXHI-90G | MX29LV800CTMI-70G | MX29LV800CBTI-55Q | MX29LV800CTXEI-70G | 76650-0074 | DCM27W2S | DDMM36H4PN | DCMAT62S | MK15-501-C-2 | LTST-C195GEKT |
Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MT18LSDF6472G-133D1 Datasheet file may be downloaded here without warranties.