MT18HTF12872FD 1GB MT18HTF25672FD 2GB
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MT18HTF25672FDY-667A5D3 (pdf) |
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MT18HTF25672FDY-667A5E3 |
PDF Datasheet Preview |
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1GB, 2GB x72, DR 240-Pin DDR2 SDRAM FBDIMM Features DDR2 SDRAM FBDIMM MT18HTF12872FD 1GB MT18HTF25672FD 2GB • 240-pin, DDR2 fully buffered dual in-line memory module FBDIMM • Fast data transfer rates PC2-4200, PC2-5300, or PC2-6400 • 1GB 128 Meg x 72 , 2GB 256 Meg x 72 • Gb/s, 4 Gb/s, or Gb/s link transfer rates • High-speed, 1.5V differential, point-to-point link be- tween the host controller and advanced memory buffer AMB • Fault-tolerant can work around a bad bit lane in each direction • High-density scaling with up to eight FBDIMM devicess per channel • SMBus interface to AMB for configuration register access • In-band and out-of-band command access • Deterministic protocol Enables memory controller to optimize DRAM accesses for maximum performance Delivers precise control and repeatable memory behavior • Automatic DDR2 SDRAM bus and channel calibration • Transmitter de-emphasis to reduce ISI • MBIST and IBIST test functions • Transparent mode for DRAM test support • VDD = VDDQ = 1.8V for DRAM • VREF = 0.9V SDRAM command/address termination • VCC = 1.5V for AMB • VDDSPD = for AMB and EEPROM • Serial presence-detect SPD with EEPROM • Gold edge contacts • Dual rank • Supports 95°C operation with 2X refresh Figure 1 240-Pin FBDIMM MO-256 R/C B Module height 30.35mm 1.19in Options • Package 240-pin DIMM Pb-free • Frequency/CAS latency 2.5ns CL = 5 DDR2-800 3.0ns CL = 5 DDR2-667 3.75ns CL = 4 DDR2-533 1 Marking -80E -667 -53E Note Not recommended for new designs. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 1GB, 2GB x72, DR 240-Pin DDR2 SDRAM FBDIMM Features Table 1 Key Timing Parameters Speed Grade -80E -667 -53E Industry Nomenclature PC2-6400 PC2-5300 PC2-4200 Data Rate MT/s CL = 5 CL = 4 CL = 3 tRCD ns 15 tRP ns 15 tRC ns 55 Table 2 Addressing Parameter Refresh count Device bank address Device page size per bank Device configuration Row address Column address Module rank address 1GB 8K 4 BA[1:0] 1KB 512Mb 64 Meg x 8 16K A[13:0] 2K A[9:0] 2 S#[1:0] 2GB 8K 8 BA[2:0] 1KB 1Gb 128 Meg x 8 16K A[13:0] 2K A[9:0] 2 S#[1:0] Table 3 Part Numbers and Timing Parameters 1GB Base device MT47H64M8,1 512Mb DDR2 SDRAM Part Number2 Module Density Configuration |
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