M58WR032KL70ZA6E

M58WR032KL70ZA6E Datasheet

M58WR016KU M58WR016KL M58WR032KU M58WR032KL M58WR064KU M58WR064KL

Part	Datasheet
M58WR032KL70ZA6E	M58WR032KL70ZA6E (pdf)

Related Parts	Information
M58WR032KL70ZA6U TR	M58WR032KL70ZA6U TR
M58WR064KU70ZA6E	M58WR064KU70ZA6E
M58WR032KU70ZA6U TR	M58WR032KU70ZA6U TR
M58WR064KU70ZA6F TR	M58WR064KU70ZA6F TR

PDF Datasheet Preview
M58WR016KU M58WR016KL M58WR032KU M58WR032KL M58WR064KU M58WR064KL 16-, 32- and 64-Mbit x 16, mux I/O, multiple bank, burst V supply flash memories - Supply voltage VDD = V to 2 V for program, erase and read VDDQ = V to 2 V for I/O buffers VPP = 9 V for fast program - Multiplexed address/data - Synchronous/asynchronous read Synchronous burst read mode 66 MHz Random access 70 ns - Synchronous burst read suspend - Programming time 10 µs by word typical for factory program Double/quadruple word program option Enhanced factory program options - Memory blocks Multiple bank memory array 4-Mbit banks Parameter blocks top or bottom location - Dual operations Program erase in one bank while read in others No delay between read and write operations - Block locking All blocks locked at power up Any combination of blocks can be locked WP for block lock-down - Security 128-bit user programmable OTP cells 64-bit unique device number - Common flash interface CFI - 100,000 program/erase cycles per block FBGA VFBGA44 ZA x 5 mm - Electronic signature Manufacturer code 20h Top device code, M58WR016KU 8823h M58WR032KU 8828h M58WR064KU 88C0h Bottom device code, M58WR016KL 8824h M58WR032KL 8829h M58WR064KL 88C1h - RoHS compliant packages available February 2011 1/123 Contents Contents M58WRxxxKU, M58WRxxxKL Description 9 Signal descriptions 17 Address inputs ADQ0-ADQ15, A16-Amax 17 Data input/output ADQ0-ADQ15 17 Chip Enable E 17 Output Enable G 17 Write Enable W 17 Write Protect WP 17 Reset/Power-down RP 18 Latch Enable L 18 Clock K 18 Wait 18 Bus Invert BINV 18 VDD supply voltage 18 VDDQ supply voltage 19 VPP program supply voltage 19 VSS ground 19 VSSQ ground 19 Bus operations 20 Bus read 20 Bus write 20 Address latch 20 Output disable 20 Standby 21 Reset/Power-down 21 Command interface 22 Command interface - standard commands 23 Read Array command 23 Signal names 11 M58WR016KU/L bank architecture 13 M58WR032KU/L bank architecture 13 M58WR064KU/L bank architecture 13 Bus operations 21 Command codes. 22 Standard commands. 29 Electronic signature codes 30 Factory program commands 37 Status register bits 41 X-latency settings 42 Configuration register 45 Burst type definition 46 Dual operations allowed in other banks 53 Dual operations allowed in same bank 54 Dual operation limitations 54 Lock status 57 Program and erase times and endurance cycles 58 Absolute maximum ratings 59 Operating and AC measurement conditions 60 Capacitance 61 DC characteristics - currents 62 DC characteristics - voltages 63 Asynchronous Read AC characteristics 65 Synchronous read AC characteristics. 69 Write AC characteristics, Write Enable controlled 71 Write AC characteristics, Chip Enable controlled 73 Reset and power-up AC characteristics 74 VFBGA44 x 5 mm, 10 x 4 ball array, mm pitch, package mechanical data 76 Ordering information scheme 77 Top boot block addresses, M58WR016KU. 78 Bottom boot block addresses, M58WR016KL 79 Top boot block addresses, M58WR032KU. 81 Bottom boot block addresses, M58WR032KL 83 Top boot block addresses, M58WR064KU. 86 Bottom boot block addresses, M58WR064KL 89 Query structure overview 94 CFI query identification string 95 CFI query system interface information 96 Device geometry definition 97 Primary algorithm-specific extended query table 98 Protection register information 99 Burst read Information 99 Bank and erase block region information 99 Bank and erase block region 1 information 100 Bank and erase block region 2 information 102 Command interface states - modify table, next state 116 Command interface states - modify table, next output 118 6/123 M58WRxxxKU, M58WRxxxKL List of tables Table 7/123 List of figures List of figures M58WRxxxKU, M58WRxxxKL Figure Logic diagram 11 VFBGA44 connections top view through package 12 M58WR016KU/L memory map 14 M58WR032KU/L memory map 15 M58WR064KU/L memory map 16 Protection register memory map. 30 X-latency and data output configuration example. 48 Wait configuration example 49 AC measurement I/O waveform 60 AC measurement load circuit 61 Asynchronous random access read AC waveforms 64 Synchronous burst read AC waveforms 66 Single synchronous read AC waveforms 67 Synchronous burst read suspend AC waveforms. 68 Clock input AC waveform 69 Write AC waveforms, Write Enable controlled 70 Write AC waveforms, Chip Enable controlled 72 Reset and power-up AC waveforms 74 VFBGA44 x 5 mm, 10 x 4 ball array, mm pitch, bottom view package outline 75 Program flowchart and pseudocode 104 Double word program flowchart and pseudocode 105 Quadruple word program flowchart and pseudocode 106 Program suspend and resume flowchart and pseudocode 107 Block erase flowchart and pseudocode 108 Erase suspend and resume flowchart and pseudocode 109 Locking operations flowchart and pseudocode. 110 Protection register program flowchart and pseudocode 111 Enhanced factory program flowchart 112 Quadruple enhanced factory program flowchart. 114 8/123 M58WRxxxKU, M58WRxxxKL The M58WR016KU/L, M58WR032KU/L and M58WR064KU/L are 16-Mbit 1 Mbit x 16 , 32- Mbit 2 Mbits x 16 and 64-Mbit 4 Mbits x 16 non-volatile flash memories, respectively. In the rest of the document, they will be referred to as M58WRxxxKU/L unless otherwise specified. The M58WRxxxKU/L may be erased electrically at block level and programmed in-system on a word-by-word basis using a V to 2 V VDD supply for the circuitry and a V to 2 V VDDQ supply for the input/output pins. An optional 9 V VPP power supply is provided to speed up customer programming. The first 16 address lines are multiplexed with the data input/output signals on the multiplexed address/data bus ADQ0-ADQ15. The remaining address lines, A16-Amax, are the most significant bit addresses. The device features an asymmetrical block architecture - the M58WR016KU/L have an array of 39 blocks, and are divided into 4-Mbit banks. There are 3 banks each containing 8 main blocks of 32 Kwords, and one parameter bank containing 8 parameter blocks of 4 Kwords and 7 main blocks of 32 Kwords. - the M58WR032KU/L have an array of 71 blocks, and are divided into 4-Mbit banks. There are 7 banks each containing 8 main blocks of 32 Kwords, and one parameter bank containing 8 parameter blocks of 4 Kwords and 7 main blocks of 32 Kwords. - the M58WR064KU/L have an array of 135 blocks, and are divided into 4-Mbit banks. There are 15 banks each containing 8 main blocks of 32 Kwords, and one parameter bank containing 8 parameter blocks of 4 Kwords and 7 main blocks of 32 Kwords. The multiple bank architecture allows dual operations while programming or erasing in one bank, read operations are possible in other banks. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architectures are summarized in Tables 2, 3 and 4, and the memory maps are shown in Figures 3, 4 and The parameter blocks are located at the top of the memory address space for the M58WR016KU, M58WR032KU and M58WR064KU, and at the bottom for the M58WR016KL, M58WR032KL and M58WR064KL. Each block can be erased separately. Erase can be suspended to perform program in any other block, and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage VDD. There are two enhanced factory programming commands available to speed up programming. Program and erase commands are written to the command interface of the memory. An internal program/erase controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the status register. The command set required to control the memory is consistent with JEDEC standards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array at power-up the device is configured for asynchronous read. In synchronous burst mode, data is output on each clock cycle at frequencies of up to 66 MHz. The synchronous burst read operation can be suspended and resumed. 9/123 M58WRxxxKU, M58WRxxxKL The device features an automatic standby mode. When the bus is inactive during asynchronous read operations, the device automatically switches to automatic standby mode. In this condition the power consumption is reduced to the standby value IDD4 and the outputs are still driven. The M58WRxxxKU/L features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked down individually, preventing any accidental programming or erasure. There is additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are locked at power- up. The device includes a protection register to increase the protection of a system’s design. The protection register is divided into two segments a 64 bit segment containing a unique device number written by Numonyx, and a 128 bit segment one-time-programmable OTP by the user. The user programmable segment can be permanently protected. Figure 6 Protection register memory map shows the protection register memory map. The memory is available in a VFBGA44 x 5 mm, 10 x 4 active ball array, mm pitch package, and is supplied with all the bits erased set to 10/123 M58WRxxxKU, M58WRxxxKL Figure Logic diagram A16-Amax 1 W E G RP WP L K VDD VDDQ VPP 16 ADQ0-ADQ15 M58WR016KU M58WR016KL M58WR032KU M58WR032KL M58WR064KU M58WR064KL WAIT BINV VSS VSSQ AI13519 Amax is equal to A19 in the M58WR016KU/L, to A20 in the M58WR032KU/L, and to A21 in the M58WR064KU/L. Table Signal names Table Ordering information scheme Example: M58 W R 032 K U 70 ZA 6 E Device type M58 Architecture W = multiple bank, burst mode Operating voltage R = VDD = VDDQ = V to 2 V Density 016 = 16 Mbit x 16 related part numbers have been EOL 032 = 32 Mbit x 16 064 = 64 Mbit x 16 Technology K = 65 nm technology Parameter location U = Top boot, mux I/O L = Bottom boot, mux I/O Speed 70 = 70 ns Package ZA = VFBGA44 x 5 mm, mm pitch Temperature range 6 = to 85 °C Option E = RoHS compliant package, standard packing U = RoHS compliant package, tape and reel packing, 16mm for 32 Mbit only F = RoHS compliant package, tape and reel packing, 16mm for 64 Mbit only Devices are shipped from the factory with the memory content bits erased to For a list of available options speed, package, etc. , daisy chain ordering information, or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you. 77/123 Block address tables Appendix A Block address tables M58WRxxxKU, M58WRxxxKL Table Top boot block addresses, M58WR016KU Bank 1 Size Kword Parameter bank Bank 1 Bank 2 Address range FE000-FEFFF FD000-FDFFF FC000-FCFFF FB000-FBFFF FA000-FAFFF F9000-F9FFF F8000-F8FFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 78/123 M58WRxxxKU, M58WRxxxKL Block address tables Table Top boot block addresses, M58WR016KU continued Bank 1 Size Kword Address range 38000-3FFFF 30000-37FFF 28000-2FFFF Bank 3 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF There are two bank regions Bank Region 1 contains all the banks that are made up of main blocks only Bank Region 2 contains the banks that are made up of the parameter and main blocks parameter bank . Table Bottom boot block addresses, M58WR016KL Bank 1 Size Kword Address range Bank 3 F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF Bank 2 79/123 Block address tables M58WRxxxKU, M58WRxxxKL Table Bottom boot block addresses, M58WR016KL continued Bank 1 Size Kword Added option F 16mm to Table 30 Ordering information scheme. 122/123 M58WRxxxKU, M58WRxxxKL Please Read Carefully INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 11/5/7, Numonyx, B.V., All Rights Reserved. 123/123

PDF Datasheet Preview

M58WR016KU M58WR016KL M58WR032KU M58WR032KL M58WR064KU M58WR064KL
16-, 32- and 64-Mbit x 16, mux I/O, multiple bank, burst V supply flash memories
- Supply voltage VDD = V to 2 V for program, erase and read VDDQ = V to 2 V for I/O buffers VPP = 9 V for fast program
- Multiplexed address/data - Synchronous/asynchronous read

Synchronous burst read mode 66 MHz Random access 70 ns - Synchronous burst read suspend - Programming time 10 µs by word typical for factory program Double/quadruple word program option Enhanced factory program options - Memory blocks Multiple bank memory array 4-Mbit banks Parameter blocks top or bottom location - Dual operations Program erase in one bank while read in
others No delay between read and write
operations - Block locking

All blocks locked at power up Any combination of blocks can be locked WP for block lock-down - Security 128-bit user programmable OTP cells 64-bit unique device number - Common flash interface CFI - 100,000 program/erase cycles per block

FBGA

VFBGA44 ZA x 5 mm
- Electronic signature Manufacturer code 20h Top device code, M58WR016KU 8823h M58WR032KU 8828h M58WR064KU 88C0h Bottom device code, M58WR016KL 8824h M58WR032KL 8829h M58WR064KL 88C1h
- RoHS compliant packages available

February 2011
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Contents

Contents

M58WRxxxKU, M58WRxxxKL

Description 9

Signal descriptions 17

Address inputs ADQ0-ADQ15, A16-Amax 17

Data input/output ADQ0-ADQ15 17

Chip Enable E 17

Output Enable G 17

Write Enable W 17

Write Protect WP 17

Reset/Power-down RP 18

Latch Enable L 18

Clock K 18

Wait 18

Bus Invert BINV 18

VDD supply voltage 18 VDDQ supply voltage 19 VPP program supply voltage 19 VSS ground 19 VSSQ ground 19

Bus operations 20

Bus read 20

Bus write 20

Address latch 20

Output disable 20

Standby 21

Reset/Power-down 21

Command interface 22

Command interface - standard commands 23

Read Array command 23
Signal names 11 M58WR016KU/L bank architecture 13 M58WR032KU/L bank architecture 13 M58WR064KU/L bank architecture 13 Bus operations 21 Command codes. 22 Standard commands. 29 Electronic signature codes 30 Factory program commands 37 Status register bits 41 X-latency settings 42 Configuration register 45 Burst type definition 46 Dual operations allowed in other banks 53 Dual operations allowed in same bank 54 Dual operation limitations 54 Lock status 57 Program and erase times and endurance cycles 58 Absolute maximum ratings 59 Operating and AC measurement conditions 60 Capacitance 61 DC characteristics - currents 62 DC characteristics - voltages 63 Asynchronous Read AC characteristics 65 Synchronous read AC characteristics. 69 Write AC characteristics, Write Enable controlled 71 Write AC characteristics, Chip Enable controlled 73 Reset and power-up AC characteristics 74 VFBGA44 x 5 mm, 10 x 4 ball array, mm pitch, package mechanical data 76 Ordering information scheme 77 Top boot block addresses, M58WR016KU. 78 Bottom boot block addresses, M58WR016KL 79 Top boot block addresses, M58WR032KU. 81 Bottom boot block addresses, M58WR032KL 83 Top boot block addresses, M58WR064KU. 86 Bottom boot block addresses, M58WR064KL 89 Query structure overview 94 CFI query identification string 95 CFI query system interface information 96 Device geometry definition 97 Primary algorithm-specific extended query table 98 Protection register information 99 Burst read Information 99 Bank and erase block region information 99 Bank and erase block region 1 information 100 Bank and erase block region 2 information 102 Command interface states - modify table, next state 116 Command interface states - modify table, next output 118
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M58WRxxxKU, M58WRxxxKL

List of tables

Table
7/123

List of figures

List of figures

M58WRxxxKU, M58WRxxxKL

Figure

Logic diagram 11 VFBGA44 connections top view through package 12 M58WR016KU/L memory map 14 M58WR032KU/L memory map 15 M58WR064KU/L memory map 16 Protection register memory map. 30 X-latency and data output configuration example. 48 Wait configuration example 49 AC measurement I/O waveform 60 AC measurement load circuit 61 Asynchronous random access read AC waveforms 64 Synchronous burst read AC waveforms 66 Single synchronous read AC waveforms 67 Synchronous burst read suspend AC waveforms. 68 Clock input AC waveform 69 Write AC waveforms, Write Enable controlled 70 Write AC waveforms, Chip Enable controlled 72 Reset and power-up AC waveforms 74 VFBGA44 x 5 mm, 10 x 4 ball array, mm pitch, bottom view package outline 75 Program flowchart and pseudocode 104 Double word program flowchart and pseudocode 105 Quadruple word program flowchart and pseudocode 106 Program suspend and resume flowchart and pseudocode 107 Block erase flowchart and pseudocode 108 Erase suspend and resume flowchart and pseudocode 109 Locking operations flowchart and pseudocode. 110 Protection register program flowchart and pseudocode 111 Enhanced factory program flowchart 112 Quadruple enhanced factory program flowchart. 114
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M58WRxxxKU, M58WRxxxKL

The M58WR016KU/L, M58WR032KU/L and M58WR064KU/L are 16-Mbit 1 Mbit x 16 , 32- Mbit 2 Mbits x 16 and 64-Mbit 4 Mbits x 16 non-volatile flash memories, respectively. In the rest of the document, they will be referred to as M58WRxxxKU/L unless otherwise specified.

The M58WRxxxKU/L may be erased electrically at block level and programmed in-system on a word-by-word basis using a V to 2 V VDD supply for the circuitry and a V to 2 V VDDQ supply for the input/output pins. An optional 9 V VPP power supply is provided to speed up customer programming.

The first 16 address lines are multiplexed with the data input/output signals on the multiplexed address/data bus ADQ0-ADQ15. The remaining address lines, A16-Amax, are the most significant bit addresses.

The device features an asymmetrical block architecture - the M58WR016KU/L have an array of 39 blocks, and are divided into 4-Mbit banks.

There are 3 banks each containing 8 main blocks of 32 Kwords, and one parameter bank containing 8 parameter blocks of 4 Kwords and 7 main blocks of 32 Kwords. - the M58WR032KU/L have an array of 71 blocks, and are divided into 4-Mbit banks. There are 7 banks each containing 8 main blocks of 32 Kwords, and one parameter bank containing 8 parameter blocks of 4 Kwords and 7 main blocks of 32 Kwords. - the M58WR064KU/L have an array of 135 blocks, and are divided into 4-Mbit banks. There are 15 banks each containing 8 main blocks of 32 Kwords, and one parameter bank containing 8 parameter blocks of 4 Kwords and 7 main blocks of 32 Kwords.

The multiple bank architecture allows dual operations while programming or erasing in one bank, read operations are possible in other banks. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architectures are summarized in Tables 2, 3 and 4, and the memory maps are shown in Figures 3, 4 and The parameter blocks are located at the top of the memory address space for the M58WR016KU, M58WR032KU and M58WR064KU, and at the bottom for the M58WR016KL, M58WR032KL and M58WR064KL.

Each block can be erased separately. Erase can be suspended to perform program in any other block, and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage VDD. There are two enhanced factory programming commands available to speed up programming.

Program and erase commands are written to the command interface of the memory. An internal program/erase controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the status register. The command set required to control the memory is consistent with JEDEC standards.

The device supports synchronous burst read and asynchronous read from all blocks of the memory array at power-up the device is configured for asynchronous read. In synchronous burst mode, data is output on each clock cycle at frequencies of up to 66 MHz. The synchronous burst read operation can be suspended and resumed.
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M58WRxxxKU, M58WRxxxKL

The device features an automatic standby mode. When the bus is inactive during asynchronous read operations, the device automatically switches to automatic standby mode. In this condition the power consumption is reduced to the standby value IDD4 and the outputs are still driven.

The M58WRxxxKU/L features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked down individually, preventing any accidental programming or erasure. There is additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are locked at power- up.

The device includes a protection register to increase the protection of a system’s design. The protection register is divided into two segments a 64 bit segment containing a unique device number written by Numonyx, and a 128 bit segment one-time-programmable OTP by the user. The user programmable segment can be permanently protected. Figure 6 Protection register memory map shows the protection register memory map.

The memory is available in a VFBGA44 x 5 mm, 10 x 4 active ball array, mm pitch package, and is supplied with all the bits erased set to
10/123

M58WRxxxKU, M58WRxxxKL

Figure Logic diagram

A16-Amax 1 W E G RP

WP L K

VDD VDDQ VPP
16 ADQ0-ADQ15

M58WR016KU M58WR016KL M58WR032KU M58WR032KL M58WR064KU M58WR064KL

WAIT BINV

VSS VSSQ

AI13519

Amax is equal to A19 in the M58WR016KU/L, to A20 in the M58WR032KU/L, and to A21 in the M58WR064KU/L.

Table Signal names
Table Ordering information scheme

Example:

M58 W R 032 K U 70 ZA 6 E

Device type M58

Architecture W = multiple bank, burst mode

Operating voltage R = VDD = VDDQ = V to 2 V

Density 016 = 16 Mbit x 16 related part numbers have been EOL 032 = 32 Mbit x 16 064 = 64 Mbit x 16

Technology K = 65 nm technology

Parameter location U = Top boot, mux I/O L = Bottom boot, mux I/O

Speed 70 = 70 ns

Package ZA = VFBGA44 x 5 mm, mm pitch

Temperature range 6 = to 85 °C

Option E = RoHS compliant package, standard packing U = RoHS compliant package, tape and reel packing, 16mm for 32 Mbit only F = RoHS compliant package, tape and reel packing, 16mm for 64 Mbit only

Devices are shipped from the factory with the memory content bits erased to
For a list of available options speed, package, etc. , daisy chain ordering information, or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you.
77/123

Block address tables

Appendix A Block address tables

M58WRxxxKU, M58WRxxxKL

Table Top boot block addresses, M58WR016KU

Bank 1

Size Kword

Parameter bank

Bank 1

Bank 2

Address range FE000-FEFFF FD000-FDFFF FC000-FCFFF FB000-FBFFF FA000-FAFFF F9000-F9FFF F8000-F8FFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF
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M58WRxxxKU, M58WRxxxKL

Block address tables

Table Top boot block addresses, M58WR016KU continued

Bank 1

Size Kword

Address range
38000-3FFFF
30000-37FFF
28000-2FFFF

Bank 3
20000-27FFF
18000-1FFFF
10000-17FFF
08000-0FFFF

There are two bank regions Bank Region 1 contains all the banks that are made up of main blocks only Bank Region 2 contains the banks that are made up of the parameter and main blocks parameter bank .

Table Bottom boot block addresses, M58WR016KL

Bank 1

Size Kword

Address range

Bank 3

F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF

Bank 2
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Block address tables

M58WRxxxKU, M58WRxxxKL

Table Bottom boot block addresses, M58WR016KL continued

Bank 1

Size Kword
Added option F 16mm to Table 30 Ordering information scheme.
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Please Read Carefully INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY

WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others. Copyright 11/5/7, Numonyx, B.V., All Rights Reserved.
123/123

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived M58WR032KL70ZA6E Datasheet file may be downloaded here without warranties.

Datasheet ID: M58WR032KL70ZA6E 648302