MPC180LMB

MPC180LMB Datasheet

MPC180LMB Security Processor User’s Manual

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MPC180LMB	MPC180LMB (pdf)

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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MPC180LMB Security Processor User’s Manual TO CHANGE WITHOUT NOTICE For More Information On This Product, Go to: Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. DigitalDNA, PowerQUICC, and PowerQUICC II are trademarks of Motorola, Inc. The PowerPC name, the PowerPC logotype, and PowerPC 603e are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation. I2C is a registered trademark of Philips Semiconductors This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. Information in this document is provided solely to enable system and software implementers to use Motorola security processors. There are no express or implied copyright licenses granted hereunder to design or fabricate Motorola security processors integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Motorola Literature Distribution Centers USA/EUROPE Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 Tel. 1-800-441-2447 or 1-303-675-2140/ JAPAN Nippon Motorola Ltd SPD, Strategic Planning Office 4-32-1, Nishi-Gotanda Shinagawa-ku, Tokyo 141, Japan Tel. 81-35487-8488 ASIA/PACIFC Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong Tel. 852-26629298 Technical Information Motorola Inc. SPS Customer Support Center 1-800-521-6274 electronic mail address Document Comments FAX 512 933-3873, Attn Security Processor Applications Engineering. World Wide Web Addresses: Motorola Inc. All rights reserved. For More Information On This Product, Go to: Freescale Semiconductor, Inc. Overview Signal Descriptions External Bus Interface and Memory Map Data Encryption Standard Execution Unit Arc Four Execution Unit Message Digest Execution Unit Public Key Execution Unit Random Number Generator Freescale Semiconductor, Inc... Glossary of Terms and Abbreviations GLO TO CHANGE WITHOUT NOTICE For More Information On This Product, Go to: Freescale Semiconductor, Inc. Overview Signal Descriptions External Bus Interface and Memory Map Data Encryption Standard Execution Unit Arc Four Execution Unit Message Digest Authentication Unit Public Key Execution Unit Random Number Generator Freescale Semiconductor, Inc... GLO Glossary of Terms and Abbreviations TO CHANGE WITHOUT NOTICE For More Information On This Product, Go to: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Paragraph Number CONTENTS Most of these registers are read and write, however some have special permissions. See Table 3-1 for more information. The 12-bit MPC180 address of each register is shown next to the register name. All registers are assumed to be 32 bits wide however, registers that contain fewer bits will return 0 or a known value on unused bits for that bus transaction only. Many registers contain multiple 32-bit words. If so, the number of words in the register set is shown in brackets after the name. Individual execution unit chapters describe how to use these registers, the bit assignments, and bit ordering. Address Map Table 3-1 lists the addresses for all registers in each execution unit. The 12-bit MPC180 address bus value is shown along with a 32-bit host processor address bus value. Table 32-Bit System Address Map MPC180 12-Bit Address 0x000 0x001 0x002 0x003 0x004 0x005 0x006 0x007 0x008 0x009 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F 0x010 0x011 0x012 0x013 0x014 0x015 0x016 0x017 Processor 32-Bit Address Register MDEU: 0x0000_0000 0x0000_0004 0x0000_0008 0x0000_000C 0x0000_0010 0x0000_0014 0x0000_0018 0x0000_001C 0x0000_0020 0x0000_0024 0x0000_0028 0x0000_002C 0x0000_0030 0x0000_0034 0x0000_0038 0x0000_003C 0x0000_0040 0x0000_0044 0x0000_0048 0x0000_004C 0x0000_0050 0x0000_0054 0x0000_0058 0x0000_005C Message buffer MB0 Message buffer MB1 Message buffer MB2 Message buffer MB3 Message buffer MB4 Message buffer MB5 Message buffer MB6 Message buffer MB7 Message buffer MB8 Message buffer MB9 Message buffer MB10 Message buffer MB11 Message buffer MB12 Message buffer MB13 Message buffer MB14 Message buffer MB15 Message digest MA Message digest MB Message digest MC Message digest MD Message digest ME Control MCR Status MSR Clear interrupt MCLRIRQ Type W R/W R/W R/W R/W R/W R/W R/W MPC180LMB Security Processor User’s Manual For More Information On This Product, Go to: Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Address Map Table 32-Bit System Address Map Continued MPC180 12-Bit Address 0x018 0x200 0x201 0x202 0x203 0x204 0x205 0x206 0x207 0x208 0x209 0x20A 0x20B 0x20C 0x20D 0X20E 0x400 0x401 0x402 0x403 0x404 0x405 0x406 0x407 0x408 0x409 0x40A 0x40B 0x410 0x414 0x418 0x50C Processor 32-Bit Address Register 0x0000_0060 Version MID DEU: 0x0000_0800 0x0000_0804 0x0000_0808 0x0000_080C 0x0000_0810 0x0000_0814 0x0000_0818 0x0000_081C 0x0000_0820 0x0000_0824 0x0000_0828 0x0000_082C 0x0000_0830 0x0000_0834 0x0000_0838 Control DCR Status DSR Key1_R Key1_L Key2_R Key2_L Key3_R Key3_L IV_R IV_L DATAIN_R DATAIN_L DATAOUT_R DATAOUT_L DCFG AFEU: 0x0000_1000 0x0000_1004 0x0000_1008 0x0000_100C 0x0000_1010 0x0000_1014 0x0000_1018 0x0000_101C 0x0000_1020 0x0000_1024 0x0000_1028 0x0000_102C 0x0000_1040 0x0000_1050 0x0000_1060 0x0000_1430 Control Status Clear interrupt Key Length Key Low Key Lower-Middle Key Upper-Middle Key Upper Message Byte Double Word Plaintext-in Ciphertext-out S-box I/J SBox [0] SBox [1] SBox [2] SBox [63] Type R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R W R/W R/W R/W R/W R/W Chapter External Bus Interface and Memory Map For More Information On This Product, Big-endian. A byte-ordering method in memory where the address n of a word corresponds to the byte. In an addressed memory word, the bytes are ordered left to right 0, 1, 2, 3, with 0 being the byte. See Little-endian. Block cipher. A symmetric cipher which encrypts a message by breaking it down into blocks and encrypting each block. Block cipher based MAC. MAC that is performed by using a block cipher as a keyed compression function. Buffer count registers. Contain the number of 32-bit words to be transferred to/from an execution unit for a given operation. For More Information On This Product, Go to: Glossary-1 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Bulk Data Encryption. The process of converting plaintext to ciphertext. Refers to encryption operations other than key exchange and hashing. Burst. A multiple-word data transfer whose total size is typically equal to a cache block. In MPC8260 mode, eight words. CBC. Cipher block chaining. Mode of DES encryption which uses IVs which are altered by the context of the preceding block. Chinese Remainder Theorem. Mathematical theorem based on the congruence of greatest common denominator and least common multiple. CRT is used in support of asymmetric key exchange. Ciphertext. Text any information which has been encrypted so as to render it unreadable by parties without the proper decryption keys. Clear. To cause a bit or bit to register a value of zero. See also Set. Context. Information associated with an encryption/decryption operation. Typical context constituents are session keys, initialization vectors, and security associations. Context memory. Local or system memory reserved for storage of security context information. Context switching. The act of changing parameters, such as Keys and IVs, between the end of the current packet and the next. Cryptography. The art and science of using mathematics to secure information and create a high degree of trust in the electronic realm. See also public key, secret key, symmetric-key, and threshold cryptography. Crypto-analysis. The art and science of code breaking. Develops methods of attacking encryption algorithms to recover plaintext in less time that brute force attacks. Decryption. The process of converting ciphertext to plaintext. Also referred to as decoding. DES. Data encryption standard. A block cipher that uses a 56-bit key to encrypt 64-bit blocks of data, one block at a time. 3DES. Triple DES. Encryption operation which permutes 64 bit blocks of plaintext with 64 bit keys three times. Triple DES is exponentially stronger than single DES encryption. Glossary-2 MPC180LMB Security Processor User’s Manual For More Information On This Product, Go to: Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. key exchange. A key exchange protocol allowing the participants to agree on a key over an insecure channel. Digest. Commonly used to refer to the output of a hash function, e.g. message digest refers to the hash of a message. Digital signature. The encryption of a message digest with a private key. DMA. Direct Memory Access. DSA. Digital Signature Algorithm. DSA is a public-key method based on the discrete logarithm problem. Proposed by NIST. DSS. Digital signature standard proposed by NIST. EBI. External Bus Interface. A functional block in the MPC180 that mediates between internal and external signals. ECB. Electronic code book. A mode of DES which uses initialization vectors that are not by processing of the previous packet. Little-endian. A byte-ordering method in memory where the address n of a word corresponds to the byte. In an addressed memory word, the bytes are ordered left to right 3, 2, 1, 0, with 3 being the byte. See Big-endian. Masking. Hiding internal interrupts and signals from the external interface via control registers. MD4. Message Digest Hashing algorithm developed by Rivest which processes a series of 512-bit message blocks and produces a single 128-bit Hash representing the original message. MD5. Message Digest Hashing algorithm developed by Rivest which pads if necessary the message to be hashed to create a 512 bit block. This block is compressed by XOR-ing two inputs the 512-bit message block, and a 128-bit key. Stronger than MD. MDEU. Message Digest Execution Unit. A device or silicon block which accelerates the hashing functions associated with message authentication. Memory-mapped accesses. Accesses whose addresses use the page or block address translation mechanisms provided by the MMU and that occur externally with the bus protocol for memory. Message Authentication Code MAC . A MAC is a function that takes a variable length input and a key to produce a output. See also hash-based MAC, stream-cipher based MAC, and block-cipher based MAC. Message Digest. The result of applying a hash function to a message. Modular arithmetic. A form of arithmetic where integers are considered equal if they leave the same remainder when divided by the modulus. Modulus. The integer used to divide out by in modular arithmetic. For More Information On This Product, Go to: Glossary-5 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. bit msb . The highest-order bit in an address, registers, data element, or instruction encoding. byte MSB . The highest-order byte in an address, registers, data element, or instruction encoding. NIST. National Institute of Standards. U.S. Government Agency responsible for defining and certifying standards. Padding. Extra bits concatenated with a key, password, or plaintext. Physical memory. The actual memory that can be accessed through the system’s memory bus. Pipelining. A technique that breaks operations, such as instruction processing or bus transactions, into smaller distinct stages or tenures respectively so that a subsequent operation can begin before the previous one has completed. PKEU. Public Key Execution Unit. A device or silicon block which accelerates the mathematical algorithms associated with public key exchange. Typically uses the RSA or algorithms. PKI. Public Key Infrastructure. PKIs are designed to solve the key management problem. Plaintext. The data to be encrypted. Private key. In public-key cryptography, this key is the secret key. It is primarily used for decryption but is also used for encryption with digital signatures. PRNG. Pseudo Random Number Generator. A device or silicon block which produces numbers or bits which are related to preceding and following numbers or bits, however this relationship is nearly imperceptible. Only predictable in a theoretical sense. Public key. In public-key cryptography this key is made public to all, it is primarily used for encryption but can be used for verifying signatures. Public-key cryptography. Cryptography based on methods involving a public key and a private key. Glossary-6 MPC180LMB Security Processor User’s Manual For More Information On This Product, Go to: Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. RC4 algorithm. Byte oriented, therefore a byte of plaintext is encrypted with a permuted substitution box S-box key to produce a byte of ciphertext. The key is variable length and supports in byte increments key lengths from 40 bits to 128 bits, providing a wide range of strengths. RNG. Random Number Generator. A device or silicon block which produces numbers or bits which are non-deterministically related to preceding and following numbers or bits, thoroughly unpredictable. RSA algorithm. A public-key cryptosystem based on the factoring problem. RSA stands for Rivest, Shamir and Adleman, the developers of the RSA public-key cryptosystem.

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MPC180LMB Security Processor User’s Manual

TO CHANGE WITHOUT NOTICE For More Information On This Product, Go to:

Freescale Semiconductor, Inc...

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DigitalDNA, PowerQUICC, and PowerQUICC II are trademarks of Motorola, Inc. The PowerPC name, the PowerPC logotype, and PowerPC 603e are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation. I2C is a registered trademark of Philips Semiconductors

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. Information in this document is provided solely to enable system and software implementers to use Motorola security processors. There are no express or implied copyright licenses granted hereunder to design or fabricate Motorola security processors integrated circuits or integrated circuits based on the information in this document.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Motorola Literature Distribution Centers USA/EUROPE Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 Tel. 1-800-441-2447 or 1-303-675-2140/ JAPAN Nippon Motorola Ltd SPD, Strategic Planning Office 4-32-1, Nishi-Gotanda Shinagawa-ku, Tokyo 141, Japan Tel. 81-35487-8488 ASIA/PACIFC Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong Tel. 852-26629298

Technical Information Motorola Inc. SPS Customer Support Center 1-800-521-6274 electronic mail address Document Comments FAX 512 933-3873, Attn Security Processor Applications Engineering. World Wide Web Addresses:

Motorola Inc. All rights reserved.

For More Information On This Product, Go to:

Freescale Semiconductor, Inc.

Overview

Signal Descriptions

External Bus Interface and Memory Map

Data Encryption Standard Execution Unit

Arc Four Execution Unit

Message Digest Execution Unit

Public Key Execution Unit

Random Number Generator

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Glossary of Terms and Abbreviations GLO

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Overview

Signal Descriptions

External Bus Interface and Memory Map

Data Encryption Standard Execution Unit

Arc Four Execution Unit

Message Digest Authentication Unit

Public Key Execution Unit

Random Number Generator

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GLO Glossary of Terms and Abbreviations

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Paragraph Number

CONTENTS
Most of these registers are read and write, however some have special permissions. See Table 3-1 for more information. The 12-bit MPC180 address of each register is shown next to the register name. All registers are assumed to be 32 bits wide however, registers that contain fewer bits will return 0 or a known value on unused bits for that bus transaction only. Many registers contain multiple 32-bit words. If so, the number of words in the register set is shown in brackets after the name. Individual execution unit chapters describe how to use these registers, the bit assignments, and bit ordering.

Address Map

Table 3-1 lists the addresses for all registers in each execution unit. The 12-bit MPC180 address bus value is shown along with a 32-bit host processor address bus value.

Table 32-Bit System Address Map

MPC180 12-Bit Address
0x000 0x001 0x002 0x003 0x004 0x005 0x006 0x007 0x008 0x009 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F 0x010 0x011 0x012 0x013 0x014 0x015 0x016 0x017

Processor 32-Bit Address

Register

MDEU:
0x0000_0000 0x0000_0004 0x0000_0008 0x0000_000C 0x0000_0010 0x0000_0014 0x0000_0018 0x0000_001C 0x0000_0020 0x0000_0024 0x0000_0028 0x0000_002C 0x0000_0030 0x0000_0034 0x0000_0038 0x0000_003C 0x0000_0040 0x0000_0044 0x0000_0048 0x0000_004C 0x0000_0050 0x0000_0054 0x0000_0058 0x0000_005C

Message buffer MB0 Message buffer MB1 Message buffer MB2 Message buffer MB3 Message buffer MB4 Message buffer MB5 Message buffer MB6 Message buffer MB7 Message buffer MB8 Message buffer MB9 Message buffer MB10 Message buffer MB11 Message buffer MB12 Message buffer MB13 Message buffer MB14 Message buffer MB15 Message digest MA Message digest MB Message digest MC Message digest MD Message digest ME Control MCR Status MSR Clear interrupt MCLRIRQ

Type

W R/W R/W R/W R/W R/W R/W R/W

MPC180LMB Security Processor User’s Manual

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Address Map

Table 32-Bit System Address Map Continued

MPC180 12-Bit Address 0x018
0x200 0x201 0x202 0x203 0x204 0x205 0x206 0x207 0x208 0x209 0x20A 0x20B 0x20C 0x20D 0X20E
0x400 0x401 0x402 0x403 0x404 0x405 0x406 0x407 0x408 0x409 0x40A 0x40B 0x410 0x414 0x418
0x50C

Processor 32-Bit Address

Register
0x0000_0060

Version MID

DEU:
0x0000_0800 0x0000_0804 0x0000_0808 0x0000_080C 0x0000_0810 0x0000_0814 0x0000_0818 0x0000_081C 0x0000_0820 0x0000_0824 0x0000_0828 0x0000_082C 0x0000_0830 0x0000_0834 0x0000_0838

Control DCR Status DSR Key1_R Key1_L Key2_R Key2_L Key3_R Key3_L IV_R IV_L DATAIN_R DATAIN_L DATAOUT_R DATAOUT_L DCFG

AFEU:
0x0000_1000 0x0000_1004 0x0000_1008 0x0000_100C 0x0000_1010 0x0000_1014 0x0000_1018 0x0000_101C 0x0000_1020 0x0000_1024 0x0000_1028 0x0000_102C 0x0000_1040 0x0000_1050 0x0000_1060
0x0000_1430

Control Status Clear interrupt Key Length Key Low Key Lower-Middle Key Upper-Middle Key Upper Message Byte Double Word Plaintext-in Ciphertext-out S-box I/J SBox [0] SBox [1] SBox [2] SBox [63]

Type R

R/W R

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

W R W R/W R/W R/W R/W R/W

Chapter External Bus Interface and Memory Map

For More Information On This Product,
Big-endian. A byte-ordering method in memory where the address n of a
word corresponds to the byte. In an addressed
memory word, the bytes are ordered left to right 0, 1, 2, 3, with 0
being the byte. See Little-endian.

Block cipher. A symmetric cipher which encrypts a message by breaking it down into blocks and encrypting each block.

Block cipher based MAC. MAC that is performed by using a block cipher as a keyed compression function.

Buffer count registers. Contain the number of 32-bit words to be transferred to/from an execution unit for a given operation.

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Glossary-1

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Bulk Data Encryption. The process of converting plaintext to ciphertext. Refers to encryption operations other than key exchange and hashing.

Burst. A multiple-word data transfer whose total size is typically equal to a cache block. In MPC8260 mode, eight words.

CBC. Cipher block chaining. Mode of DES encryption which uses IVs which
are altered by the context of the preceding block.

Chinese Remainder Theorem. Mathematical theorem based on the congruence of greatest common denominator and least common multiple. CRT is used in support of asymmetric key exchange.

Ciphertext. Text any information which has been encrypted so as to render it unreadable by parties without the proper decryption keys.

Clear. To cause a bit or bit to register a value of zero. See also Set.

Context. Information associated with an encryption/decryption operation. Typical context constituents are session keys, initialization vectors, and security associations.

Context memory. Local or system memory reserved for storage of security context information.

Context switching. The act of changing parameters, such as Keys and IVs, between the end of the current packet and the next.

Cryptography. The art and science of using mathematics to secure information and create a high degree of trust in the electronic realm. See also public key, secret key, symmetric-key, and threshold cryptography.

Crypto-analysis. The art and science of code breaking. Develops methods of attacking encryption algorithms to recover plaintext in less time that brute force attacks.

Decryption. The process of converting ciphertext to plaintext. Also referred
to as decoding.

DES. Data encryption standard. A block cipher that uses a 56-bit key to encrypt 64-bit blocks of data, one block at a time.
3DES. Triple DES. Encryption operation which permutes 64 bit blocks of plaintext with 64 bit keys three times. Triple DES is exponentially stronger than single DES encryption.

Glossary-2

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key exchange. A key exchange protocol allowing the participants to agree on a key over an insecure channel.

Digest. Commonly used to refer to the output of a hash function, e.g. message digest refers to the hash of a message.

Digital signature. The encryption of a message digest with a private key.

DMA. Direct Memory Access.

DSA. Digital Signature Algorithm. DSA is a public-key method based on the discrete logarithm problem. Proposed by NIST.

DSS. Digital signature standard proposed by NIST.

EBI. External Bus Interface. A functional block in the MPC180 that mediates
between internal and external signals.

ECB. Electronic code book. A mode of DES which uses initialization vectors that are not by processing of the previous packet.
Little-endian. A byte-ordering method in memory where the address n of a word corresponds to the byte. In an addressed memory word, the bytes are ordered left to right 3, 2, 1, 0, with 3 being the byte. See Big-endian.

Masking. Hiding internal interrupts and signals from the external interface
via control registers.

MD4. Message Digest Hashing algorithm developed by Rivest which processes a series of 512-bit message blocks and produces a single 128-bit Hash representing the original message.

MD5. Message Digest Hashing algorithm developed by Rivest which pads if necessary the message to be hashed to create a 512 bit block. This block is compressed by XOR-ing two inputs the 512-bit message block, and a 128-bit key. Stronger than MD.

MDEU. Message Digest Execution Unit. A device or silicon block which accelerates the hashing functions associated with message authentication.

Memory-mapped accesses. Accesses whose addresses use the page or block address translation mechanisms provided by the MMU and that occur externally with the bus protocol for memory.

Message Authentication Code MAC . A MAC is a function that takes a variable length input and a key to produce a output. See also hash-based MAC, stream-cipher based MAC, and block-cipher based MAC.

Message Digest. The result of applying a hash function to a message.

Modular arithmetic. A form of arithmetic where integers are considered equal if they leave the same remainder when divided by the modulus.

Modulus. The integer used to divide out by in modular arithmetic.

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Glossary-5

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bit msb . The highest-order bit in an address, registers, data element, or instruction encoding.
byte MSB . The highest-order byte in an address, registers, data element, or instruction encoding.

NIST. National Institute of Standards. U.S. Government Agency responsible
for defining and certifying standards.

Padding. Extra bits concatenated with a key, password, or plaintext.

Physical memory. The actual memory that can be accessed through the system’s memory bus.

Pipelining. A technique that breaks operations, such as instruction processing or bus transactions, into smaller distinct stages or tenures respectively so that a subsequent operation can begin before the previous one has completed.

PKEU. Public Key Execution Unit. A device or silicon block which accelerates the mathematical algorithms associated with public key exchange. Typically uses the RSA or algorithms.

PKI. Public Key Infrastructure. PKIs are designed to solve the key management problem.

Plaintext. The data to be encrypted.

Private key. In public-key cryptography, this key is the secret key. It is primarily used for decryption but is also used for encryption with digital signatures.

PRNG. Pseudo Random Number Generator. A device or silicon block which produces numbers or bits which are related to preceding and following numbers or bits, however this relationship is nearly imperceptible. Only predictable in a theoretical sense.

Public key. In public-key cryptography this key is made public to all, it is primarily used for encryption but can be used for verifying signatures.

Public-key cryptography. Cryptography based on methods involving a public key and a private key.

Glossary-6

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RC4 algorithm. Byte oriented, therefore a byte of plaintext is encrypted with
a permuted substitution box S-box key to produce a byte of
ciphertext. The key is variable length and supports in byte
increments key lengths from 40 bits to 128 bits, providing a wide
range of strengths.

RNG. Random Number Generator. A device or silicon block which produces numbers or bits which are non-deterministically related to preceding and following numbers or bits, thoroughly unpredictable.

RSA algorithm. A public-key cryptosystem based on the factoring problem. RSA stands for Rivest, Shamir and Adleman, the developers of the RSA public-key cryptosystem.

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Datasheet ID: MPC180LMB 635544