M45PE20-VMP6G

M45PE20-VMP6G Datasheet

M45PE20

Part	Datasheet
M45PE20-VMP6G	M45PE20-VMP6G (pdf)

Related Parts	Information
M45PE20-VMN6P	M45PE20-VMN6P
M45PE20-VMP6TG TR	M45PE20-VMP6TG TR
M45PE20-VMN6TP TR	M45PE20-VMN6TP TR

PDF Datasheet Preview
M45PE20 2-Mbit, page-erasable serial flash memory with byte alterability and a 75 MHz SPI bus interface • SPI bus compatible serial interface • 75 MHz clock rate maximum • V to V single supply voltage • 2-Mbit, page-erasable flash memory • Page size 256 bytes Page write in 11 ms typical Page program in ms typical Page erase in 10 ms typical • Sector erase 512 Kbits • Hardware write protection of the bottom sector 64 Kbytes • Electronic signature JEDEC standard two-byte signature 4012h Unique ID code UID with 16 bytes read- only, available upon customer request only in the T9HX process • Deep power-down mode 1 µA typical • More than 100 000 write cycles • More than 20 years data retention • Packages RoHS compliant SO8 MN 150 mil width VFQFPN8 MP MLP8 May 2008 1/47 Contents Contents M45PE20 Description 6 Signal descriptions 8 Serial data output Q 8 Serial data input D 8 Serial Clock C 8 Chip Select S 8 Reset 8 Write Protect W 8 VCC supply voltage 9 VSS ground 9 SPI modes 10 Operating features 12 Sharing the overhead of modifying data 12 An easy way to modify data 12 A fast way to modify data 13 Polling during a write, program or erase cycle 13 Reset 13 Active power, standby power and deep power-down modes 13 Status register 14 Protection modes 14 Memory organization 15 Instructions 17 Write enable WREN 18 Write disable WRDI 18 Read identification RDID 19 Read status register RDSR 21 WIP bit 21 2/47 M45PE20 Ordering information 45 3/47 List of tables List of tables M45PE20 Table Table Table 4/47 M45PE20 List of figures List of figures Figure Figure Logic diagram 6 SO and VFQFPN connections 6 Bus master and memory devices on the SPI bus 10 SPI modes supported 11 Block diagram 16 Write enable WREN instruction sequence 18 Write disable WRDI instruction sequence 18 Read identification RDID instruction sequence and data-out sequence 20 Read status register RDSR instruction sequence and data-out sequence 21 Read data bytes READ instruction sequence and data-out sequence 22 Read data bytes at higher speed FAST_READ instruction sequence and data-out sequence 23 Page write PW instruction sequence 25 Page program PP instruction sequence 27 Page erase PE instruction sequence 28 Sector erase SE instruction sequence 29 Deep power-down DP instruction sequence 30 Release from deep power-down RDP instruction sequence 31 Power-up timing 33 AC measurement I/O waveform 35 Serial input timing 41 Write protect setup and hold timing 41 Output timing 42 Reset AC waveforms 42 SO8N 8 lead plastic small outline, 150 mils body width, package outline 43 MLP8, 8-lead very thin dual flat package no lead, 6 x 5 mm, package outline. 44 5/47 M45PE20 The M45PE20 is a 2-Mbit 256 Kbits x8 serial paged flash memory accessed by a high speed SPI-compatible bus. The memory can be written or programmed 1 to 256 bytes at a time, using the page write or page program instruction. The page write instruction consists of an integrated page erase cycle followed by a page program cycle. The memory is organized as 4 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 1024 pages, or 262,144 bytes. The memory can be erased a page at a time, using the page erase instruction, or a sector at a time, using the sector erase instruction. Important note This datasheet details the functionality of the M45PE20 devices, based on the previous T7X process or based on the current T9HX process available since August Delivery of parts operating with a maximum clock rate of 75 MHz starts from week 8 of Figure Logic diagram D C S W Reset Q M45PE20 6/47 AI07400 Figure SO and VFQFPN connections M45PE20 D1 C2 Reset 3 S4 8Q 7 VSS 6 VCC 5W AI07401 There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB. See Package mechanical section for package dimensions, and how to identify pin-1. M45PE20 Table Signal names Signal name Function Serial Clock Serial data input Serial data output Chip Select Write Protect Reset Reset Supply voltage Ground Direction Input Output Input Details of how to find the technology process in the marking are given in AN1995, see also Section 12 Ordering information. tCH + tCL must be greater than or equal to 1/ fC. Value guaranteed by characterization, not 100% tested in production. Only applicable as a constraint for a WRSR instruction when SRWD is set to When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes 1 n int A corresponds to the upper integer part of A. For instance, int 12/8 = 2, int 32/8 = 4 int 15.3 40/47 M45PE20 Figure Serial input timing S tCHSL tSLCH C tDVCH tCHDX MSB IN High Impedance Q Figure Write protect setup and hold timing W tWHSL DC and AC parameters tSHSL tCHSH tSHCH tCLCH LSB IN tCHCL AI01447C tSHWL High Impedance Q AI07439 41/47 DC and AC parameters Figure Output timing C tCLQV tCLQX Q tCLQX tCLQV D ADDR.LSB IN Figure Reset AC waveforms S Reset tSHRH tRLRH M45PE20 tSHQZ tQLQH tQHQL LSB OUT AI01449e tRHSL 12 Ordering information Ordering information Table Ordering information scheme Example: M45PE20 V MP 6 T G Device type M45PE = serial flash memory for data storage Device function 20 = 2-Mbit 256 Kbits x8 Operating voltage V = VCC = V to V Package MN = SO8 150 mil width MP = VDFPN8 6 x 5 mm MLP8 Device grade 6 = Industrial temperature range, to 85 °C. Device tested with standard test flow Option blank = standard packing T = tape and reel packing Plating technology P or G = RoHS compliant Note: For a list of available options speed, package, etc. , for further information on any aspect of this device or when ordering parts operating at 75 MHz µm technology, process digit ‘4’ , please contact your nearest Numonyx sales office. 45/47 M45PE20 Version Changes 30-Apr-2003 Initial release. 04-Jun-2003 Description corrected of entering hardware protected mode W must be driven, and cannot be left unconnected . 04-Dec-2003 VIO min extended to V, tPW typ and tPP typ improved. Table of contents, warning about exposed paddle on MLP8, and Pb-free options added. Change of naming for VDFPN8 package 21-Apr-2004 Soldering temperature information clarified for RoHS compliant devices. Device grade clarified. 22-Sep-2004 Document promoted to preliminary data. Minor wording changes. Device grade further clarified. 08-Oct-2004 3 Document promoted to full datasheet. No other changes. 4-Oct-2005 Added Table 13 AC characteristics 33 MHz operation . An easy way to modify data, A fast way to modify data, Page write PW and Page 4 program PP sections updated to explain optimal use of page write and page program instructions. Updated ICC3 values in Table 11 DC characteristics. Updated Table information added. 02-Feb-2007 Document reformatted. Small text changes. 50 MHz frequency added Table 14 added . VCC supply voltage and VSS ground descriptions added. Figure 3 Bus master and memory devices on the SPI bus modified and explanatory text added. VIO max modified in Table 7 Absolute maximum ratings. At power-up, The write in progress WIP bit is reset. tSHQZ end timing line modified in Figure 22 Output timing. Blank option removed below Plating technology in Table 18 Ordering information scheme. Small text changes. Package specifications updated see Section 11 Package mechanical . 22-May-2008 Applied Numonyx branding. Removed ‘low voltage’ from the title. Updated the value for the maximum clock frequency from 50 to 75 MHz throughout the document. 6 Added Table 15 AC characteristics 75 MHz operation, T9HX µm process and text in Section 11 Package mechanical. Modified Table 11 DC characteristics, Figure 3 Bus master and memory devices on the SPI bus, Section 3 SPI modes, and Section Read identification RDID . 46/47 M45PE20 Please Read Carefully INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 11/5/7, Numonyx, B.V., All Rights Reserved. 47/47

PDF Datasheet Preview

M45PE20
2-Mbit, page-erasable serial flash memory with byte alterability and a 75 MHz SPI bus interface
• SPI bus compatible serial interface
• 75 MHz clock rate maximum
• V to V single supply voltage
• 2-Mbit, page-erasable flash memory
• Page size 256 bytes

Page write in 11 ms typical Page program in ms typical Page erase in 10 ms typical
• Sector erase 512 Kbits
• Hardware write protection of the bottom sector 64 Kbytes
• Electronic signature JEDEC standard two-byte signature
4012h Unique ID code UID with 16 bytes read-
only, available upon customer request only in the T9HX process
• Deep power-down mode 1 µA typical
• More than 100 000 write cycles
• More than 20 years data retention
• Packages RoHS compliant

SO8 MN 150 mil width

VFQFPN8 MP MLP8

May 2008
1/47

Contents

Contents

M45PE20

Description 6

Signal descriptions 8

Serial data output Q 8

Serial data input D 8

Serial Clock C 8

Chip Select S 8

Reset 8

Write Protect W 8

VCC supply voltage 9 VSS ground 9

SPI modes 10

Operating features 12

Sharing the overhead of modifying data 12

An easy way to modify data 12

A fast way to modify data 13

Polling during a write, program or erase cycle 13

Reset 13

Active power, standby power and deep power-down modes 13

Status register 14

Protection modes 14

Memory organization 15

Instructions 17

Write enable WREN 18

Write disable WRDI 18

Read identification RDID 19

Read status register RDSR 21

WIP bit 21
2/47

M45PE20
Ordering information 45
3/47

List of tables

List of tables

M45PE20

Table

Table

Table
4/47

M45PE20

List of figures

List of figures

Figure

Figure

Logic diagram 6 SO and VFQFPN connections 6 Bus master and memory devices on the SPI bus 10 SPI modes supported 11 Block diagram 16 Write enable WREN instruction sequence 18 Write disable WRDI instruction sequence 18 Read identification RDID instruction sequence and data-out sequence 20 Read status register RDSR instruction sequence and data-out sequence 21 Read data bytes READ instruction sequence and data-out sequence 22 Read data bytes at higher speed FAST_READ instruction sequence and data-out sequence 23 Page write PW instruction sequence 25 Page program PP instruction sequence 27 Page erase PE instruction sequence 28 Sector erase SE instruction sequence 29 Deep power-down DP instruction sequence 30 Release from deep power-down RDP instruction sequence 31 Power-up timing 33 AC measurement I/O waveform 35 Serial input timing 41 Write protect setup and hold timing 41 Output timing 42 Reset AC waveforms 42 SO8N 8 lead plastic small outline, 150 mils body width, package outline 43 MLP8, 8-lead very thin dual flat package no lead, 6 x 5 mm, package outline. 44
5/47

M45PE20

The M45PE20 is a 2-Mbit 256 Kbits x8 serial paged flash memory accessed by a high speed SPI-compatible bus.

The memory can be written or programmed 1 to 256 bytes at a time, using the page write or page program instruction. The page write instruction consists of an integrated page erase cycle followed by a page program cycle.

The memory is organized as 4 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 1024 pages, or 262,144 bytes.

The memory can be erased a page at a time, using the page erase instruction, or a sector at a time, using the sector erase instruction.

Important note

This datasheet details the functionality of the M45PE20 devices, based on the previous T7X process or based on the current T9HX process available since August Delivery of parts operating with a maximum clock rate of 75 MHz starts from week 8 of

Figure Logic diagram

D C S W Reset

Q M45PE20
6/47

AI07400

Figure SO and VFQFPN connections

M45PE20

D1 C2 Reset 3 S4
8Q 7 VSS 6 VCC 5W

AI07401

There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.

See Package mechanical section for package dimensions, and how to identify pin-1.

M45PE20

Table Signal names

Signal name

Function

Serial Clock

Serial data input

Serial data output

Chip Select

Write Protect

Reset

Reset

Supply voltage

Ground

Direction Input Output Input
Details of how to find the technology process in the marking are given in AN1995, see also Section 12 Ordering information.
tCH + tCL must be greater than or equal to 1/ fC. Value guaranteed by characterization, not 100% tested in production.

Only applicable as a constraint for a WRSR instruction when SRWD is set to

When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes 1 n
int A corresponds to the upper integer part of A. For instance, int 12/8 = 2, int 32/8 = 4 int 15.3
40/47

M45PE20 Figure Serial input timing

S tCHSL
tSLCH

C tDVCH
tCHDX

MSB IN

High Impedance Q

Figure Write protect setup and hold timing

W tWHSL

DC and AC parameters
tSHSL
tCHSH
tSHCH
tCLCH LSB IN
tCHCL

AI01447C
tSHWL

High Impedance Q

AI07439
41/47

DC and AC parameters Figure Output timing

C tCLQV
tCLQX Q
tCLQX
tCLQV

D ADDR.LSB IN

Figure Reset AC waveforms

S Reset
tSHRH tRLRH

M45PE20
tSHQZ
tQLQH tQHQL

LSB OUT

AI01449e
tRHSL
12 Ordering information
Ordering information
Table Ordering information scheme

Example:

M45PE20

V MP 6 T G

Device type M45PE = serial flash memory for data storage

Device function 20 = 2-Mbit 256 Kbits x8

Operating voltage V = VCC = V to V

Package MN = SO8 150 mil width MP = VDFPN8 6 x 5 mm MLP8

Device grade
6 = Industrial temperature range, to 85 °C. Device tested with standard test flow

Option blank = standard packing T = tape and reel packing

Plating technology P or G = RoHS compliant

Note:
For a list of available options speed, package, etc. , for further information on any aspect of this device or when ordering parts operating at 75 MHz µm technology, process digit ‘4’ , please contact your nearest Numonyx sales office.
45/47

M45PE20

Version

Changes
30-Apr-2003 Initial release.
04-Jun-2003

Description corrected of entering hardware protected mode W must be driven, and cannot be left unconnected .
04-Dec-2003

VIO min extended to V, tPW typ and tPP typ improved. Table of contents, warning about exposed paddle on MLP8, and Pb-free options
added. Change of naming for VDFPN8 package
21-Apr-2004

Soldering temperature information clarified for RoHS compliant devices. Device grade clarified.
22-Sep-2004

Document promoted to preliminary data. Minor wording changes. Device grade further clarified.
08-Oct-2004
3 Document promoted to full datasheet. No other changes.
4-Oct-2005

Added Table 13 AC characteristics 33 MHz operation . An easy way to modify data, A fast way to modify data, Page write PW and Page 4 program PP sections updated to explain optimal use of page write and page program instructions. Updated ICC3 values in Table 11 DC characteristics. Updated Table information added.
02-Feb-2007

Document reformatted. Small text changes.
50 MHz frequency added Table 14 added . VCC supply voltage and VSS ground descriptions added. Figure 3 Bus master and memory devices on the SPI bus modified and explanatory text added.

VIO max modified in Table 7 Absolute maximum ratings.

At power-up, The write in progress WIP bit is reset.
tSHQZ end timing line modified in Figure 22 Output timing. Blank option removed below Plating technology in Table 18 Ordering information scheme. Small text changes.

Package specifications updated see Section 11 Package mechanical .
22-May-2008

Applied Numonyx branding. Removed ‘low voltage’ from the title.

Updated the value for the maximum clock frequency from 50 to 75 MHz throughout the document. 6 Added Table 15 AC characteristics 75 MHz operation, T9HX µm process and text in Section 11 Package mechanical. Modified Table 11 DC characteristics, Figure 3 Bus master and memory devices on the SPI bus, Section 3 SPI modes, and Section Read identification RDID .
46/47

M45PE20

Please Read Carefully INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY

WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others. Copyright 11/5/7, Numonyx, B.V., All Rights Reserved.
47/47

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived M45PE20-VMP6G Datasheet file may be downloaded here without warranties.

Datasheet ID: M45PE20-VMP6G 648296