M25PE40-VMC6G

M25PE40-VMC6G Datasheet

M25PE40

Part	Datasheet
M25PE40-VMC6G	M25PE40-VMC6G (pdf)

PDF Datasheet Preview
M25PE40 4 Mbit, page-erasable serial Flash memory with byte alterability, 75 MHz SPI bus, standard pinout • SPI bus compatible serial interface • 4 Mbit page-erasable Flash memory • Page size 256 bytes Page Write in 11 ms typical Page Program in ms typical Page Erase in 10 ms typical • Subsector Erase 4 Kbytes • Sector Erase 64 Kbytes • Bulk Erase 4 Mbits • V to V single supply voltage • 75 MHz clock rate maximum • Deep Power-down mode 1 µA typical • Electronic signature JEDEC standard two-byte signature 8013h • Software write protection on a 64-Kbyte sector basis • Hardware write protection of the memory area selected using the BP0, BP1 and BP2 bits • More than 100 000 Write cycles • More than 20 year data retention • Packages VFQFPN8 MP 6 x 5 mm MLP8 SO8W MW 208 mils SO8N MN 150 mils January 2008 1/62 Contents Contents M25PE40 Description 6 Signal description 8 Serial Data output Q 8 Serial Data input D 8 Serial Clock C 8 Chip Select S 8 Reset 8 Write Protect W or Top Sector Lock TSL 9 VCC supply voltage 9 VSS ground 9 SPI modes 10 Operating features 12 Sharing the overhead of modifying data 12 An easy way to modify data 12 A fast way to modify data 13 Polling during a Write, Program or Erase cycle 13 Reset 13 Active Power, Standby Power and Deep Power-down modes 13 Status Register 14 Protection modes 14 Protocol-related protections 14 Specific hardware and software protections 15 Memory organization 17 Instructions 19 Write Enable WREN 21 Write Disable WRDI 22 Read Identification RDID 23 Ordering information 59 3/62 List of tables List of tables M25PE40 Table Table 4/62 M25PE40 List of figures List of figures Figure Figure Figure Figure Logic diagram - previous T7X process 7 Logic diagram - new T9HX process 7 VFQFPN and SO connections 7 Bus master and memory devices on the SPI bus 10 SPI modes supported 11 Block diagram 18 Write Enable WREN instruction sequence 21 Write Disable WRDI instruction sequence 22 Read Identification RDID instruction sequence and data-out sequence 23 Read Status Register RDSR instruction sequence and data-out sequence 25 Write Status Register WRSR instruction sequence 26 Read Data Bytes READ instruction sequence and data-out sequence 28 Read Data Bytes at Higher Speed FAST_READ instruction sequence and data-out sequence 29 Read Lock Register RDLR instruction sequence and data-out sequence 30 Page Write PW instruction sequence 32 Page Program PP instruction sequence 34 Write to Lock Register WRLR instruction sequence. 35 Page Erase PE instruction sequence 36 Subsector Erase SSE instruction sequence. 37 Sector Erase SE instruction sequence 38 Bulk Erase BE instruction sequence 39 Deep Power-down DP instruction sequence 40 Release from Deep Power-down RDP instruction sequence 41 Power-up timing 43 AC measurement I/O waveform 46 Serial input timing 52 Top Sector Lock T7X process or Write Protect T9HX process setup and hold timing 52 Output timing 53 Reset AC waveforms 54 VFQFPN8 MLP8 8-lead very thin fine pitch quad flat package no lead 6 x 5 mm, package outline 55 SO8N 8 lead plastic small outline, 150 mils body width, package outline 57 SO8W 8 lead plastic small outline, 208 mils body width, package outline. 58 5/62 M25PE40 The M25PE40 is a 4 Mbit 512Kbit x 8 bit serial paged Flash memory accessed by a high speed SPI-compatible bus. The memory can be written or programmed 1 to 256 bytes at a time, using the Page Write or Page Program instruction. The Page Write instruction consists of an integrated Page Erase cycle followed by a Page Program cycle. The memory is organized as 8 sectors that are further divided up into 16 subsectors each 128 subsectors in total . Each sector contains 256 pages and each subsector contains 16 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 2048 pages, or 524,288 bytes. The memory can be erased a page at a time, using the Page Erase instruction, a subsector at a time, using the Subsector Erase instruction, a sector at a time, using the Sector Erase instruction or as a whole, using the Bulk Erase BE instruction. The memory can be write protected by either hardware or software using a mix of volatile and non-volatile protection features, depending on the application needs. The protection granularity is of 64 Kbytes sector granularity . Important note This datasheet details the functionality of the devices, based on the previous T7X process or based on the current T9HX process available since July Delivery of parts operating with a maximum clock rate of 75 MHz starts from week 8 of What are the changes? The M25PE40 in T9HX process offers the following additional features ● the whole memory array is partitioned into 4-Kbyte subsectors ● five new instructions Write Status Register WRSR , Write to Lock Register WRLR , Read Lock Register RDLR , 4-Kbyte Subsector Erase SSE and Bulk Erase BE ● Status Register 4 bits can be written BP0, BP1, BP2, SRWD ● WP input pin 3 write protection limits are extended, depending on the value of the BP0, BP1, BP2, SRWD bits. The WP write protection remains the same if bits BP2, BP1, BP0 are set to 0, 0, 1 ● smaller die size allowing assembly into an SO8N package. 6/62 M25PE40 Figure Logic diagram - previous T7X Figure Logic diagram - new T9HX process process D C S TSL Reset Q M25PE40 D C S W Reset Q M25PE40 AI09704C AI13781 Table Signal names Signal name Function Direction Serial Clock Input Serial Data input Input Details of how to find the technology process in the marking are given in AN1995, see also Section 13 Ordering information. tCH + tCL must be greater than or equal to 1/ fC. Value guaranteed by characterization, not 100% tested in production. Only applicable as a constraint for a WRSR instruction when SRWD is set to When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes 1 n int A corresponds to the upper integer part of A. For instance, int 12/8 = 2, int 32/8 = 4 int 15.3 50/62 M25PE40 DC and AC parameters Table AC characteristics 75 MHz operation, T9HX 0.11µm process 1 2 3 4 Test conditions specified in Table 14 and Table 15 Symbol Alt. Parameter Min. Typ. Max. Clock frequency for the following instructions: fC FAST_READ, RDLR, PW, PP, WRLR, PE, SE, D.C. SSE, DP, RDP, WREN, WRDI, RDSR, WRSR Clock frequency for READ instructions D.C. tCH 5 tCLH Clock High time tCL 5 tCLL Clock Low time Clock Slew Rate peak to peak tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ 6 tCLQV tCLQX tWHSL 7 tSHWL 7 tDP 6 tRDP 6 tW tPW 8 tPP 8 tCSS tDSU tDH tCSH tDIS tV tHO S Active Setup time relative to C S Not Active Hold time relative to C Data In Setup time Data In Hold time S Active Hold time relative to C S Not Active Setup time relative to C S Deselect time Output Disable time Clock Low to Output Valid Output Hold time Write Protect Setup time Write Protect Hold time S to Deep Power-down S High to Standby mode Write Status Register cycle time Page Write cycle time 256 bytes Page Program cycle time 256 bytes Page Program cycle time n bytes int n/8 x Page Erase cycle time Sector Erase cycle time tSSE Subsector Erase cycle time Bulk Erase cycle time See Important note on page Details of how to find the technology process in the marking are given in AN1995, see also Section 13 Ordering information. Delivery of parts operating with a maximum clock rate of 75 MHz starts from week 8 of Preliminary data. tCH + tCL must be greater than or equal to 1/ fC. Value guaranteed by characterization, not 100% tested in production. Only applicable as a constraint for a WRSR instruction when SRWD is set to Unit MHz ns V/ns µs µs ms ms s ms s 51/62 DC and AC parameters M25PE40 When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes 1 n int A corresponds to the upper integer part of A. For instance, int 12/8 = 2, int 32/8 = 4 int 15.3 Figure Serial input timing S tCHSL tSLCH C tDVCH tCHDX MSB IN tSHSL tCHSH tSHCH tCLCH LSB IN tCHCL High Impedance Q AI01447C Figure Top Sector Lock T7X process or Write Protect T9HX process setup and hold timing TSL or W tTHSL tWHSL tSHTL tSHWL D High Impedance For the differences between devices produced in the two processes, see Important note on page AI3559 52/62 M25PE40 Figure Output timing C tCLQV tCLQX Q tCLQX tCLQV D ADDR.LSB IN DC and AC parameters tCH tCL tSHQZ tQLQH tQHQL 13 Ordering information Ordering information Note: Table Ordering information scheme Example: M25PE40 V MP 6 T G Device type M25PE = page-erasable serial Flash memory Device function 40 = 4 Mbit 512Kbit x 8 Operating voltage V = VCC = to V Package MW = SO8W 208 mils width MP = VFQFPN8 6 x 5 mm MLP8 MN = SO8N 150 mils width 1 Device grade 6 = Industrial device tested with standard test flow over to 85 °C Option blank = standard packing T = tape and reel packing Plating technology P or G = RoHS compliant Package only available for products in the T9HX process. For a list of available options speed, package, etc. , for further information on any aspect of this device or when ordering parts operating at 75 MHz µm, process digit ‘4’ , please contact your nearest Numonyx Sales Office. 59/62 M25PE40 Changes 01-Apr-2004 Initial release. 09-Nov-2004 Write Protect W pin replaced by Top Block Lock TBL . Section Reset description modified. JEDEC signature modified. Reset timings tRLRH, tRHSL and tSHRH removed from Table 20 AC characteristics 33 MHz operation and inserted in Table 21 Reset timings tRHSL modified . Document status promoted from target specification to preliminary data. 01-Dec-2004 Top Block Lock TBL renamed as Top Sector Lock TSL . Small text changes. Deep Power-down mode clarified in Section Active Power, Standby Power and Deep Power-down modes. 11-Jan-2005 Notes removed from Table 28 Ordering information scheme. Wording changes. SO16 package removed, SO8 wide package added. 4-Oct-2005 Added Table 20 AC characteristics 33 MHz operation . Document status promoted from preliminary data to full datasheet. Table 19: AC characteristics 25 MHz operation updated. Section An easy way to modify data, Section A fast way to modify data, Section Page Write PW and Section Page Program PP updated to explain optimal use of Page Write and Page Program instructions. Clock slew rate changed from to V/ns. Updated Table 28 Ordering information scheme. Added information. 11-Aug 2006 Changed document to new template amended figure in Feature summary replaced Figure 4 Bus master and memory devices on the SPI bus amended data in Table 19 and Table 20 amended title of Figure 30 VFQFPN8 MLP8 8-lead very thin fine pitch quad flat package no lead 6 x 5 mm, package outline and added a footnote; amended name of the MP package in Table 28 Ordering information scheme. 60/62 M25PE40 Changes 15-Jan-2007 23-Jan-2007 50 MHz frequency added. SO8N package added, VFQFPN and SO8W package specifications updated see Section 12 Package mechanical . The sectors are further divided up into subsectors see Table 4 Memory organization . Important note on page 6 added. Figure 4 Bus master and memory devices on the SPI bus updated and explanatory paragraph added. VCC supply voltage and VSS ground added. Section Protection modes modified. Section 8 Reset added, reset timings table split into Table 23 Reset conditions and Table 24 Timings after a Reset Low pulse. At power-up the WIP bit is reset see Section 7 Power-up and power-down . VIO max changed in Table 13 Absolute maximum ratings. End timing line of tSHQZ moved in Figure 28 Output timing. Products processed in T9HX process added to datasheet: WP pin replaces TSL T7X technology , see Section Write Protect W or Top Sector Lock TSL Write Status Register WRSR and Subsector Erase SSE instructions added for T9HX process subsector protection granularity removed in T9HX process, still exists in T7X process Table 4 Memory organization updated to show subsectors Status Register BP2, BP1, BP0 bits and SRWD bit added. Small text changes. T7X process name corrected. Write Enable Latch WEL bit is reset also on completion of the Subsector Erase, Bulk Erase, Write to Lock Register and Write Status Register instructions see Section Write Disable WRDI . Address bit A20 is not Don’t care Note 1 modified in the Sector Erase SE instruction sequence. SO8N package is only available in products manufactured in the T9HX process. 10-Dec-2007 03-Jan-2007 Removed ‘low voltage’ from the title. Table 18 DC characteristics 75 MHz operation, T9HX µm process and Table 22 AC characteristics 75 MHz operation, T9HX 0.11µm process added. Added text in Section 12 Package mechanical. Updated the value for the maximum clock frequency from 50 to 75 MHz through the document. Minor text changes. Applied Numonyx branding. 61/62 M25PE40 Please Read Carefully INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.

PDF Datasheet Preview

M25PE40
4 Mbit, page-erasable serial Flash memory with byte alterability, 75 MHz SPI bus, standard pinout
• SPI bus compatible serial interface
• 4 Mbit page-erasable Flash memory
• Page size 256 bytes

Page Write in 11 ms typical Page Program in ms typical Page Erase in 10 ms typical
• Subsector Erase 4 Kbytes
• Sector Erase 64 Kbytes
• Bulk Erase 4 Mbits
• V to V single supply voltage
• 75 MHz clock rate maximum
• Deep Power-down mode 1 µA typical
• Electronic signature JEDEC standard two-byte signature
8013h
• Software write protection on a 64-Kbyte sector
basis
• Hardware write protection of the memory area
selected using the BP0, BP1 and BP2 bits
• More than 100 000 Write cycles
• More than 20 year data retention
• Packages

VFQFPN8 MP 6 x 5 mm MLP8

SO8W MW 208 mils

SO8N MN 150 mils

January 2008
1/62

Contents

Contents

M25PE40

Description 6

Signal description 8

Serial Data output Q 8

Serial Data input D 8

Serial Clock C 8

Chip Select S 8

Reset 8

Write Protect W or Top Sector Lock TSL 9

VCC supply voltage 9 VSS ground 9

SPI modes 10

Operating features 12

Sharing the overhead of modifying data 12

An easy way to modify data 12

A fast way to modify data 13

Polling during a Write, Program or Erase cycle 13

Reset 13

Active Power, Standby Power and Deep Power-down modes 13

Status Register 14

Protection modes 14

Protocol-related protections 14

Specific hardware and software protections 15

Memory organization 17

Instructions 19

Write Enable WREN 21

Write Disable WRDI 22

Read Identification RDID 23
Ordering information 59
3/62

List of tables

List of tables

M25PE40

Table

Table
4/62

M25PE40

List of figures

List of figures

Figure

Figure

Figure

Figure

Logic diagram - previous T7X process 7 Logic diagram - new T9HX process 7 VFQFPN and SO connections 7 Bus master and memory devices on the SPI bus 10 SPI modes supported 11 Block diagram 18 Write Enable WREN instruction sequence 21 Write Disable WRDI instruction sequence 22 Read Identification RDID instruction sequence and data-out sequence 23 Read Status Register RDSR instruction sequence and data-out sequence 25 Write Status Register WRSR instruction sequence 26 Read Data Bytes READ instruction sequence and data-out sequence 28 Read Data Bytes at Higher Speed FAST_READ instruction sequence and data-out sequence 29 Read Lock Register RDLR instruction sequence and data-out sequence 30 Page Write PW instruction sequence 32 Page Program PP instruction sequence 34 Write to Lock Register WRLR instruction sequence. 35 Page Erase PE instruction sequence 36 Subsector Erase SSE instruction sequence. 37 Sector Erase SE instruction sequence 38 Bulk Erase BE instruction sequence 39 Deep Power-down DP instruction sequence 40 Release from Deep Power-down RDP instruction sequence 41 Power-up timing 43 AC measurement I/O waveform 46 Serial input timing 52 Top Sector Lock T7X process or Write Protect T9HX process setup and hold timing 52 Output timing 53 Reset AC waveforms 54 VFQFPN8 MLP8 8-lead very thin fine pitch quad flat package no lead 6 x 5 mm, package outline 55 SO8N 8 lead plastic small outline, 150 mils body width, package outline 57 SO8W 8 lead plastic small outline, 208 mils body width, package outline. 58
5/62

M25PE40

The M25PE40 is a 4 Mbit 512Kbit x 8 bit serial paged Flash memory accessed by a high speed SPI-compatible bus.

The memory can be written or programmed 1 to 256 bytes at a time, using the Page Write or Page Program instruction. The Page Write instruction consists of an integrated Page Erase cycle followed by a Page Program cycle.

The memory is organized as 8 sectors that are further divided up into 16 subsectors each 128 subsectors in total . Each sector contains 256 pages and each subsector contains 16 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 2048 pages, or 524,288 bytes.

The memory can be erased a page at a time, using the Page Erase instruction, a subsector at a time, using the Subsector Erase instruction, a sector at a time, using the Sector Erase instruction or as a whole, using the Bulk Erase BE instruction.

The memory can be write protected by either hardware or software using a mix of volatile and non-volatile protection features, depending on the application needs. The protection granularity is of 64 Kbytes sector granularity .

Important note

This datasheet details the functionality of the devices, based on the previous T7X process or based on the current T9HX process available since July Delivery of parts operating with a maximum clock rate of 75 MHz starts from week 8 of

What are the changes?

The M25PE40 in T9HX process offers the following additional features ● the whole memory array is partitioned into 4-Kbyte subsectors ● five new instructions Write Status Register WRSR , Write to Lock Register WRLR ,

Read Lock Register RDLR , 4-Kbyte Subsector Erase SSE and Bulk Erase BE ● Status Register 4 bits can be written BP0, BP1, BP2, SRWD ● WP input pin 3 write protection limits are extended, depending on the value of the

BP0, BP1, BP2, SRWD bits. The WP write protection remains the same if bits BP2, BP1, BP0 are set to 0, 0, 1 ● smaller die size allowing assembly into an SO8N package.
6/62

M25PE40

Figure Logic diagram - previous T7X Figure Logic diagram - new T9HX
process
process

D C S TSL Reset

Q M25PE40

D C S W Reset

Q M25PE40

AI09704C

AI13781

Table Signal names

Signal name

Function

Direction

Serial Clock

Input

Serial Data input

Input
Details of how to find the technology process in the marking are given in AN1995, see also Section 13 Ordering information.
tCH + tCL must be greater than or equal to 1/ fC. Value guaranteed by characterization, not 100% tested in production.

Only applicable as a constraint for a WRSR instruction when SRWD is set to

When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes 1 n
int A corresponds to the upper integer part of A. For instance, int 12/8 = 2, int 32/8 = 4 int 15.3
50/62

M25PE40

DC and AC parameters

Table

AC characteristics 75 MHz operation, T9HX 0.11µm process 1 2 3 4 Test conditions specified in Table 14 and Table 15

Symbol Alt.

Parameter

Min.

Typ.

Max.

Clock frequency for the following instructions:
fC FAST_READ, RDLR, PW, PP, WRLR, PE, SE, D.C.

SSE, DP, RDP, WREN, WRDI, RDSR, WRSR

Clock frequency for READ instructions

D.C.
tCH 5
tCLH Clock High time
tCL 5
tCLL Clock Low time

Clock Slew Rate peak to peak
tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ 6 tCLQV tCLQX tWHSL 7 tSHWL 7 tDP 6 tRDP 6
tW tPW 8
tPP 8
tCSS
tDSU tDH
tCSH tDIS tV tHO

S Active Setup time relative to C S Not Active Hold time relative to C Data In Setup time Data In Hold time S Active Hold time relative to C S Not Active Setup time relative to C S Deselect time Output Disable time Clock Low to Output Valid Output Hold time Write Protect Setup time Write Protect Hold time S to Deep Power-down S High to Standby mode Write Status Register cycle time Page Write cycle time 256 bytes Page Program cycle time 256 bytes

Page Program cycle time n bytes
int n/8 x

Page Erase cycle time

Sector Erase cycle time
tSSE

Subsector Erase cycle time

Bulk Erase cycle time
See Important note on page Details of how to find the technology process in the marking are given in AN1995, see also Section 13 Ordering
information. Delivery of parts operating with a maximum clock rate of 75 MHz starts from week 8 of Preliminary data. tCH + tCL must be greater than or equal to 1/ fC. Value guaranteed by characterization, not 100% tested in production. Only applicable as a constraint for a WRSR instruction when SRWD is set to

Unit

MHz ns V/ns µs µs ms
ms s ms s
51/62

DC and AC parameters

M25PE40

When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes 1 n
int A corresponds to the upper integer part of A. For instance, int 12/8 = 2, int 32/8 = 4 int 15.3

Figure Serial input timing

S tCHSL
tSLCH

C tDVCH
tCHDX

MSB IN
tSHSL
tCHSH
tSHCH
tCLCH LSB IN
tCHCL

High Impedance Q

AI01447C

Figure Top Sector Lock T7X process or Write Protect T9HX process setup and hold timing

TSL or W
tTHSL tWHSL
tSHTL tSHWL

D High Impedance

For the differences between devices produced in the two processes, see Important note on page

AI3559
52/62

M25PE40 Figure Output timing

C tCLQV
tCLQX Q
tCLQX
tCLQV

D ADDR.LSB IN

DC and AC parameters
tCH tCL
tSHQZ
tQLQH tQHQL
13 Ordering information
Ordering information

Note:
Table Ordering information scheme

Example:

M25PE40

V MP 6 T G

Device type M25PE = page-erasable serial Flash memory

Device function 40 = 4 Mbit 512Kbit x 8

Operating voltage V = VCC = to V

Package MW = SO8W 208 mils width MP = VFQFPN8 6 x 5 mm MLP8 MN = SO8N 150 mils width 1

Device grade 6 = Industrial device tested with standard test flow over to 85 °C

Option blank = standard packing T = tape and reel packing

Plating technology

P or G = RoHS compliant

Package only available for products in the T9HX process.
For a list of available options speed, package, etc. , for further information on any aspect of this device or when ordering parts operating at 75 MHz µm, process digit ‘4’ , please contact your nearest Numonyx Sales Office.
59/62

M25PE40

Changes
01-Apr-2004

Initial release.
09-Nov-2004

Write Protect W pin replaced by Top Block Lock TBL .

Section Reset description modified. JEDEC signature
modified. Reset timings tRLRH, tRHSL and tSHRH removed from

Table 20 AC characteristics 33 MHz operation and inserted in

Table 21 Reset timings tRHSL modified . Document status promoted from target specification to preliminary data.
01-Dec-2004

Top Block Lock TBL renamed as Top Sector Lock TSL . Small text
changes. Deep Power-down mode clarified in Section Active

Power, Standby Power and Deep Power-down modes.
11-Jan-2005
Notes removed from Table 28 Ordering information scheme.

Wording changes. SO16 package removed, SO8 wide package
added.
4-Oct-2005

Added Table 20 AC characteristics 33 MHz operation . Document
status promoted from preliminary data to full datasheet. Table 19:

AC characteristics 25 MHz operation updated. Section An
easy way to modify data, Section A fast way to modify data,

Section Page Write PW and Section Page Program PP
updated to explain optimal use of Page Write and Page Program
instructions. Clock slew rate changed from to V/ns.
Updated Table 28 Ordering information scheme. Added
information.
11-Aug 2006

Changed document to new template amended figure in Feature
summary replaced Figure 4 Bus master and memory devices on
the SPI bus amended data in Table 19 and Table 20 amended title
of Figure 30 VFQFPN8 MLP8 8-lead very thin fine pitch quad flat
package no lead 6 x 5 mm, package outline and added a footnote;
amended name of the MP package in Table 28 Ordering
information scheme.
60/62

M25PE40

Changes
15-Jan-2007 23-Jan-2007
50 MHz frequency added. SO8N package added, VFQFPN and SO8W package specifications updated see Section 12 Package mechanical .

The sectors are further divided up into subsectors see Table 4 Memory organization . Important note on page 6 added. Figure 4 Bus master and memory devices on the SPI bus updated and explanatory paragraph added. VCC supply voltage and VSS ground added. Section Protection modes modified. Section 8 Reset added, reset timings table split into Table 23 Reset conditions and Table 24 Timings after a Reset Low pulse.

At power-up the WIP bit is reset see Section 7 Power-up and power-down .

VIO max changed in Table 13 Absolute maximum ratings. End
timing line of tSHQZ moved in Figure 28 Output timing.

Products processed in T9HX process added to datasheet:

WP pin replaces TSL T7X technology , see Section Write Protect W or Top Sector Lock TSL

Write Status Register WRSR and Subsector Erase SSE instructions added for T9HX process
subsector protection granularity removed in T9HX process, still exists in T7X process

Table 4 Memory organization updated to show subsectors

Status Register BP2, BP1, BP0 bits and SRWD bit added.

Small text changes.

T7X process name corrected.

Write Enable Latch WEL bit is reset also on completion of the

Subsector Erase, Bulk Erase, Write to Lock Register and Write

Status Register instructions see Section Write Disable WRDI .

Address bit A20 is not Don’t care Note 1 modified in the Sector Erase SE instruction sequence. SO8N package is only available in products manufactured in the T9HX process.
10-Dec-2007 03-Jan-2007

Removed ‘low voltage’ from the title.

Table 18 DC characteristics 75 MHz operation, T9HX µm
process and Table 22 AC characteristics 75 MHz operation, T9HX
0.11µm process added.

Added text in Section 12 Package mechanical.

Updated the value for the maximum clock frequency from 50 to 75 MHz through the document.

Minor text changes.

Applied Numonyx branding.
61/62

M25PE40

Please Read Carefully INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY

WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived M25PE40-VMC6G Datasheet file may be downloaded here without warranties.

Datasheet ID: M25PE40-VMC6G 648286