EDY4016AABG-GX-F-D

EDY4016AABG-GX-F-D Datasheet

EDY4016A - 256Mb x 16

Part	Datasheet
EDY4016AABG-GX-F-D	EDY4016AABG-GX-F-D (pdf)

Related Parts	Information
EDY4016AABG-GX-F-R TR	EDY4016AABG-GX-F-R TR
EDY4016AABG-JD-F-R TR	EDY4016AABG-JD-F-R TR
EDY4016AABG-JD-F-D	EDY4016AABG-JD-F-D
EDY4016AABG-DR-F-D	EDY4016AABG-DR-F-D
EDY4016AABG-DR-F-R TR	EDY4016AABG-DR-F-R TR

PDF Datasheet Preview
DDR4 SDRAM EDY4016A - 256Mb x 16 • VDD = VDDQ = 1.2V ±60mV • VPP = 2.5V, • On-die, internal, adjustable VREFDQ generation • 1.2V pseudo open-drain I/O • TC of 0°C to 95°C 64ms, 8192-cycle refresh at 0°C to 85°C 32ms at 85°C to 95°C • 8 internal banks 2 groups of 4 banks each • 8n-bit prefetch architecture • Programmable data strobe preambles • Data strobe preamble training • Command/Address latency CAL • Multipurpose register READ and WRITE capability • Write and read leveling • Self refresh mode • Low-power auto self refresh LPASR • Temperature controlled refresh TCR • Fine granularity refresh • Self refresh abort • Maximum power saving • Output driver calibration • Nominal, park, and dynamic on-die termination ODT • Data bus inversion DBI for data bus • Command/Address CA parity 4Gb x16 DDR4 SDRAM Features • Databus write cyclic redundancy check CRC • Per-DRAM addressability • Connectivity test • JEDEC JESD-79-4 compliant Options1 Marking • FBGA package size 96-ball 7.5mm x 13.5mm • Timing cycle time 0.625ns CL = 24 DDR4-3200 0.750ns CL = 19 DDR4-2666 0.833ns CL = 16 DDR4-2400 • Packaging Lead-free RoHS-compliant and hal- - F ogen-free Not all options listed can be combined to define an offered product. Use the part catalog search on for available offerings. Restricted and limited availability. Table 1 Key Timing Parameters Speed Grade -JD1 -GX2 -DR3 Data Rate MT/s 3200 2666 2400 Target tRCD-tRP-CL 24-24-24 19-19-19 16-16-16 tRCD ns tRP ns CL ns Notes Backward compatible to 2666 CL = 20, 2400 CL = 18 , 2133 CL = 16, 1866 CL = 14, 1600 CL = Backward compatible to 2400 CL = 17, 2133 CL = 15, 1866 CL = 13, 1600 CL = Backward compatible to 2133 CL = 15, 1866 CL = 13, 1600 CL = Table 2 Addressing Parameter Number of bank groups Bank group address 256 Meg x 16 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 4Gb x16 DDR4 SDRAM Features Table 2 Addressing Continued Parameter Bank count per group Bank address in bank group Row addressing Column addressing Page size1 256 Meg x 16 4 BA[1:0] 32K A[14:0] 1K A[9:0] 2KB Note Page size is per bank, calculated as follows Page size = 2COLBITS x ORG/8, where COLBIT = the number of column address bits and ORG = the number of DQ bits. Micron Memory Japan DDR4 Part Numbering PPR Row Repair - Entry 122 PPR Row Repair WRA Initiated REF Commands Allowed 123 PPR Row Repair WR Initiated REF Commands NOT Allowed 124 sPPR Row Repair 126 PPR/sPPR Support Identifier 128 Target Row Refresh Mode 129 ACTIVATE Command 130 PRECHARGE Command 131 REFRESH Command 131 Temperature-Controlled Refresh Mode 133 TCR Mode Normal Temperature Range 133 TCR Mode Extended Temperature Range 133 Fine Granularity Refresh Mode 135 Mode Register and Command Truth Table 135 tREFI and tRFC Parameters 135 Changing Refresh Rate 138 Usage with TCR Mode 138 Self Refresh Entry and Exit 138 SELF REFRESH Operation 140 Self Refresh Abort 142 Self Refresh Exit with NOP Command 143 Power-Down Mode 145 Power-Down Clarifications Case 1 150 Power-Down Entry, Exit Timing with CAL 151 ODT Input Buffer Disable Mode for Power-Down 154 CRC Write Data Feature 156 CRC Write Data 156 WRITE CRC DATA Operation 156 DBI_n and CRC Both Enabled 157 DM_n and CRC Both Enabled 157 DM_n and DBI_n Conflict During Writes with CRC Enabled 157 CRC and Write Preamble Restrictions 157 CRC Simultaneous Operation Restrictions 157 CRC Polynomial 157 CRC Combinatorial Logic Equations 158 Burst Ordering for BL8 159 CRC Data Bit Mapping 159 CRC Enabled With BC4 160 CRC with BC4 Data Bit Mapping 160 CRC Equations for x8 Device in BC4 Mode with A2 = 0 and A2 = 1 163 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved. 4Gb x16 DDR4 SDRAM Features CRC Error Handling 165 CRC Write Data Flow Diagram 166 Data Bus Inversion 167 DBI During a WRITE Operation 167 DBI During a READ Operation 168 Data Mask 169 Programmable Preamble Modes and DQS Postambles 170 WRITE Preamble Mode 170 READ Preamble Mode 174 READ Preamble Training 174 WRITE Postamble 175 READ Postamble 175 Bank Access Operation 177 READ Operation 181 Read Timing Definitions 181 Read Timing Clock-to-Data Strobe Relationship 182 Read Timing Data Strobe-to-Data Relationship 183 tLZ DQS , tLZ DQ , tHZ DQS , and tHZ DQ Calculations 184 tRPRE Calculation 186 tRPST Calculation 187 READ Burst Operation 188 READ Operation Followed by Another READ Operation 190 READ Operation Followed by WRITE Operation 195 READ Operation Followed by PRECHARGE Operation 201 READ Operation with Read Data Bus Inversion DBI 204 READ Operation with Command/Address Parity CA Parity 205 READ Followed by WRITE with CRC Enabled 207 READ Operation with Command/Address Latency CAL Enabled 208 WRITE Operation 210 Write Timing Definitions 210 Write Timing Clock-to-Data Strobe Relationship 210 Write Timing Data Strobe-to-Data Relationship 211 WRITE Burst Operation 215 WRITE Operation Followed by Another WRITE Operation 217 WRITE Operation Followed by READ Operation 223 WRITE Operation Followed by PRECHARGE Operation 227 WRITE Operation with WRITE DBI Enabled 230 WRITE Operation with CA Parity Enabled 232 WRITE Operation with Write CRC Enabled 233 Write Timing Violations 238 Motivation 238 Data Setup and Hold Violations 238 Strobe-to-Strobe and Strobe-to-Clock Violations 238 ZQ CALIBRATION Commands 239 On-Die Termination 241 ODT Mode Register and ODT State Table 241 ODT Read Disable State Table 242 Synchronous ODT Mode 243 ODT Latency and Posted ODT 243 Timing Parameters 243 ODT During Reads 245 Dynamic ODT 246 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved. 4Gb x16 DDR4 SDRAM Features Functional Description 246 Asynchronous ODT Mode 249 Electrical Specifications 250 Absolute Ratings 250 DRAM Component Operating Temperature Range 250 Electrical Characteristics AC and DC Operating Conditions 251 Supply Operating Conditions 251 Leakages 251 VREFCA Supply 252 VREFDQ Supply and Calibration Ranges 253 VREFDQ Ranges 254 Electrical Characteristics AC and DC Single-Ended Input Measurement Levels 256 RESET_n Input Levels 256 Command/Address Input Levels 256 Data Receiver Input Requirements 259 Connectivity Test CT Mode Input Levels 262 Electrical Characteristics AC and DC Differential Input Measurement Levels 266 Differential Inputs 266 Single-Ended Requirements for CK Differential Signals 267 Slew Rate Definitions for CK Differential Input Signals 268 CK Differential Input Cross Point Voltage 269 DQS Differential Input Signal Definition and Swing Requirements 271 DQS Differential Input Cross Point Voltage 273 Slew Rate Definitions for DQS Differential Input Signals 274 Electrical Characteristics Overshoot and Undershoot Specifications 276 Address, Command, and Control Overshoot and Undershoot Specifications 276 Clock Overshoot and Undershoot Specifications 276 Data, Strobe, and Mask Overshoot and Undershoot Specifications 277 Electrical Characteristics AC and DC Output Measurement Levels 278 Single-Ended Outputs 278 Differential Outputs 279 Reference Load for AC Timing and Output Slew Rate 281 Connectivity Test Mode Output Levels 281 Electrical Characteristics AC and DC Output Driver Characteristics 284 Output Driver Electrical Characteristics 284 Output Driver Temperature and Voltage Sensitivity 287 Alert Driver 287 Electrical Characteristics On-Die Termination Characteristics 289 ODT Levels and I-V Characteristics 289 ODT Temperature and Voltage Sensitivity 290 ODT Timing Definitions 291 DRAM Package Electrical Specifications 294 Thermal Characteristics 298 Current Specifications Measurement Conditions 299 IDD, IPP, and IDDQ Measurement Conditions 299 IDD Definitions 300 Current Specifications Patterns and Test Conditions 304 Current Test Definitions and Patterns 304 IDD Specifications 313 Current Specifications Limits 314 Speed Bin Tables 316 Refresh Parameters By Device Density 325 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved. 4Gb x16 DDR4 SDRAM Features Electrical Characteristics and AC Timing Parameters 326 Electrical Characteristics and AC Timing Parameters 2666 Through 3200 338 Timing Parameter Notes 349 Clock Specification 351 Definition for tCK AVG 351 Definition for tCK ABS 351 Definition for tCH AVG and tCL AVG 351 Definition for tJIT per and tJIT per,lck 351 Definition for tJIT cc and tJIT cc,lck 351 Definition for tERR nper 351 Jitter Notes 352 EDY4016 Option and Exception Lists 353 Mode Register Settings 353 Options Tables 354 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved. 4Gb x16 DDR4 SDRAM Features List of Figures Figure 1 4Gb DDR4 Part Numbers 2 Figure 2 96-Ball x16 Ball Assignments 19 Figure 3 96-Ball FBGA x16 23 Figure 4 Simplified State Diagram 24 Figure 5 RESET and Initialization Sequence at Power-On Ramping 29 Figure 6 RESET Procedure at Power Stable Condition 30 Figure 7 tMRD Timing 32 Figure 8 tMOD Timing 32 Figure 9 DLL-Off Mode Read Timing Operation 62 Figure 10 DLL Switch Sequence from DLL-On to DLL-Off 64 Figure 11 DLL Switch Sequence from DLL-Off to DLL-On 65 Figure 12 Write-Leveling Concept, Example 1 67 Figure 13 Write-Leveling Concept, Example 2 68 Figure 14 Write-Leveling Sequence DQS Capturing CK LOW at T1 and CK HIGH at T2 70 Figure 15 Write-Leveling Exit 71 Figure 16 CAL Timing Definition 72 Figure 17 CAL Timing Example Consecutive CS_n = LOW 72 Figure 18 CAL Enable Timing tMOD_CAL 73 Figure 19 tMOD_CAL, MRS to Valid Command Timing with CAL Enabled 73 Figure 20 CAL Enabling MRS to Next MRS Command, tMRD_CAL 74 Figure 21 tMRD_CAL, Mode Register Cycle Time With CAL Enabled 74 Figure 22 Consecutive READ BL8, CAL3, 1tCK Preamble, Different Bank Group 75 Figure 23 Consecutive READ BL8, CAL4, 1tCK Preamble, Different Bank Group 75 Figure 24 Auto Self Refresh Ranges 78 Figure 25 MPR Block Diagram 79 Figure 26 MPR READ Timing 86 Figure 27 MPR Back-to-Back READ Timing 86 Figure 28 MPR READ-to-WRITE Timing 88 Figure 29 MPR WRITE and WRITE-to-READ Timing 89 Figure 30 MPR Back-to-Back WRITE Timing 90 Figure 31 REFRESH Timing 90 Figure 32 READ-to-REFRESH Timing 91 Figure 33 WRITE-to-REFRESH Timing 91 Figure 34 Clock Mode Change from 1/2 Rate to 1/4 Rate Initialization 94 Figure 35 Clock Mode Change After Exiting Self Refresh 94 Figure 36 Comparison Between Gear-Down Disable and Gear-Down Enable 95 Figure 37 Maximum Power-Saving Mode Entry 96 Figure 38 Maximum Power-Saving Mode Entry with PDA 97 Figure 39 Maintaining Maximum Power-Saving Mode with CKE Transition 97 Figure 40 Maximum Power-Saving Mode Exit 98 Figure 41 Command/Address Parity Operation 99 Figure 42 Command/Address Parity During Normal Operation 101 Figure 43 Persistent CA Parity Error Checking Operation 102 Figure 44 CA Parity Error Checking SRE Attempt 102 Figure 45 CA Parity Error Checking SRX Attempt 103 Figure 46 CA Parity Error Checking PDE/PDX 103 Figure 47 Parity Entry Timing Example tMRD_PAR 104 Figure 48 Parity Entry Timing Example tMOD_PAR 104 Figure 49 Parity Exit Timing Example tMRD_PAR 105 Figure 50 Parity Exit Timing Example tMOD_PAR 105 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved. 4Gb x16 DDR4 SDRAM Features Figure 51 CA Parity Flow Diagram 106 Figure 52 PDA Operation Enabled, BL8 108 Figure 53 PDA Operation Enabled, BC4 108 Figure 54 MRS PDA Exit 109 Figure 55 VREFDQ Voltage Range 110 Figure 56 Example of VREF Set Tolerance and Step Size 112 Figure 57 VREFDQ Timing Diagram for VREF,time Parameter 113 Figure 58 VREFDQ Training Mode Entry and Exit Timing Diagram 114 Figure 59 VREF Step Single Step Size Increment Case 115 Figure 60 VREF Step Single Step Size Decrement Case 115 Figure 61 VREF Full Step From VREF,min to VREF,maxCase 116 Figure 62 VREF Full Step From VREF,max to VREF,minCase 116 Figure 63 VREFDQ Equivalent Circuit 117 Figure 64 Connectivity Test Mode Entry 121 Figure 65 PPR WRA Entry 124 Figure 66 PPR WRA Repair and Exit 124 Figure 67 PPR WR Entry 125 Figure 68 PPR WR Repair and Exit 126 Figure 69 sPPR Entry, Repair, and Exit 127 Figure 70 tRRD Timing 130 Figure 71 tFAW Timing 130 Figure 72 REFRESH Command Timing 132 Figure 73 Postponing REFRESH Commands Example 132 Figure 74 Pulling In REFRESH Commands Example 132 Figure 75 TCR Mode Example1 134 Figure 76 4Gb with Fine Granularity Refresh Mode Example 137 Figure 77 OTF REFRESH Command Timing 138 Figure 78 Self Refresh Entry/Exit Timing 141 Figure 79 Self Refresh Entry/Exit Timing with CAL Mode 142 Figure 80 Self Refresh Abort 143 Figure 81 Self Refresh Exit with NOP Command 144 Figure 82 Active Power-Down Entry and Exit 146 Figure 83 Power-Down Entry After Read and Read with Auto Precharge 147 Figure 84 Power-Down Entry After Write and Write with Auto Precharge 147 Figure 85 Power-Down Entry After Write 148 Figure 86 Precharge Power-Down Entry and Exit 148 Figure 87 REFRESH Command to Power-Down Entry 149 Figure 88 Active Command to Power-Down Entry 149 Figure 89 PRECHARGE/PRECHARGE ALL Command to Power-Down Entry 150 Figure 90 MRS Command to Power-Down Entry 150 Figure 91 Power-Down Entry/Exit Clarifications Case 1 151 Figure 92 Active Power-Down Entry and Exit Timing with CAL 152 Figure 93 REFRESH Command to Power-Down Entry with CAL 153 Figure 94 ODT Power-Down Entry with ODT Buffer Disable Mode 154 Figure 95 ODT Power-Down Exit with ODT Buffer Disable Mode 155 Figure 96 CRC Write Data Operation 156 Figure 97 CRC Error Reporting 165 Figure 98 CA Parity Flow Diagram 166 Figure 99 1tCK vs. 2tCK WRITE Preamble Mode 170 Figure 100 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 4 172 Figure 101 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 5 173 Figure 102 1tCK vs. 2 tCK WRITE Preamble Mode, tCCD = 6 173 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved. 4Gb x16 DDR4 SDRAM Features Figure 103 1tCK vs. 2tCK READ Preamble Mode 174 Figure 104 READ Preamble Training 175 Figure 105 WRITE Postamble 175 Figure 106 READ Postamble 176 Figure 107 Bank Group x4/x8 Block Diagram 177 Figure 108 READ Burst tCCD_S and tCCD_L Examples 178 Figure 109 Write Burst tCCD_S and tCCD_L Examples 178 Figure 110 tRRD Timing 179 Figure 111 tWTR_S Timing WRITE-to-READ, Different Bank Group, CRC and DM Disabled 179 Figure 112 tWTR_L Timing WRITE-to-READ, Same Bank Group, CRC and DM Disabled 180 Figure 113 Read Timing Definition 182 Figure 114 Clock-to-Data Strobe Relationship 183 Figure 115 Data Strobe-to-Data Relationship 184 Figure 116 tLZ and tHZ Method for Calculating Transitions and Endpoints 185 Figure 117 tRPRE Method for Calculating Transitions and Endpoints 186 Figure 118 tRPST Method for Calculating Transitions and Endpoints 187 Figure 119 READ Burst Operation, RL = 11 AL = 0, CL = 11, BL8 188 Figure 120 READ Burst Operation, RL = 21 AL = 10, CL = 11, BL8 189 Figure 121 Consecutive READ BL8 with 1tCK Preamble in Different Bank Group 190 Figure 122 Consecutive READ BL8 with 2tCK Preamble in Different Bank Group 190 Figure 123 Nonconsecutive READ BL8 with 1tCK Preamble in Same or Different Bank Group 191 Figure 124 Nonconsecutive READ BL8 with 2tCK Preamble in Same or Different Bank Group 191 Figure 125 READ BC4 to READ BC4 with 1tCK Preamble in Different Bank Group 192 Figure 126 READ BC4 to READ BC4 with 2tCK Preamble in Different Bank Group 192 Figure 127 READ BL8 to READ BC4 OTF with 1tCK Preamble in Different Bank Group 193 Figure 128 READ BL8 to READ BC4 OTF with 2tCK Preamble in Different Bank Group 193 Figure 129 READ BC4 to READ BL8 OTF with 1tCK Preamble in Different Bank Group 194 Figure 130 READ BC4 to READ BL8 OTF with 2tCK Preamble in Different Bank Group 194 Figure 131 READ BL8 to WRITE BL8 with 1tCK Preamble in Same or Different Bank Group 195 Figure 132 READ BL8 to WRITE BL8 with 2tCK Preamble in Same or Different Bank Group 195 Figure 133 READ BC4 OTF to WRITE BC4 OTF with 1tCK Preamble in Same or Different Bank Group 196 Figure 134 READ BC4 OTF to WRITE BC4 OTF with 2tCK Preamble in Same or Different Bank Group 197 Figure 135 READ BC4 Fixed to WRITE BC4 Fixed with 1tCK Preamble in Same or Different Bank Group 197 Figure 136 READ BC4 Fixed to WRITE BC4 Fixed with 2tCK Preamble in Same or Different Bank Group 198 Figure 137 READ BC4 to WRITE BL8 OTF with 1tCK Preamble in Same or Different Bank Group 199 Figure 138 READ BC4 to WRITE BL8 OTF with 2tCK Preamble in Same or Different Bank Group 199 Figure 139 READ BL8 to WRITE BC4 OTF with 1tCK Preamble in Same or Different Bank Group 200 Figure 140 READ BL8 to WRITE BC4 OTF with 2tCK Preamble in Same or Different Bank Group 200 Figure 141 READ to PRECHARGE with 1tCK Preamble 201 Figure 142 READ to PRECHARGE with 2tCK Preamble 202 Figure 143 READ to PRECHARGE with Additive Latency and 1tCK Preamble 202 Figure 144 READ with Auto Precharge and 1tCK Preamble 203 Figure 145 READ with Auto Precharge, Additive Latency, and 1tCK Preamble 204 Figure 146 Consecutive READ BL8 with 1tCK Preamble and DBI in Different Bank Group 204 Figure 147 Consecutive READ BL8 with 1tCK Preamble and CA Parity in Different Bank Group 205 Figure 148 READ BL8 to WRITE BL8 with 1tCK Preamble and CA Parity in Same or Different Bank Group 206 Figure 149 READ BL8 to WRITE BL8 or BC4 OTF with 1tCK Preamble and Write CRC in Same or Different Bank Group 207 Figure 150 READ BC4 Fixed to WRITE BC4 Fixed with 1tCK Preamble and Write CRC in Same or Different Bank Group 208 Figure 151 Consecutive READ BL8 with CAL 3tCK and 1tCK Preamble in Different Bank Group 208 Figure 152 Consecutive READ BL8 with CAL 4tCK and 1tCK Preamble in Different Bank Group 209 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved. 4Gb x16 DDR4 SDRAM Features Figure 153 Write Timing Definition 211 Figure 154 Rx Compliance Mask 212 Figure 155 VCENT_DQ VREFDQ Voltage Variation 212 Figure 156 Rx Mask DQ-to-DQS Timings 213 Figure 157 Rx Mask DQ-to-DQS DRAM-Based Timings 214 Figure 158 Example of Data Input Requirements Without Training 215 Figure 159 WRITE Burst Operation, WL = 9 AL = 0, CWL = 9, BL8 216 Burst type BT Data burst ordering within a READ or WRITE burst access 0 = Nibble sequential 1 = Interleave Burst length BL Data burst size associated with each read or write access 00 = BL8 fixed 01 = BC4 or BL8 on-the-fly 10 = BC4 fixed 11 = Reserved Note Not allowed when 1/4 rate gear-down mode is enabled. Burst Length, Type, and Order Accesses within a given burst may be programmed to sequential or interleaved order. The ordering of accesses within a burst is determined by the burst length, burst type, and the starting column address as shown in the following table. Burst length options Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved. 4Gb x16 DDR4 SDRAM Mode Register 0 include fixed BC4, fixed BL8, and on-the-fly OTF , which allows BC4 or BL8 to be selected coincidentally with the registration of a READ or WRITE command via A12/BC_n. Table 7 Burst Type and Burst Order Note 1 applies to the entire table Starting Burst READ/ Column Address Length WRITE A[2, 1, 0] READ WRITE 0, V, V 1, V, V READ WRITE V, V, V Burst Type = Sequential Decimal 0, 1, 2, 3, T, T, T, T 1, 2, 3, 0, T, T, T, T 2, 3, 0, 1, T, T, T, T 3, 0, 1, 2, T, T, T, T 4, 5, 6, 7, T, T, T, T 5, 6, 7, 4, T, T, T, T 6, 7, 4, 5, T, T, T, T 7, 4, 5, 6, T, T, T, T 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 Burst Type = Interleaved Decimal 0, 1, 2, 3, T, T, T, T 1, 0, 3, 2, T, T, T, T 2, 3, 0, 1, T, T, T, T 3, 2, 1, 0, T, T, T, T 4, 5, 6, 7, T, T, T, T 5, 4, 7, 6, T, T, T, T 6, 7, 4, 5, T, T, T, T 7, 6, 5, 4, T, T, T, T 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7 Notes 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 bit number is the value of CA[2:0] that causes this bit to be the first read during a burst. When setting burst length to BC4 fixed in MR0, the internal WRITE operation starts two clock cycles earlier than for the BL8 mode, meaning the starting point for tWR and tWTR will be pulled in by two clocks. When setting burst length to OTF in MR0, the internal WRITE operation starts at the same time as a BL8 even if BC4 was selected during column time using A12/BC4_n meaning that if the OTF MR0 setting is used, the starting point for tWR and tWTR will not be pulled in by two clocks as described in the BC4 fixed case. T = Output driver for data and strobes are in High-Z. V = Valid logic level 0 or 1 , but respective buffer input ignores level on input pins. X = “Don’t Care.” CAS Latency The CAS latency CL setting is defined in the MR0 Register Definition table. CAS latency is the delay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The device does not support half-clock latencies. The Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved. 4Gb x16 DDR4 SDRAM Mode Register 0 overall read latency RL is defined as additive latency AL + CAS latency CL RL = AL + CL. Test Mode The normal operating mode is selected by MR0[7] and all other bits set to the desired values shown in the MR0 Register Definition table. Programming MR0[7] to a value of 1 places the device into a DRAM manufacturer-defined test mode to be used only by the manufacturer, not by the end user. No operations or functionality is specified if MR0[7] = Write Recovery WR /READ-to-PRECHARGE The programmed write recovery WR value is used for the auto precharge feature along with tRP to determine tDAL. WR for auto precharge MIN in clock cycles is calculated by dividing tWR in ns by tCK in ns and rounding up to the next integer WR MIN cycles = roundup tWR[ns]/tCK[ns] . The WR value must be programmed to be equal to or larger than tWR MIN . When both DM and write CRC are enabled in the mode register, the device calculates CRC before sending the write data into the array tWR values will change when enabled. If there is a CRC error, the device blocks the WRITE operation and discards the data. Internal READ-to-PRECHARGE RTP command delay for auto precharge MIN in clock cycles is calculated by dividing tRTP in ns by tCK in ns and rounding up to the next integer RTP MIN cycles = roundup tRTP[ns]/tCK[ns] . The RTP value in the mode register must be programmed to be equal to or larger than RTP MIN . The programmed RTP value is used with tRP to determine the ACT timing to the same bank. DLL RESET The DLL reset bit is self-clearing, meaning that it returns to the value of 0 after the DLL RESET function has been issued. After the DLL is enabled, a subsequent DLL RESET should be applied. Any time the DLL RESET function is used, tDLLK must be met before functions requiring the DLL can be used, such as READ commands or synchronous ODT operations, for example, . Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved. 4Gb x16 DDR4 SDRAM Mode Register 1 Burst Ordering for BL8 DDR4 supports fixed WRITE burst ordering [A2:A1:A0 = 0:0:0] when write CRC is enabled in BL8 fixed . CRC Data Bit Mapping Table 51 CRC Data Mapping for x4 Devices, BL8 Func- Transfer tion DQ0 D0 DQ1 D8 D9 D10 D11 D12 D13 D14 DQ2 D16 D17 D18 D19 D20 D21 D22 DQ3 D24 D25 D26 D27 D28 D29 D30 D7 CRC0 CRC4 D15 CRC1 CRC5 D23 CRC2 CRC6 D31 CRC3 CRC7 Table 52 CRC Data Mapping for x8 Devices, BL8 Func- Transfer tion DQ0 D0 D7 CRC0 1 DQ1 D8 D9 D10 D11 D12 D13 D14 D15 CRC1 1 DQ2 D16 D17 D18 D19 D20 D21 D22 D23 CRC2 1 DQ3 D24 D25 D26 D27 D28 D29 D30 D31 CRC3 1 DQ4 D32 D33 D34 D35 D36 D37 D38 D39 CRC4 1 DQ5 D40 D41 D42 D43 D44 D45 D46 D47 CRC5 1 DQ6 D48 D49 D50 D51 D52 D53 D54 D55 CRC6 1 DQ7 D56 D57 D58 D59 D60 D61 D62 D63 CRC7 1 DM_n/ D64 D65 D66 D67 D68 D69 D70 D71 DBI_n A x16 device is treated as two x8 devices a x16 device will have two identical CRC trees implemented. CRC[7:0] covers data bits D[71:0], and CRC[15:8] covers data bits D[143:72]. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved. 4Gb x16 DDR4 SDRAM CRC Write Data Feature Table 53 CRC Data Mapping for x16 Devices, BL8 Func- Transfer tion DQ0 D0 D7 CRC0 1 DQ1 D8

PDF Datasheet Preview

DDR4 SDRAM

EDY4016A - 256Mb x 16
• VDD = VDDQ = 1.2V ±60mV
• VPP = 2.5V,
• On-die, internal, adjustable VREFDQ generation
• 1.2V pseudo open-drain I/O
• TC of 0°C to 95°C
64ms, 8192-cycle refresh at 0°C to 85°C 32ms at 85°C to 95°C
• 8 internal banks 2 groups of 4 banks each
• 8n-bit prefetch architecture
• Programmable data strobe preambles
• Data strobe preamble training
• Command/Address latency CAL
• Multipurpose register READ and WRITE capability
• Write and read leveling
• Self refresh mode
• Low-power auto self refresh LPASR
• Temperature controlled refresh TCR
• Fine granularity refresh
• Self refresh abort
• Maximum power saving
• Output driver calibration
• Nominal, park, and dynamic on-die termination ODT
• Data bus inversion DBI for data bus
• Command/Address CA parity
4Gb x16 DDR4 SDRAM Features
• Databus write cyclic redundancy check CRC
• Per-DRAM addressability
• Connectivity test
• JEDEC JESD-79-4 compliant

Options1

Marking
• FBGA package size
96-ball 7.5mm x 13.5mm
• Timing cycle time
0.625ns CL = 24 DDR4-3200
0.750ns CL = 19 DDR4-2666
0.833ns CL = 16 DDR4-2400
• Packaging

Lead-free RoHS-compliant and hal- - F
ogen-free

Not all options listed can be combined to define an offered product. Use the part catalog search on for available offerings.

Restricted and limited availability.

Table 1 Key Timing Parameters

Speed Grade -JD1 -GX2 -DR3

Data Rate MT/s 3200 2666 2400

Target tRCD-tRP-CL 24-24-24 19-19-19 16-16-16
tRCD ns
tRP ns

CL ns

Notes Backward compatible to 2666 CL = 20, 2400 CL = 18 , 2133 CL = 16, 1866 CL = 14, 1600 CL = Backward compatible to 2400 CL = 17, 2133 CL = 15, 1866 CL = 13, 1600 CL = Backward compatible to 2133 CL = 15, 1866 CL = 13, 1600 CL =

Table 2 Addressing

Parameter Number of bank groups Bank group address
256 Meg x 16 2

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
4Gb x16 DDR4 SDRAM Features

Table 2 Addressing Continued

Parameter Bank count per group Bank address in bank group Row addressing Column addressing Page size1
256 Meg x 16 4

BA[1:0] 32K A[14:0]
1K A[9:0] 2KB

Note Page size is per bank, calculated as follows Page size = 2COLBITS x ORG/8, where COLBIT = the number of column address bits and ORG = the number of

DQ bits.

Micron Memory Japan DDR4 Part Numbering
PPR Row Repair - Entry 122 PPR Row Repair WRA Initiated REF Commands Allowed 123 PPR Row Repair WR Initiated REF Commands NOT Allowed 124 sPPR Row Repair 126 PPR/sPPR Support Identifier 128 Target Row Refresh Mode 129 ACTIVATE Command 130 PRECHARGE Command 131 REFRESH Command 131 Temperature-Controlled Refresh Mode 133 TCR Mode Normal Temperature Range 133 TCR Mode Extended Temperature Range 133 Fine Granularity Refresh Mode 135 Mode Register and Command Truth Table 135 tREFI and tRFC Parameters 135 Changing Refresh Rate 138 Usage with TCR Mode 138 Self Refresh Entry and Exit 138 SELF REFRESH Operation 140 Self Refresh Abort 142 Self Refresh Exit with NOP Command 143 Power-Down Mode 145 Power-Down Clarifications Case 1 150 Power-Down Entry, Exit Timing with CAL 151 ODT Input Buffer Disable Mode for Power-Down 154 CRC Write Data Feature 156 CRC Write Data 156 WRITE CRC DATA Operation 156 DBI_n and CRC Both Enabled 157 DM_n and CRC Both Enabled 157 DM_n and DBI_n Conflict During Writes with CRC Enabled 157 CRC and Write Preamble Restrictions 157 CRC Simultaneous Operation Restrictions 157 CRC Polynomial 157 CRC Combinatorial Logic Equations 158 Burst Ordering for BL8 159 CRC Data Bit Mapping 159 CRC Enabled With BC4 160 CRC with BC4 Data Bit Mapping 160 CRC Equations for x8 Device in BC4 Mode with A2 = 0 and A2 = 1 163

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved.
4Gb x16 DDR4 SDRAM Features

CRC Error Handling 165 CRC Write Data Flow Diagram 166 Data Bus Inversion 167 DBI During a WRITE Operation 167 DBI During a READ Operation 168 Data Mask 169 Programmable Preamble Modes and DQS Postambles 170 WRITE Preamble Mode 170 READ Preamble Mode 174 READ Preamble Training 174 WRITE Postamble 175 READ Postamble 175 Bank Access Operation 177 READ Operation 181 Read Timing Definitions 181 Read Timing Clock-to-Data Strobe Relationship 182 Read Timing Data Strobe-to-Data Relationship 183 tLZ DQS , tLZ DQ , tHZ DQS , and tHZ DQ Calculations 184 tRPRE Calculation 186 tRPST Calculation 187 READ Burst Operation 188 READ Operation Followed by Another READ Operation 190 READ Operation Followed by WRITE Operation 195 READ Operation Followed by PRECHARGE Operation 201 READ Operation with Read Data Bus Inversion DBI 204 READ Operation with Command/Address Parity CA Parity 205 READ Followed by WRITE with CRC Enabled 207 READ Operation with Command/Address Latency CAL Enabled 208 WRITE Operation 210 Write Timing Definitions 210 Write Timing Clock-to-Data Strobe Relationship 210 Write Timing Data Strobe-to-Data Relationship 211 WRITE Burst Operation 215 WRITE Operation Followed by Another WRITE Operation 217 WRITE Operation Followed by READ Operation 223 WRITE Operation Followed by PRECHARGE Operation 227 WRITE Operation with WRITE DBI Enabled 230 WRITE Operation with CA Parity Enabled 232 WRITE Operation with Write CRC Enabled 233 Write Timing Violations 238 Motivation 238 Data Setup and Hold Violations 238 Strobe-to-Strobe and Strobe-to-Clock Violations 238 ZQ CALIBRATION Commands 239 On-Die Termination 241 ODT Mode Register and ODT State Table 241 ODT Read Disable State Table 242 Synchronous ODT Mode 243 ODT Latency and Posted ODT 243 Timing Parameters 243 ODT During Reads 245 Dynamic ODT 246

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved.
4Gb x16 DDR4 SDRAM Features

Functional Description 246 Asynchronous ODT Mode 249 Electrical Specifications 250

Absolute Ratings 250 DRAM Component Operating Temperature Range 250 Electrical Characteristics AC and DC Operating Conditions 251 Supply Operating Conditions 251 Leakages 251 VREFCA Supply 252 VREFDQ Supply and Calibration Ranges 253 VREFDQ Ranges 254 Electrical Characteristics AC and DC Single-Ended Input Measurement Levels 256 RESET_n Input Levels 256 Command/Address Input Levels 256 Data Receiver Input Requirements 259 Connectivity Test CT Mode Input Levels 262 Electrical Characteristics AC and DC Differential Input Measurement Levels 266 Differential Inputs 266 Single-Ended Requirements for CK Differential Signals 267 Slew Rate Definitions for CK Differential Input Signals 268 CK Differential Input Cross Point Voltage 269 DQS Differential Input Signal Definition and Swing Requirements 271 DQS Differential Input Cross Point Voltage 273 Slew Rate Definitions for DQS Differential Input Signals 274 Electrical Characteristics Overshoot and Undershoot Specifications 276 Address, Command, and Control Overshoot and Undershoot Specifications 276 Clock Overshoot and Undershoot Specifications 276 Data, Strobe, and Mask Overshoot and Undershoot Specifications 277 Electrical Characteristics AC and DC Output Measurement Levels 278 Single-Ended Outputs 278 Differential Outputs 279 Reference Load for AC Timing and Output Slew Rate 281 Connectivity Test Mode Output Levels 281 Electrical Characteristics AC and DC Output Driver Characteristics 284 Output Driver Electrical Characteristics 284 Output Driver Temperature and Voltage Sensitivity 287 Alert Driver 287 Electrical Characteristics On-Die Termination Characteristics 289 ODT Levels and I-V Characteristics 289 ODT Temperature and Voltage Sensitivity 290 ODT Timing Definitions 291 DRAM Package Electrical Specifications 294 Thermal Characteristics 298 Current Specifications Measurement Conditions 299 IDD, IPP, and IDDQ Measurement Conditions 299 IDD Definitions 300 Current Specifications Patterns and Test Conditions 304 Current Test Definitions and Patterns 304 IDD Specifications 313 Current Specifications Limits 314 Speed Bin Tables 316 Refresh Parameters By Device Density 325

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved.
4Gb x16 DDR4 SDRAM Features

Electrical Characteristics and AC Timing Parameters 326 Electrical Characteristics and AC Timing Parameters 2666 Through 3200 338 Timing Parameter Notes 349 Clock Specification 351

Definition for tCK AVG 351 Definition for tCK ABS 351 Definition for tCH AVG and tCL AVG 351 Definition for tJIT per and tJIT per,lck 351 Definition for tJIT cc and tJIT cc,lck 351 Definition for tERR nper 351 Jitter Notes 352 EDY4016 Option and Exception Lists 353 Mode Register Settings 353 Options Tables 354

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved.
4Gb x16 DDR4 SDRAM Features

List of Figures

Figure 1 4Gb DDR4 Part Numbers 2 Figure 2 96-Ball x16 Ball Assignments 19 Figure 3 96-Ball FBGA x16 23 Figure 4 Simplified State Diagram 24 Figure 5 RESET and Initialization Sequence at Power-On Ramping 29 Figure 6 RESET Procedure at Power Stable Condition 30 Figure 7 tMRD Timing 32 Figure 8 tMOD Timing 32 Figure 9 DLL-Off Mode Read Timing Operation 62 Figure 10 DLL Switch Sequence from DLL-On to DLL-Off 64 Figure 11 DLL Switch Sequence from DLL-Off to DLL-On 65 Figure 12 Write-Leveling Concept, Example 1 67 Figure 13 Write-Leveling Concept, Example 2 68 Figure 14 Write-Leveling Sequence DQS Capturing CK LOW at T1 and CK HIGH at T2 70 Figure 15 Write-Leveling Exit 71 Figure 16 CAL Timing Definition 72 Figure 17 CAL Timing Example Consecutive CS_n = LOW 72 Figure 18 CAL Enable Timing tMOD_CAL 73 Figure 19 tMOD_CAL, MRS to Valid Command Timing with CAL Enabled 73 Figure 20 CAL Enabling MRS to Next MRS Command, tMRD_CAL 74 Figure 21 tMRD_CAL, Mode Register Cycle Time With CAL Enabled 74 Figure 22 Consecutive READ BL8, CAL3, 1tCK Preamble, Different Bank Group 75 Figure 23 Consecutive READ BL8, CAL4, 1tCK Preamble, Different Bank Group 75 Figure 24 Auto Self Refresh Ranges 78 Figure 25 MPR Block Diagram 79 Figure 26 MPR READ Timing 86 Figure 27 MPR Back-to-Back READ Timing 86 Figure 28 MPR READ-to-WRITE Timing 88 Figure 29 MPR WRITE and WRITE-to-READ Timing 89 Figure 30 MPR Back-to-Back WRITE Timing 90 Figure 31 REFRESH Timing 90 Figure 32 READ-to-REFRESH Timing 91 Figure 33 WRITE-to-REFRESH Timing 91 Figure 34 Clock Mode Change from 1/2 Rate to 1/4 Rate Initialization 94 Figure 35 Clock Mode Change After Exiting Self Refresh 94 Figure 36 Comparison Between Gear-Down Disable and Gear-Down Enable 95 Figure 37 Maximum Power-Saving Mode Entry 96 Figure 38 Maximum Power-Saving Mode Entry with PDA 97 Figure 39 Maintaining Maximum Power-Saving Mode with CKE Transition 97 Figure 40 Maximum Power-Saving Mode Exit 98 Figure 41 Command/Address Parity Operation 99 Figure 42 Command/Address Parity During Normal Operation 101 Figure 43 Persistent CA Parity Error Checking Operation 102 Figure 44 CA Parity Error Checking SRE Attempt 102 Figure 45 CA Parity Error Checking SRX Attempt 103 Figure 46 CA Parity Error Checking PDE/PDX 103 Figure 47 Parity Entry Timing Example tMRD_PAR 104 Figure 48 Parity Entry Timing Example tMOD_PAR 104 Figure 49 Parity Exit Timing Example tMRD_PAR 105 Figure 50 Parity Exit Timing Example tMOD_PAR 105

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved.
4Gb x16 DDR4 SDRAM Features

Figure 51 CA Parity Flow Diagram 106 Figure 52 PDA Operation Enabled, BL8 108 Figure 53 PDA Operation Enabled, BC4 108 Figure 54 MRS PDA Exit 109 Figure 55 VREFDQ Voltage Range 110 Figure 56 Example of VREF Set Tolerance and Step Size 112 Figure 57 VREFDQ Timing Diagram for VREF,time Parameter 113 Figure 58 VREFDQ Training Mode Entry and Exit Timing Diagram 114 Figure 59 VREF Step Single Step Size Increment Case 115 Figure 60 VREF Step Single Step Size Decrement Case 115 Figure 61 VREF Full Step From VREF,min to VREF,maxCase 116 Figure 62 VREF Full Step From VREF,max to VREF,minCase 116 Figure 63 VREFDQ Equivalent Circuit 117 Figure 64 Connectivity Test Mode Entry 121 Figure 65 PPR WRA Entry 124 Figure 66 PPR WRA Repair and Exit 124 Figure 67 PPR WR Entry 125 Figure 68 PPR WR Repair and Exit 126 Figure 69 sPPR Entry, Repair, and Exit 127 Figure 70 tRRD Timing 130 Figure 71 tFAW Timing 130 Figure 72 REFRESH Command Timing 132 Figure 73 Postponing REFRESH Commands Example 132 Figure 74 Pulling In REFRESH Commands Example 132 Figure 75 TCR Mode Example1 134 Figure 76 4Gb with Fine Granularity Refresh Mode Example 137 Figure 77 OTF REFRESH Command Timing 138 Figure 78 Self Refresh Entry/Exit Timing 141 Figure 79 Self Refresh Entry/Exit Timing with CAL Mode 142 Figure 80 Self Refresh Abort 143 Figure 81 Self Refresh Exit with NOP Command 144 Figure 82 Active Power-Down Entry and Exit 146 Figure 83 Power-Down Entry After Read and Read with Auto Precharge 147 Figure 84 Power-Down Entry After Write and Write with Auto Precharge 147 Figure 85 Power-Down Entry After Write 148 Figure 86 Precharge Power-Down Entry and Exit 148 Figure 87 REFRESH Command to Power-Down Entry 149 Figure 88 Active Command to Power-Down Entry 149 Figure 89 PRECHARGE/PRECHARGE ALL Command to Power-Down Entry 150 Figure 90 MRS Command to Power-Down Entry 150 Figure 91 Power-Down Entry/Exit Clarifications Case 1 151 Figure 92 Active Power-Down Entry and Exit Timing with CAL 152 Figure 93 REFRESH Command to Power-Down Entry with CAL 153 Figure 94 ODT Power-Down Entry with ODT Buffer Disable Mode 154 Figure 95 ODT Power-Down Exit with ODT Buffer Disable Mode 155 Figure 96 CRC Write Data Operation 156 Figure 97 CRC Error Reporting 165 Figure 98 CA Parity Flow Diagram 166 Figure 99 1tCK vs. 2tCK WRITE Preamble Mode 170 Figure 100 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 4 172 Figure 101 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 5 173 Figure 102 1tCK vs. 2 tCK WRITE Preamble Mode, tCCD = 6 173

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved.
4Gb x16 DDR4 SDRAM Features

Figure 103 1tCK vs. 2tCK READ Preamble Mode 174

Figure 104 READ Preamble Training 175

Figure 105 WRITE Postamble 175

Figure 106 READ Postamble 176

Figure 107 Bank Group x4/x8 Block Diagram 177 Figure 108 READ Burst tCCD_S and tCCD_L Examples 178 Figure 109 Write Burst tCCD_S and tCCD_L Examples 178 Figure 110 tRRD Timing 179 Figure 111 tWTR_S Timing WRITE-to-READ, Different Bank Group, CRC and DM Disabled 179 Figure 112 tWTR_L Timing WRITE-to-READ, Same Bank Group, CRC and DM Disabled 180

Figure 113 Read Timing Definition 182

Figure 114 Clock-to-Data Strobe Relationship 183

Figure 115 Data Strobe-to-Data Relationship 184 Figure 116 tLZ and tHZ Method for Calculating Transitions and Endpoints 185 Figure 117 tRPRE Method for Calculating Transitions and Endpoints 186 Figure 118 tRPST Method for Calculating Transitions and Endpoints 187

Figure 119 READ Burst Operation, RL = 11 AL = 0, CL = 11, BL8 188

Figure 120 READ Burst Operation, RL = 21 AL = 10, CL = 11, BL8 189 Figure 121 Consecutive READ BL8 with 1tCK Preamble in Different Bank Group 190 Figure 122 Consecutive READ BL8 with 2tCK Preamble in Different Bank Group 190 Figure 123 Nonconsecutive READ BL8 with 1tCK Preamble in Same or Different Bank Group 191 Figure 124 Nonconsecutive READ BL8 with 2tCK Preamble in Same or Different Bank Group 191 Figure 125 READ BC4 to READ BC4 with 1tCK Preamble in Different Bank Group 192 Figure 126 READ BC4 to READ BC4 with 2tCK Preamble in Different Bank Group 192 Figure 127 READ BL8 to READ BC4 OTF with 1tCK Preamble in Different Bank Group 193 Figure 128 READ BL8 to READ BC4 OTF with 2tCK Preamble in Different Bank Group 193 Figure 129 READ BC4 to READ BL8 OTF with 1tCK Preamble in Different Bank Group 194 Figure 130 READ BC4 to READ BL8 OTF with 2tCK Preamble in Different Bank Group 194 Figure 131 READ BL8 to WRITE BL8 with 1tCK Preamble in Same or Different Bank Group 195 Figure 132 READ BL8 to WRITE BL8 with 2tCK Preamble in Same or Different Bank Group 195 Figure 133 READ BC4 OTF to WRITE BC4 OTF with 1tCK Preamble in Same or Different Bank Group 196 Figure 134 READ BC4 OTF to WRITE BC4 OTF with 2tCK Preamble in Same or Different Bank Group 197 Figure 135 READ BC4 Fixed to WRITE BC4 Fixed with 1tCK Preamble in Same or Different Bank Group 197 Figure 136 READ BC4 Fixed to WRITE BC4 Fixed with 2tCK Preamble in Same or Different Bank Group 198 Figure 137 READ BC4 to WRITE BL8 OTF with 1tCK Preamble in Same or Different Bank Group 199 Figure 138 READ BC4 to WRITE BL8 OTF with 2tCK Preamble in Same or Different Bank Group 199 Figure 139 READ BL8 to WRITE BC4 OTF with 1tCK Preamble in Same or Different Bank Group 200 Figure 140 READ BL8 to WRITE BC4 OTF with 2tCK Preamble in Same or Different Bank Group 200 Figure 141 READ to PRECHARGE with 1tCK Preamble 201 Figure 142 READ to PRECHARGE with 2tCK Preamble 202 Figure 143 READ to PRECHARGE with Additive Latency and 1tCK Preamble 202 Figure 144 READ with Auto Precharge and 1tCK Preamble 203 Figure 145 READ with Auto Precharge, Additive Latency, and 1tCK Preamble 204 Figure 146 Consecutive READ BL8 with 1tCK Preamble and DBI in Different Bank Group 204 Figure 147 Consecutive READ BL8 with 1tCK Preamble and CA Parity in Different Bank Group 205 Figure 148 READ BL8 to WRITE BL8 with 1tCK Preamble and CA Parity in Same or Different Bank Group 206 Figure 149 READ BL8 to WRITE BL8 or BC4 OTF with 1tCK Preamble and Write CRC in Same or Different

Bank Group 207 Figure 150 READ BC4 Fixed to WRITE BC4 Fixed with 1tCK Preamble and Write CRC in Same or Different

Bank Group 208 Figure 151 Consecutive READ BL8 with CAL 3tCK and 1tCK Preamble in Different Bank Group 208 Figure 152 Consecutive READ BL8 with CAL 4tCK and 1tCK Preamble in Different Bank Group 209

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved.
4Gb x16 DDR4 SDRAM Features

Figure 153 Write Timing Definition 211

Figure 154 Rx Compliance Mask 212

Figure 155 VCENT_DQ VREFDQ Voltage Variation 212 Figure 156 Rx Mask DQ-to-DQS Timings 213

Figure 157 Rx Mask DQ-to-DQS DRAM-Based Timings 214

Figure 158 Example of Data Input Requirements Without Training 215

Figure 159 WRITE Burst Operation, WL = 9 AL = 0, CWL = 9, BL8 216
Burst type BT Data burst ordering within a READ or WRITE burst access 0 = Nibble sequential 1 = Interleave

Burst length BL Data burst size associated with each read or write access 00 = BL8 fixed 01 = BC4 or BL8 on-the-fly 10 = BC4 fixed 11 = Reserved

Note Not allowed when 1/4 rate gear-down mode is enabled.

Burst Length, Type, and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The ordering of accesses within a burst is determined by the burst length, burst type, and the starting column address as shown in the following table. Burst length options

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved.
4Gb x16 DDR4 SDRAM Mode Register 0
include fixed BC4, fixed BL8, and on-the-fly OTF , which allows BC4 or BL8 to be selected coincidentally with the registration of a READ or WRITE command via A12/BC_n.

Table 7 Burst Type and Burst Order

Note 1 applies to the entire table

Starting

Burst

READ/ Column Address

Length

WRITE

A[2, 1, 0]

READ

WRITE
0, V, V
1, V, V

READ

WRITE

V, V, V

Burst Type = Sequential Decimal
0, 1, 2, 3, T, T, T, T 1, 2, 3, 0, T, T, T, T 2, 3, 0, 1, T, T, T, T 3, 0, 1, 2, T, T, T, T 4, 5, 6, 7, T, T, T, T 5, 6, 7, 4, T, T, T, T 6, 7, 4, 5, T, T, T, T 7, 4, 5, 6, T, T, T, T 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7

Burst Type = Interleaved Decimal
0, 1, 2, 3, T, T, T, T 1, 0, 3, 2, T, T, T, T 2, 3, 0, 1, T, T, T, T 3, 2, 1, 0, T, T, T, T 4, 5, 6, 7, T, T, T, T 5, 4, 7, 6, T, T, T, T 6, 7, 4, 5, T, T, T, T 7, 6, 5, 4, T, T, T, T 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7

Notes 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3
bit number is the value of CA[2:0] that causes this bit to be the first read during a burst.

When setting burst length to BC4 fixed in MR0, the internal WRITE operation starts two clock cycles earlier than for the BL8 mode, meaning the starting point for tWR and tWTR will be pulled in by two clocks. When setting burst length to OTF in MR0, the internal WRITE operation starts at the same time as a BL8 even if BC4 was selected during column time using A12/BC4_n meaning that if the OTF MR0 setting is used, the starting point for tWR and tWTR will not be pulled in by two clocks as described in the BC4 fixed case.

T = Output driver for data and strobes are in High-Z. V = Valid logic level 0 or 1 , but respective buffer input ignores level on input pins. X = “Don’t Care.”

CAS Latency

The CAS latency CL setting is defined in the MR0 Register Definition table. CAS latency is the delay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The device does not support half-clock latencies. The

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved.
4Gb x16 DDR4 SDRAM Mode Register 0
overall read latency RL is defined as additive latency AL + CAS latency CL RL = AL + CL.

Test Mode

The normal operating mode is selected by MR0[7] and all other bits set to the desired values shown in the MR0 Register Definition table. Programming MR0[7] to a value of 1 places the device into a DRAM manufacturer-defined test mode to be used only by the manufacturer, not by the end user. No operations or functionality is specified if MR0[7] =

Write Recovery WR /READ-to-PRECHARGE

The programmed write recovery WR value is used for the auto precharge feature along with tRP to determine tDAL. WR for auto precharge MIN in clock cycles is calculated by dividing tWR in ns by tCK in ns and rounding up to the next integer WR MIN cycles = roundup tWR[ns]/tCK[ns] . The WR value must be programmed to be equal to or larger than tWR MIN . When both DM and write CRC are enabled in the mode register, the device calculates CRC before sending the write data into the array tWR values will change when enabled. If there is a CRC error, the device blocks the WRITE operation and discards the data.

Internal READ-to-PRECHARGE RTP command delay for auto precharge MIN in clock cycles is calculated by dividing tRTP in ns by tCK in ns and rounding up to the next integer RTP MIN cycles = roundup tRTP[ns]/tCK[ns] . The RTP value in the mode register must be programmed to be equal to or larger than RTP MIN . The programmed RTP value is used with tRP to determine the ACT timing to the same bank.

DLL RESET

The DLL reset bit is self-clearing, meaning that it returns to the value of 0 after the DLL RESET function has been issued. After the DLL is enabled, a subsequent DLL RESET should be applied. Any time the DLL RESET function is used, tDLLK must be met before functions requiring the DLL can be used, such as READ commands or synchronous ODT operations, for example, .

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved.
4Gb x16 DDR4 SDRAM Mode Register 1
Burst Ordering for BL8
DDR4 supports fixed WRITE burst ordering [A2:A1:A0 = 0:0:0] when write CRC is enabled in BL8 fixed .

CRC Data Bit Mapping

Table 51 CRC Data Mapping for x4 Devices, BL8

Func-

Transfer
tion

DQ0 D0

DQ1 D8

D9 D10 D11 D12 D13 D14

DQ2 D16 D17 D18 D19 D20 D21 D22

DQ3 D24 D25 D26 D27 D28 D29 D30

D7 CRC0 CRC4

D15 CRC1 CRC5

D23 CRC2 CRC6

D31 CRC3 CRC7

Table 52 CRC Data Mapping for x8 Devices, BL8

Func-

Transfer
tion

DQ0 D0

D7 CRC0 1

DQ1 D8

D9 D10 D11 D12 D13 D14 D15 CRC1 1

DQ2 D16 D17 D18 D19 D20 D21 D22 D23 CRC2 1

DQ3 D24 D25 D26 D27 D28 D29 D30 D31 CRC3 1

DQ4 D32 D33 D34 D35 D36 D37 D38 D39 CRC4 1

DQ5 D40 D41 D42 D43 D44 D45 D46 D47 CRC5 1

DQ6 D48 D49 D50 D51 D52 D53 D54 D55 CRC6 1

DQ7 D56 D57 D58 D59 D60 D61 D62 D63 CRC7 1

DM_n/ D64 D65 D66 D67 D68 D69 D70 D71

DBI_n

A x16 device is treated as two x8 devices a x16 device will have two identical CRC trees implemented. CRC[7:0] covers data bits D[71:0], and CRC[15:8] covers data bits D[143:72].

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved.
4Gb x16 DDR4 SDRAM CRC Write Data Feature

Table 53 CRC Data Mapping for x16 Devices, BL8

Func-

Transfer
tion

DQ0 D0

D7 CRC0 1

DQ1 D8

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived EDY4016AABG-GX-F-D Datasheet file may be downloaded here without warranties.

Datasheet ID: EDY4016AABG-GX-F-D 648273