EDW2032BBBG-7A-F-R TR

EDW2032BBBG-7A-F-R TR Datasheet

EDW2032BBBG 4 Meg x 32 I/O x 16 banks, 8 Meg x 16 I/O x 16 banks

Part	Datasheet
EDW2032BBBG-7A-F-R TR	EDW2032BBBG-7A-F-R TR (pdf)

Related Parts	Information
EDW2032BBBG-6A-F-D	EDW2032BBBG-6A-F-D
EDW2032BBBG-50-F-R TR	EDW2032BBBG-50-F-R TR
EDW2032BBBG-7A-F-D	EDW2032BBBG-7A-F-D
EDW2032BBBG-50-F-D	EDW2032BBBG-50-F-D
EDW2032BBBG-6A-F-R TR	EDW2032BBBG-6A-F-R TR

PDF Datasheet Preview
2Gb x16, x32 GDDR5 SGRAM Features GDDR5 SGRAM EDW2032BBBG 4 Meg x 32 I/O x 16 banks, 8 Meg x 16 I/O x 16 banks • VDD = VDDQ = 1.6V/1.5V ±3% and 1.35V ±3% • Data rate Gb/s, Gb/s, Gb/s MAX • 16 internal banks • Four bank groups for tCCDL = 3 tCK • 8n-bit prefetch architecture 256-bit per array read or write access for x32 128-bit for x16 • Burst length BL 8 only • Programmable CAS latency • Programmable WRITE latency • Programmable CRC READ latency • Programmable CRC WRITE latency • Programmable EDC hold pattern for CDR • Precharge Auto option for each burst access • Auto refresh and self refresh modes • Refresh cycles 16,384 cycles/32ms • Interface Pseudo open drain POD-15 compatible outputs 40Ω pull-down, 60Ω pull-up • On-die termination ODT 60Ω or 120Ω NOM • ODT and output driver strength auto calibration with external resistor ZQ pin 120Ω • Programmable termination and driver strength off- sets • Selectable external or internal VREF for data inputs; programmable offsets for internal VREF • Separate external VREF for address/command in- puts • TC = 0°C to +95°C • x32/x16 mode configuration set at power-up with EDC pin • Single-ended interface for data, address, and com- mand • Quarter data rate differential clock inputs CK_t, CK_c for address and commands • Two half data rate differential clock inputs, WCK_t and WCK_c, each associated with two data bytes DQ, DBI_n, EDC • DDR data WCK and addressing CK • SDR command CK • Write data mask function via address bus single/ double byte mask • Data bus inversion DBI and address bus inversion ABI • Input/output PLL on/off mode • Duty cycle corrector DCC for data clock WCK • Address training Address input monitoring via DQ pins • WCK2CK clock training Phase information via EDC pins • Data read and write training via read FIFO depth = 6 • Read FIFO pattern preloaded by LDFF command • Direct write data load to read FIFO by WRTR com- mand • Consecutive read of read FIFO by RDTR command • Read/write data transmission integrity secured by cyclic redundancy check CRC-8 • Read/write EDC on/off mode • Low power modes • RDQS mode on EDC pin • On-die temperature sensor with readout • Automatic temperature sensor controlled self refresh rate • Digital RAS lockout • Vendor ID, FIFO depth and density info fields for identification • Mirror function with MF pin • Boundary scan function with SEN pin Options1 • Organization Density 64 Meg x 32 words x bits • FBGA package 170-ball 12mm x 14mm • Package environment code Lead- and halogen-free RoHS-compliant • Package media Dry pack tray Reel • Timing Cycle time Gb/s, Gb/s Gb/s, Gb/s Gb/s, Gb/s • Operating temperature Commercial 0°C TC +95°C Marking 20 32 -D -R -50 -6A -7A None B Note: Not all options listed can be combined to define an offered product. Use the part catalog search on for available offerings. Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 2Gb x16, x32 GDDR5 SGRAM Features Table 1 Addressing Parameter Configuration Refresh count Refresh period Row addressing Bank addressing Column addressing Auto precharge Page size

PDF Datasheet Preview

2Gb x16, x32 GDDR5 SGRAM Features

GDDR5 SGRAM

EDW2032BBBG 4 Meg x 32 I/O x 16 banks, 8 Meg x 16 I/O x 16 banks
• VDD = VDDQ = 1.6V/1.5V ±3% and 1.35V ±3%
• Data rate Gb/s, Gb/s, Gb/s MAX
• 16 internal banks
• Four bank groups for tCCDL = 3 tCK
• 8n-bit prefetch architecture 256-bit per array read
or write access for x32 128-bit for x16
• Burst length BL 8 only
• Programmable CAS latency
• Programmable WRITE latency
• Programmable CRC READ latency
• Programmable CRC WRITE latency
• Programmable EDC hold pattern for CDR
• Precharge Auto option for each burst access
• Auto refresh and self refresh modes
• Refresh cycles 16,384 cycles/32ms
• Interface Pseudo open drain POD-15 compatible
outputs 40Ω pull-down, 60Ω pull-up
• On-die termination ODT 60Ω or 120Ω NOM
• ODT and output driver strength auto calibration
with external resistor ZQ pin 120Ω
• Programmable termination and driver strength off-
sets
• Selectable external or internal VREF for data inputs;
programmable offsets for internal VREF
• Separate external VREF for address/command in-
puts
• TC = 0°C to +95°C
• x32/x16 mode configuration set at power-up with

EDC pin
• Single-ended interface for data, address, and com-
mand
• Quarter data rate differential clock inputs CK_t,

CK_c for address and commands
• Two half data rate differential clock inputs, WCK_t
and WCK_c, each associated with two data bytes DQ, DBI_n, EDC
• DDR data WCK and addressing CK
• SDR command CK
• Write data mask function via address bus single/ double byte mask
• Data bus inversion DBI and address bus inversion ABI
• Input/output PLL on/off mode
• Duty cycle corrector DCC for data clock WCK
• Address training Address input monitoring via DQ pins
• WCK2CK clock training Phase information via EDC pins
• Data read and write training via read FIFO depth = 6
• Read FIFO pattern preloaded by LDFF command
• Direct write data load to read FIFO by WRTR com-
mand
• Consecutive read of read FIFO by RDTR command
• Read/write data transmission integrity secured by
cyclic redundancy check CRC-8
• Read/write EDC on/off mode
• Low power modes
• RDQS mode on EDC pin
• On-die temperature sensor with readout
• Automatic temperature sensor controlled self
refresh rate
• Digital RAS lockout
• Vendor ID, FIFO depth and density info fields for
identification
• Mirror function with MF pin
• Boundary scan function with SEN pin

Options1
• Organization Density 64 Meg x 32 words x bits
• FBGA package 170-ball 12mm x 14mm
• Package environment code Lead- and halogen-free RoHS-compliant
• Package media Dry pack tray Reel
• Timing Cycle time Gb/s, Gb/s Gb/s, Gb/s Gb/s, Gb/s
• Operating temperature Commercial 0°C TC +95°C

Marking
20 32
-D -R
-50 -6A -7A

None B

Note:

Not all options listed can be combined to define an offered product. Use the part catalog search on for available offerings.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 2014 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
2Gb x16, x32 GDDR5 SGRAM Features

Table 1 Addressing

Parameter Configuration Refresh count Refresh period Row addressing Bank addressing Column addressing Auto precharge Page size

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived EDW2032BBBG-7A-F-RTR Datasheet file may be downloaded here without warranties.

Datasheet ID: EDW2032BBBG-7A-F-RTR 648272