RD38F1020C0ZTL0SB93

RD38F1020C0ZTL0SB93 Datasheet

RD3 8 F 1 0 1 0 C0 Z T L 0

Part	Datasheet
RD38F1020C0ZTL0SB93	RD38F1020C0ZTL0SB93 (pdf)

Related Parts	Information
RD38F1020C0ZBL0SB93	RD38F1020C0ZBL0SB93
RD28F1604C3BD70A	RD28F1604C3BD70A
RD28F1604C3TD70SB93	RD28F1604C3TD70SB93

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Advanced+ Boot Block Flash Memory C3 SCSP Family Datasheet Product Features • Flash Memory Plus SRAM Reduces Memory Board Space Required, Simplifying PCB Design Complexity • SCSP Technology Smallest Memory Subsystem Footprint Area 8 x 10 mm for 16 Mbit µm Flash + 2 Mbit or 4 Mbit SRAM Area 8 x 12 mm for 32 Mbit µm Flash + 4 Mbit or 8 Mbit SRAM Height mm for 16 Mbit µm Flash + 2 Mbit or 4 Mbit SRAM, and 32 Mbit 0.13um Flash + 8 Mbit SRAM Height mm for 32 Mbit µm Flash + 4 Mbit SRAM This Family also includes µm, µm, and µm technologies • Advanced SRAM Technology 70 ns Access Time Low Power Operation Low Voltage Data Retention Mode • Flash Data Integrator FDI Software Real-Time Data Storage and Code Execution in the Same Memory Device Full Flash File Manager Capability • Advanced+ Boot Block Flash Memory ns Access Time Individual Block Locking bit Protection Register V Production Programming Program and Erase Suspend Temperature °C to +85 °C • Blocking Architecture Sizes for Code + Data Storage Parameter Blocks Main Blocks Erase Cycles per Block • Low Power Operation Read Current 9 mA Flash Current 7 µA Flash Power Saving Mode • Flash Technologies µm ETOX VI, µm ETOX VII and µm ETOX VIII Flash Technologies The Advanced+ Boot Block Flash Memory C3 Stacked Chip Scale Package SCSP device delivers a feature-rich solution for low-power applications. The C3 SCSP memory device incorporates flash memory and static RAM in one package with low voltage capability to achieve the smallest system memory solution form-factor together with high-speed, low-power operations. The C3 SCSP memory device offers a protection register and flexible block locking to enable next generation security capability. Combined with the Flash Data Integrator FDI software, the C3 SCSP memory device provides a cost-effective, flexible, code plus data storage solution. INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH PRODUCTS. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. The Advanced+ Boot Block Flash Memory C3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at Intel, the Intel logo, Intel StrataFlash, and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 2005, Intel Corporation. All rights reserved. 26 Aug 2005 2 Datasheet C3 SCSP Flash Memory Contents Document Conventions 6 Product Overview Package Ballout 8 Signal Definitions 9 Principles of Operation Bus Operation 11 Read Output Disable 12 13 Flash 13 Write Flash Memory Modes of Read Array FFh 14 Read Identifier 90h 14 Read Status Register 70h 15 Clear Status Register 50h 16 CFI Query 98h 16 Word Program 40h/10h 16 Suspending and Resuming Program Block Erase 20h Suspending and Resuming Erase B0h/D0h 18 Block Block Locking Operation 21 Locked State 21 Unlocked State 21 Lock-Down State 21 Reading Lock Status for a 22 Locking Operation During Erase Suspend 22 Status Register Error Checking 22 128 Bit Protection Register Reading the Protection Register 23 Programming the Protection Register 24 Locking the Protection Register 24 Power and Reset Considerations 25 Power-Up/Down Characteristics 25 Additional Flash Features 25 Improved 12 Volt Production Programming F-VPP VPPLK for Complete Protection 25 Electrical Specifications 26 Absolute Maximum Ratings 26 Operating Conditions 27 Capacitance 27 Datasheet 26 Aug 2005 3 C3 SCSP Flash Memory DC 28 Flash AC Characteristics. 32 Flash AC 33 Flash Erase and Program 34 Flash Reset Operations 36 SRAM AC 37 SRAM AC Operations 38 SRAM Data Retention Temperature 40 Migration Guide Information 41 System Design 41 41 Flash + SRAM Footprint Integration 41 C3 Flash Memory Features 42 Flash Control Considerations 42 F-RP# Connected to System 42 F-VCC, F-VPP and F-RP# Transition 42 Noise Reduction 43 Simultaneous Operation 44 SRAM Operation during Flash “Busy” 45 Simultaneous Bus Operations 45 Printed Circuit Board Notes 45 System Design Notes 45 A Program/Erase Flowcharts 46 B CFI Query Structure 52 B.1 Query Structure 52 B.2 Query Structure Overview 53 B.3 Block Lock Status 54 B.4 CFI Query Identification 54 B.5 System Interface 55 B.6 Device Geometry Definition 56 B.7 Intel-Specific Extended Query Table 57 C Word-Wide Memory Map Diagrams 59 D Device ID Table 66 E Protection Register Addressing 67 F Mechanical and Shipping Media 68 F.8 Mechanical Specification 68 F.9 Media Information 71 G Additional 73 H Ordering 74 26 Aug 2005 4 Datasheet C3 SCSP Flash Memory 02/11/03 01/29/04 03/05 26 Aug 2005 Version -001 -002 -003 -004 Initial release, Stacked Chip Scale Package Minor text edits. Updated Ordering Information figures and table in Appendix H. Updated Ordering Information to add PF28F1602C3TD70. Datasheet 26 Aug 2005 5 C3 SCSP Flash Memory Introduction This document contains the specifications for the Advanced+ Boot Block Flash Memory C3 Stacked Chip Scale Package SCSP device. C3 SCSP memory solutions are offered in the following combinations: • 32-Mbit flash + 8-Mbit SRAM • 32-Mbit flash + 4-Mbit SRAM • 16-Mbit flash + 4-Mbit SRAM • 16-Mbit flash memory + 2-Mbit SRAM Document Conventions Throughout this document, the following conventions have been adopted. • Voltages: V refers to the full voltage range, 12 V refers to V to V • Main block s 32-Kword block • Parameter block s 4-Kword block Table Product Overview The C3 SCSP device combines flash memory and SRAM into a single package, which provides secure low-voltage memory solutions for portable applications. The flash memory provides the following features: • Enhanced security. • Instant locking/unlocking of any flash block with zero-latency • A 128-bit protection register that enables unique device identification, to meet the needs of next generation portable applications. • Improved 12 V production programming for increased factory throughput. Block Organization x16 Memory Device 32-Mbit Flash 16-Mbit Flash 2-Mbit SRAM 4-Mbit SRAM 8-Mbit SRAM Note All words are 16 bits each. Kwords 2048 1024 128 256 512 26 Aug 2005 6 Datasheet C3 SCSP Flash Memory The flash memory is asymmetrically-blocked to enable system integration of code and data storage in a single device. Each flash block can be erased independently of the others up to 100,000 times. The flash memory has eight 8-KB parameter blocks located at either the top denoted by -T suffix or the bottom -B suffix of the address map, to accommodate different microprocessor protocols for kernel code location. The remaining flash memory is grouped into 32-Kword main blocks. Any individual flash memory block can be locked or unlocked instantly to provide complete protection for code or data see Section “Flash Erase and Program Timings 1 ” on page 34 for details . The flash memory contains both a Command User Interface CUI and a Write State Machine WSM . • The CUI is the interface between the microcontroller and the internal operation of the flash memory. • The internal WSM automatically executes the algorithms and timings necessary for program and erase operations, including verification, thereby unburdening the microprocessor or microcontroller. To indicate the status of the WSM, the flash memory status register signifies block erase or word program completion and status. Flash program and erase automation enables executing program and erase operations using an industry-standard two-write command sequence to the CUI. • Program operations are performed in word increments. • Erase operations erase all locations within a block simultaneously. The system software can suspend both program and erase operations to read from any other flash block. In addition, data can be programmed to another flash block during an erase suspend. The C3 SCSP memory device offers two low-power savings features to significantly reduce power consumption: Appendix H Ordering Information Table Ordering Information for Product Combinations with µm to µm Flash RD2 8 F 1 6 0 2C3 TD7 0 Table Package RD = Leaded Ball Stacked -CSP PF = Lead-Free Ball Stacked-CSP Product Line Designator 28F or 38F = Flash Memory Flash Density 320 = x16 32 Mbit 160 = x16 16 Mbit SRAM Device Density 8 = x16 8 Mbit 4 = x16 4 Mbit 2 = x16 2 Mbit Access Speed ns 16 Mbit = 70, 90, or 110 ns 32 Mbit = 70 or 90 ns Technology Differentiator D = 0.13µm <blank> = 0.25µm or 0.18µm refer to access speed for differientation Parameter Location T = Top Blocking B = Bottom Blocking Product Family C = Advanced+ Boot Block Flash Memory Ordering Information for Combinations specific to 32M µm Flash RD3 8 F 1 0 1 0 C0 Z T L 0 Package RD = Leaded Ball Stacked-CSP PF = Lead-Free Ball Stacked-CSP Product Line Designator 38F = Flash Stacked Memory Density Flash #1 = 1 = 32 Mbit Flash #2 = 0 = No Die Flash #3 = 1 = 4 Mbit SRAM =2 = 8 Mbit SRAM Flash #4 = 0 = No Die Product Family C = Advanced+ Boot Block Flash Memory Device Details 0 = Original Version of this product Flash Speed = 70 ns Flash Process = µm Vccq = V to V Pinout Indicator L = 72 ball "I"-ballout Parameter Location T = Top Blocking B = Bottom Blocking Voltage Z = V I/O 26 Aug 2005 74 Datasheet C3 SCSP Flash Memory Table Ordering Information Valid Combinations 32-Mbit 16-Mbit 0.25µm C3 SCSP No longer available. RD28F1604C3T90 RD28F1604C3B90 RD28F1604C3T110 RD28F1604C3B110 RD28F1602C3T90 RD28F1602C3B90 RD28F1602C3T110 RD28F1602C3B110 0.18µm C3 SCSP RD28F3208C3T70 RD28F3208C3B70 RD28F3208C3T90 RD28F3208C3B90 RD28F3204C3T70 RD28F3204C3B70 RD28F1602C3T70 RD28F1602C3B70 0.13µm C3 SCSP RD38F1010C0ZTL0 RD38F1010C0ZBL0 PF38F1010C0ZTL0 PF38F1010C0ZBL0 RD38F1020C0ZTL0 RD38F1020C0ZBL0 PF28F1602C3TD70 RD28F1602C3TD70 RD28F1602C3BD70 RD28F1604C3TD70 RD28F1604C3BD70 Datasheet 26 Aug 2005 75

PDF Datasheet Preview

Advanced+ Boot Block Flash Memory C3

SCSP Family

Datasheet

Product Features
• Flash Memory Plus SRAM Reduces Memory Board Space Required, Simplifying PCB Design Complexity
• SCSP Technology Smallest Memory Subsystem Footprint

Area 8 x 10 mm for 16 Mbit µm Flash + 2 Mbit or 4 Mbit SRAM

Area 8 x 12 mm for 32 Mbit µm Flash + 4 Mbit or 8 Mbit SRAM

Height mm for 16 Mbit µm Flash + 2 Mbit or 4 Mbit SRAM, and 32 Mbit 0.13um Flash + 8 Mbit SRAM

Height mm for 32 Mbit µm Flash + 4 Mbit SRAM

This Family also includes µm, µm, and µm technologies
• Advanced SRAM Technology 70 ns Access Time

Low Power Operation

Low Voltage Data Retention Mode
• Flash Data Integrator FDI

Software Real-Time Data Storage and Code

Execution in the Same Memory Device

Full Flash File Manager Capability
• Advanced+ Boot Block Flash Memory ns Access Time Individual Block Locking bit Protection Register V Production Programming Program and Erase Suspend Temperature °C to +85 °C
• Blocking Architecture Sizes for Code + Data Storage Parameter Blocks Main Blocks Erase Cycles per Block
• Low Power Operation Read Current 9 mA Flash Current 7 µA Flash Power Saving Mode
• Flash Technologies µm ETOX VI, µm ETOX VII and µm ETOX VIII Flash Technologies

The Advanced+ Boot Block Flash Memory C3 Stacked Chip Scale Package SCSP device delivers a feature-rich solution for low-power applications. The C3 SCSP memory device incorporates flash memory and static RAM in one package with low voltage capability to achieve the smallest system memory solution form-factor together with high-speed, low-power operations. The C3 SCSP memory device offers a protection register and flexible block locking to enable next generation security capability. Combined with the Flash Data Integrator FDI software, the C3 SCSP memory device provides a cost-effective, flexible, code plus data storage solution.

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH PRODUCTS. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT.

Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Intel may make changes to specifications and product descriptions at any time, without notice. The Advanced+ Boot Block Flash Memory C3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at

Intel, the Intel logo, Intel StrataFlash, and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.

Copyright 2005, Intel Corporation. All rights reserved.
26 Aug 2005 2

Datasheet

C3 SCSP Flash Memory

Contents

Document Conventions 6 Product Overview Package Ballout 8 Signal Definitions 9

Principles of Operation

Bus Operation 11 Read Output Disable 12 13 Flash 13 Write

Flash Memory Modes of

Read Array FFh 14 Read Identifier 90h 14 Read Status Register 70h 15

Clear Status Register 50h 16 CFI Query 98h 16 Word Program 40h/10h 16

Suspending and Resuming Program Block Erase 20h

Suspending and Resuming Erase B0h/D0h 18 Block

Block Locking Operation 21 Locked State 21 Unlocked State 21 Lock-Down State 21 Reading Lock Status for a 22 Locking Operation During Erase Suspend 22 Status Register Error Checking 22 128 Bit Protection Register Reading the Protection Register 23 Programming the Protection Register 24 Locking the Protection Register 24

Power and Reset Considerations 25

Power-Up/Down Characteristics 25 Additional Flash Features 25

Improved 12 Volt Production Programming F-VPP VPPLK for Complete Protection 25

Electrical Specifications 26

Absolute Maximum Ratings 26 Operating Conditions 27 Capacitance 27

Datasheet
26 Aug 2005 3

C3 SCSP Flash Memory

DC 28 Flash AC Characteristics. 32 Flash AC 33 Flash Erase and Program 34 Flash Reset Operations 36 SRAM AC 37 SRAM AC Operations 38 SRAM Data Retention Temperature 40

Migration Guide Information 41

System Design 41
41 Flash + SRAM Footprint Integration 41 C3 Flash Memory Features 42

Flash Control Considerations 42 F-RP# Connected to System 42 F-VCC, F-VPP and F-RP# Transition 42

Noise Reduction 43 Simultaneous Operation 44

SRAM Operation during Flash “Busy” 45 Simultaneous Bus Operations 45 Printed Circuit Board Notes 45 System Design Notes 45

A Program/Erase Flowcharts 46

B CFI Query Structure 52

B.1 Query Structure 52 B.2 Query Structure Overview 53 B.3 Block Lock Status 54 B.4 CFI Query Identification 54 B.5 System Interface 55 B.6 Device Geometry Definition 56 B.7 Intel-Specific Extended Query Table 57

C Word-Wide Memory Map Diagrams 59

D Device ID Table 66

E Protection Register Addressing 67

F Mechanical and Shipping Media 68

F.8 Mechanical Specification 68 F.9 Media Information 71

G Additional 73
H Ordering 74
26 Aug 2005 4

Datasheet

C3 SCSP Flash Memory
02/11/03 01/29/04
03/05 26 Aug 2005

Version
-001 -002 -003 -004
Initial release, Stacked Chip Scale Package Minor text edits. Updated Ordering Information figures and table in Appendix H. Updated Ordering Information to add PF28F1602C3TD70.

Datasheet
26 Aug 2005 5

C3 SCSP Flash Memory

Introduction

This document contains the specifications for the Advanced+ Boot Block Flash Memory C3 Stacked Chip Scale Package SCSP device. C3 SCSP memory solutions are offered in the following combinations:
• 32-Mbit flash + 8-Mbit SRAM
• 32-Mbit flash + 4-Mbit SRAM
• 16-Mbit flash + 4-Mbit SRAM
• 16-Mbit flash memory + 2-Mbit SRAM

Document Conventions

Throughout this document, the following conventions have been adopted.
• Voltages:

V refers to the full voltage range, 12 V refers to V to V
• Main block s 32-Kword block
• Parameter block s 4-Kword block

Table

Product Overview

The C3 SCSP device combines flash memory and SRAM into a single package, which provides secure low-voltage memory solutions for portable applications.

The flash memory provides the following features:
• Enhanced security.
• Instant locking/unlocking of any flash block with zero-latency
• A 128-bit protection register that enables unique device identification, to meet the needs of
next generation portable applications.
• Improved 12 V production programming for increased factory throughput.

Block Organization x16

Memory Device 32-Mbit Flash 16-Mbit Flash 2-Mbit SRAM 4-Mbit SRAM 8-Mbit SRAM Note All words are 16 bits each.

Kwords 2048 1024 128 256 512
26 Aug 2005 6

Datasheet

C3 SCSP Flash Memory

The flash memory is asymmetrically-blocked to enable system integration of code and data storage in a single device. Each flash block can be erased independently of the others up to 100,000 times.

The flash memory has eight 8-KB parameter blocks located at either the top denoted by -T suffix or the bottom -B suffix of the address map, to accommodate different microprocessor protocols for kernel code location.

The remaining flash memory is grouped into 32-Kword main blocks.

Any individual flash memory block can be locked or unlocked instantly to provide complete protection for code or data see Section “Flash Erase and Program Timings 1 ” on page 34 for details .

The flash memory contains both a Command User Interface CUI and a Write State Machine WSM .
• The CUI is the interface between the microcontroller and the internal operation of the flash
memory.
• The internal WSM automatically executes the algorithms and timings necessary for program
and erase operations, including verification, thereby unburdening the microprocessor or microcontroller. To indicate the status of the WSM, the flash memory status register signifies block erase or word program completion and status.

Flash program and erase automation enables executing program and erase operations using an industry-standard two-write command sequence to the CUI.
• Program operations are performed in word increments.
• Erase operations erase all locations within a block simultaneously.

The system software can suspend both program and erase operations to read from any other flash block. In addition, data can be programmed to another flash block during an erase suspend.

The C3 SCSP memory device offers two low-power savings features to significantly reduce power consumption:
Appendix H Ordering Information

Table
Ordering Information for Product Combinations with µm to µm Flash

RD2 8 F 1 6 0 2C3 TD7 0

Table

Package

RD = Leaded Ball Stacked -CSP PF = Lead-Free Ball Stacked-CSP

Product Line Designator
28F or 38F = Flash Memory

Flash Density
320 = x16 32 Mbit 160 = x16 16 Mbit

SRAM Device Density
8 = x16 8 Mbit 4 = x16 4 Mbit 2 = x16 2 Mbit

Access Speed ns
16 Mbit = 70, 90, or 110 ns 32 Mbit = 70 or 90 ns

Technology Differentiator

D = 0.13µm <blank> = 0.25µm or 0.18µm refer to access speed for differientation

Parameter Location

T = Top Blocking B = Bottom Blocking

Product Family

C = Advanced+ Boot Block Flash Memory
Ordering Information for Combinations specific to 32M µm Flash

RD3 8 F 1 0 1 0 C0 Z T L 0

Package

RD = Leaded Ball Stacked-CSP PF = Lead-Free Ball Stacked-CSP

Product Line Designator 38F = Flash Stacked Memory

Density

Flash #1 = 1 = 32 Mbit Flash #2 = 0 = No Die Flash #3 = 1 = 4 Mbit SRAM
=2 = 8 Mbit SRAM Flash #4 = 0 = No Die

Product Family

C = Advanced+ Boot Block Flash Memory

Device Details
0 = Original Version of this product Flash Speed = 70 ns Flash Process = µm Vccq = V to V

Pinout Indicator

L = 72 ball "I"-ballout

Parameter Location

T = Top Blocking B = Bottom Blocking

Voltage

Z = V I/O
26 Aug 2005 74

Datasheet

C3 SCSP Flash Memory

Table
Ordering Information Valid Combinations
32-Mbit 16-Mbit
0.25µm C3 SCSP

No longer available.

RD28F1604C3T90 RD28F1604C3B90 RD28F1604C3T110 RD28F1604C3B110 RD28F1602C3T90 RD28F1602C3B90 RD28F1602C3T110 RD28F1602C3B110
0.18µm C3 SCSP RD28F3208C3T70 RD28F3208C3B70 RD28F3208C3T90 RD28F3208C3B90 RD28F3204C3T70 RD28F3204C3B70

RD28F1602C3T70 RD28F1602C3B70
0.13µm C3 SCSP

RD38F1010C0ZTL0 RD38F1010C0ZBL0 PF38F1010C0ZTL0 PF38F1010C0ZBL0 RD38F1020C0ZTL0 RD38F1020C0ZBL0

PF28F1602C3TD70 RD28F1602C3TD70 RD28F1602C3BD70 RD28F1604C3TD70 RD28F1604C3BD70

Datasheet
26 Aug 2005 75

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Datasheet ID: RD38F1020C0ZTL0SB93 638920