RC28F256K3C120

RC28F256K3C120 Datasheet

RC28F640K3C110 RC28F640K18C110 RC28F128K3C115 RC28F128K18C115 RC28F256K3C120 RC28F256K18C120

Part	Datasheet
RC28F256K3C120	RC28F256K3C120 (pdf)

PDF Datasheet Preview
Intel Synchronous Memory K3/K18 28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18 x16 Datasheet Product Features • Performance 110/115/120 ns Initial Access Speed for 64/128/256 Mbit Densities 25 ns Asynchronous Page-Mode Reads, 8 Words Wide 13 ns Synchronous Burst-Mode Reads, 8 or 16 Words Wide 32-Word Write Buffer Buffered Enhanced Factory Programming • Software 25 µs typ. Program and Erase Suspend Latency Time Flash Data Integrator FDI , Common Flash Interface CFI Compatible Programmable WAIT Signal Polarity • Quality and Reliability Operating Temperature °C to +85 °C 100K Minimum Erase Cycles per Block µm ETOX VII Process • Architecture Multi-Level Cell Technology High Density at Low Cost Symmetrical 64 K-Word Blocks 256 Mbit 256 Blocks 128 Mbit 128 Blocks 64 Mbit 64 Blocks Ideal for “CODE + DATA” applications • Security 2-Kbit Protection Register Unique 64-bit Device Identifier Absolute Data Protection with VPEN and WP# Individual and Instantaneous Block Locking, Unlocking and Lock-Down Capability • Packaging and Voltage 64-Ball Easy BGA Package 128-Mbit is also offered in a lead-free package 56-and 79-Ball VF BGA Package VCC = V to V VCCQ = to V/2.375 to V The Intel Synchronous Memory K3/K18 product line adds a high performance burst-mode interface and other additional features to the Intel memory family of products. Just like its J3 counterpart, the K3/K18 device utilizes reliable and proven two-bit-percell technology to deliver 2x the memory in 1x the space, offering high density flash at low cost. This is Intel’s third generation MLC technology, manufactured on µm lithography, making it the most widely used and proven MLC product family on the market. K3/K18 is a 3-volt device core , but it is available with 3-volt K3 or 1.8-volt K18 I/O voltages. These devices are ideal for mainstream applications requiring large storage space for both code and data storage. Advanced system designs will benefit from the high performance page and burst modes for direct execution from the flash memory. Available in densities from 64 Mbit to 256 Mbit 32 Mbyte , the K3/K18 device is the highest density NOR-based flash component available today, just as it was when Intel introduced the original device in Notice This document contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Order Number 290737-009 February 2005 Information in this document is provided in connection with products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 3 Volt Synchronous Intel Memory may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at Copyright Intel Corporation, Other names and brands may be claimed as the property of others. Datasheet 28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18 Contents Introduction Nomenclature Conventions Functional Overview High Performance Page/Burst Single Chip Solution Packaging Options Product Highlights K3/K18 Block Diagram Memory Map Package Information Easy BGA VF BGA for 64 Mbit and 128 Mbit Package VF BGA for 256 Mbit Package Ballout and Signal 64-Ball Easy BGA Package for All Densities mm Ball Pitch 56-Ball VF BGA Package for 64- and 128-Mbit Density mm Ball Pitch 79-Ball VF BGA for 256-Mbit Density Signal Maximum Ratings and Operating Conditions Absolute Maximum Operating Electrical DC Current Characteristics Read Operations Write Operation Block Erase and Program Operation Performance AC Test Conditions Capacitance Power and Power-Up/Down Characteristics Power Supply Decoupling Reset Characteristics Reset Operation Bus Operations Bus Operations Read Mode Write/Program Datasheet 28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18 Output Disable 36 Standby 36 Reset 36 Device Commands 37 Read 39 Asynchronous Page-Mode Read 39 Synchronous Burst-Mode Read 40 Read Configuration Register 40 Read 41 Latency Count 41 WAIT Polarity 43 Data Hold 43 WAIT Delay 44 Burst 44 Clock Edge 44 Burst Length 44 Program 45 Word Programming 45 Write-Buffer Programming 45 Program Suspend 46 Program Resume 47 Buffered Enhanced Factory Programming 47 Buffered-EFP Requirements and Considerations 47 Buffered-EFP Setup Phase 48 Buffered-EFP Program and Verify Phase 48 Buffered-EFP Exit Phase 49 Erase Mode 50 Block Erase 50 Erase 50 Erase Resume 51 Security Modes 52 Block Locking Operations 52 Block Lock 53 Block Unlock 53 Block Lock-Down 53 Block Lock During Erase 53 WP# Lock-Down Control 53 Protection Registers 54 Reading the Protection Registers 55 Programming the Protection Registers 55 Locking the Protection Registers 55 Array Protection 55 Special Modes 56 Read Status Register 56 Clear Status Register 57 Read Device Identifier 57 Appendix A Write State Machine 59 Appendix B Common Flash Interface 64 Appendix C 70 Appendix D Additional Information 78 Appendix E Ordering Information 79 Datasheet 28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18 02/22/02 06/17/02 06/11/03 12/01/03 5/19/04 2/1/05 -001 -002 -003 -004 -005 -006 -007 -008 -009 Datasheet 28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18 Introduction This document contains information pertaining to the Intel Synchronous Memory K3/K18 device. The purpose of this document is to describe the features, operations and specifications of these devices. Nomenclature 3 Volt core 3 Volt I/O Volt I/O AMIN: AMAX: Block Program VPEN CUI OTP PR PLR RFU SR RCR WSM MLC Set Clear: VCC range of V VCCQ range of V VCCQ range of V For Easy BGA packages AMIN = A1 For VF BGA packages AMIN = A0 For Easy BGA packages: 64 Mbit AMAX = A22 128 Mbit AMAX = A23 256 Mbit AMAX = A24 For VF BGA packages: 64 Mbit AMAX = A21 128 Mbit AMAX = A22 256 Mbit AMAX = A23 A group of flash cells that share common erase circuitry and erase simultaneously To write data to the flash array Refers to a signal or package connection name Refers to timing or voltage levels Command User Interface One Time Programmable Protection Register Protection Lock Register Reserved for Future Use Status Register Read Configuration Register Write State Machine Multi-Level Cell Indicates a logic one 1 Indicates a logic zero 0 Datasheet 28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18 Conventions 0x 0b k noun M noun Byte Word Kword Kb Mb Brackets: Hexadecimal prefix Binary prefix 1,000 1,000,000 8 bits 16 bits 1,024 words 1,024 bits 1,024 bytes 1,048,576 bits 1,048,576 bytes Square brackets [] will be used to designate group membership or to define a group of signals with similar function i.e. A[21:1], SR[4,1] and D[15:0] . Datasheet 28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18 Functional Overview This section provides an overview of the K3/K18 device features and architecture. The K3/K18 device product line adds a high performance burst-mode interface and other additional features to the Intel memory family of products. Just like its J3 counterpart, the K3/K18 utilizes reliable and proven two-bit-per-cell technology to deliver 2x the memory in 1x the space, offering high density flash at low cost. This is the third generation of Intel's multi-level cell MLC technology, manufactured on µm lithography, making it the most widely used and proven MLC product family on the market. K3/K18 is a 3-volt device core , but it is available with 3-volt K3 or 1.8-volt K18 I/O voltages. These devices are ideal for mainstream applications requiring large storage space for both code and data storage. Advanced system designs will benefit from the high performance page and burst modes for direct execution from the flash memory. Available in densities from 64 Mb to 256 Mbit 32 Mbyte , the K3/K18 device is the highest density NOR-based flash component available today, just as it was when Intel introduced the original device in High Performance Page/Burst Modes NOR-based flash is generally preferred over other architectures for its reliability and fast read speeds. Fast reads allow the application to execute code directly out of flash, rather than downloading to RAM for execution, saving the costs of redundant system memory and board space. The K3/K18 device sets the standard for fast read speeds by adding burst mode and utilizing an 8 word page mode. Burst mode increases throughput up to 76MB/s, effectively five times faster than asynchronous reads on standard flash memory, and supports performance up to 66 Mhz with zero wait states. Both page and burst modes also provide a high performance glueless interface to the StrongARM SA-1110 CPU and future XScale processors and many other microprocessors. Single Chip Solution In addition to code execution, many applications also have data storage needs. K3/K18 memory provides a single-chip solution for combined code execution and data storage. A single-chip solution is easy to implement by utilizing a unique hardware and software combination the K3/ K18 device and Persistent Storage Manager PSM . PSM is royalty free when used with Flash, is an installable file system and block device driver for Microsoft Windows* CE OS version and later. The PSM software is appropriate for any application using the Microsoft Windows CE operating system, including PC Companions, Set-Top Boxes, and other connected appliances and hand-held devices. Other operating system ports are also available. PSM is optimized for the Intel Memory product line. Table Burst Sequence Word Ordering Start Addr. DEC 0 1 2 3 4 5 6 7 Burst Addressing Sequence DEC 8-Word Burst BL[2:0] = 010 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 16-Word Burst BL[2:0] = 011 Clock Edge The Clock Edge CE bit selects either a rising default or falling clock edge for CLK. This is the clock edge that is used at the start of a burst cycle to output synchronous data and to assert/deassert WAIT. Burst Length BL[2:0] selects the linear burst length for all synchronous burst reads of the flash memory. The burst length can be configured to be an 8-word or a 16-word burst. Once a burst cycle begins, the device will output synchronous burst data until it reaches the end of the burstable address space. Datasheet 28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18 Program Modes The device supports three different programming methods Word Programming, Write-Buffer Programming, and Buffered Enhanced Factory Programming or Buffered-EFP. Successful programming requires the addressed block to be unlocked. If the block is locked down, WP# must be de-asserted and the block unlocked before attempting to program the array. An attempt to program a locked block will result in the operation aborting, and SR[1] and SR[4] being set, indicating a programming error. The following sections describe device programming in detail. Word Programming Word Programming is performed by executing the Word Program command. Word Programming is a non-buffered operation and programs one word to the flash array based on the initial program address A[AMAX:AMIN]. To determine the status of a word-program operation, poll the status register and analyze the bits. If the flash device is put in standby mode during a program operation, the device will continue to program the word until the operation is complete then the device will enter standby mode. Refer to Figure 26, “Word Programming Flowchart” on page 71 for a detailed flow on how to implement a word program operation. During programming, the Write State Machine executes a sequence of internally-timed events that program the desired data bits and verifies that the bits are sufficiently programmed. Programming the flash memory array changes “ones” to “zeros.” Memory array bits that are zeros can be changed to ones only by erasing the block. When programming has finished, Status Register bit SR4 set indicates a programming failure. If SR3 is set, this indicates that the Write State Machine could not perform the Word Programming operation because VPEN was outside of its acceptable limits. If SR1 is set, the Word Programming operation had attempted to program a locked block, causing the operation to abort. After examining the status register, it should be cleared using the Clear Status Register command before issuing a new command. Any valid command can follow, after Word Programming has completed. Write-Buffer Programming The device features a 32-word Write Buffer to allow optimum programming performance. For Write-Buffer Programming, data is first written to an on-chip write buffer, then programmed into the flash memory array in buffer-size increments. Optimal performance is realized when programming is buffer-size aligned to the 32-word write-buffer boundary. The write-buffer is directly mapped to the flash array through A[AMIN+4:AMIN]. Unaligned buffered writes will decrease program performance. Buffered writes can improve system programming performance more than 20X over non write-buffer programming. To perform Write-Buffer Programming, the Write-to-Buffer Setup command, 0xE8, is issued along with the block address see Section “Device Commands” on page Status Register information is updated, and a read from the block address will return Status Register data showing the write buffer’s availability. Note Do not issue the Read Status Register command during this sequence. SR7 indicates the availability of the write buffer for loading data. If SR7 is set, the write Datasheet 28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18 buffer is available if not set, the write buffer is not available. To retry, issue the Write-to-Buffer Setup command again, and re-check SR7. When SR7 is set, the write buffer is available. See Figure 25, “Write to Buffer Flowchart” on page Next, a word count actual word count - 1 is written to the device at the buffer address. This tells the device how many data words will be written to the write buffer, up to the maximum size of the write buffer. The valid range of values for word count is 0x00 to 0x1F. On the next write, a device start address is given along with the first data to be written to the flash memory array. Subsequent writes provide additional device addresses and data. All data addresses must lie within the start address plus the word count. Maximum programming performance and lower power are obtained by aligning the starting address at the beginning of a 32 word boundary. A misaligned starting address will result in a doubling of the total program time. After the last data is written to the write buffer, the Write-to-Buffer Confirm command is issued. The Write State Machine begins to copy the write buffer contents to the flash memory array. If a command other than the Write-to-Buffer Confirm command is written to the device, a command sequence error will occur and Status Register bits SR4, SR5 and SR7 will be set. If an error occurs while writing to the array, the device will stop programming, and Status Register bit SR4 and SR7 will be set, indicating a programming failure. Additional buffer writes can be initiated by issuing another Write-to-Buffer Setup command and repeating the write-to-buffer sequence. Anytime SR4 and SR5 are set, the device will not accept Write-to-Buffer commands. If an attempt is made to program past a block boundary using the Write-to-Buffer command, the device will abort the operation. This will generate a command sequence error, and Status Register bits SR4 and SR5 will be set. If Write-Buffer Programming is attempted while VPEN is below VPENLK, Status Register bits SR3 and SR4 will be set. If any errors are detected that have set Status Register bits, the Status Register should be cleared using the Clear Status Register command. Program Suspend To execute a program suspend, execute the Program Suspend command. A suspend operation halts any in-progress programming operation. The Suspend command can be written to any device address. A Suspend command allows data to be accessed from any memory location other than those suspended. A program operation can be suspended to perform a device read. A program operation nested within an erase suspend operation can be suspended to read the flash device. Once the program process starts, a suspend operation can only occur at certain points in the program algorithm. Erase suspend operations cannot resume until program operations initiated during the erase suspend are complete. All device read functions are permitted during a suspend operation. During a suspend, VPEN must remain at a valid program level and WP# must not change. Also, a minimum amount of time is required between issuing a Program or Erase command and then issuing a Suspend command. Datasheet 28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18 Program Resume To resume i.e., continue a program suspend operation, execute the Program Resume command. The Resume command can be written to any device address. When a program operation is nested within an erase suspend operation and the Program Suspend command is issued, the device will suspend the program operation. When the Resume command is issued, the device will resume and complete the program operation. Once the nested program operation is completed, an additional Resume command is required to complete the block erase operation. The device supports a maximum suspend/resume of two nested routines. See Figure 27, “Program Suspend/Resume Flowchart” on page Buffered Enhanced Factory Programming Buffered-EFP Appendix E Ordering Information RC 28F 128 K 18 C 115 Package Designator, Extended Temperature -40C to +85C GE = mm VF BGA RC = Easy BGA PC = 64-ball PB-free Easy BGA Product line designator for all Flash Products Density 640 = 64 Mbit 8-MB x16 128 = 128 Mbit 16-MB x16 256 = 256 Mbit 32-MB x16 Access Speed ns 64 Mbit = 110 128 Mbit = 115 256 Mbit = 120 Process Identifier C = 0.18um Voltage Identifer VCC / V CCQ 3 = - 3.6V / - 3.6V 18 = - 3.6V / 1.65-1.95V Product Family K = 3 Volt Synchronous Intel Memory Table Valid Combinations Density VF BGA 64 Mbit 128 Mbit 256 Mbit GE28F640K3C110 GE28F640K18C110 GE28F128K3C115 GE28F128K18C115 GE28F256K3C120 GE28F256K18C120 Easy BGA RC28F640K3C110 RC28F640K18C110 RC28F128K3C115 RC28F128K18C115 RC28F256K3C120 RC28F256K18C120 Lead-free Easy BGA Not Available PC 28F128K3C115 144 PC Tray Not Available Datasheet 28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18 Datasheet

PDF Datasheet Preview

Intel Synchronous Memory K3/K18
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18 x16

Datasheet

Product Features
• Performance 110/115/120 ns Initial Access Speed for 64/128/256 Mbit Densities 25 ns Asynchronous Page-Mode Reads, 8 Words Wide 13 ns Synchronous Burst-Mode Reads, 8 or 16 Words Wide 32-Word Write Buffer Buffered Enhanced Factory Programming
• Software 25 µs typ. Program and Erase Suspend Latency Time Flash Data Integrator FDI , Common Flash Interface CFI Compatible Programmable WAIT Signal Polarity
• Quality and Reliability Operating Temperature °C to +85 °C 100K Minimum Erase Cycles per Block µm ETOX VII Process
• Architecture Multi-Level Cell Technology High Density at Low Cost Symmetrical 64 K-Word Blocks 256 Mbit 256 Blocks 128 Mbit 128 Blocks 64 Mbit 64 Blocks Ideal for “CODE + DATA” applications
• Security 2-Kbit Protection Register Unique 64-bit Device Identifier Absolute Data Protection with VPEN and WP# Individual and Instantaneous Block Locking, Unlocking and Lock-Down Capability
• Packaging and Voltage 64-Ball Easy BGA Package 128-Mbit is also offered in a lead-free package 56-and 79-Ball VF BGA Package VCC = V to V VCCQ = to V/2.375 to V

The Intel Synchronous Memory K3/K18 product line adds a high performance burst-mode interface and other additional features to the Intel memory family of products. Just like its J3 counterpart, the K3/K18 device utilizes reliable and proven two-bit-percell technology to deliver 2x the memory in 1x the space, offering high density flash at low cost. This is Intel’s third generation MLC technology, manufactured on µm lithography, making it the most widely used and proven MLC product family on the market.

K3/K18 is a 3-volt device core , but it is available with 3-volt K3 or 1.8-volt K18 I/O voltages. These devices are ideal for mainstream applications requiring large storage space for both code and data storage. Advanced system designs will benefit from the high performance page and burst modes for direct execution from the flash memory. Available in densities from 64 Mbit to 256 Mbit 32 Mbyte , the K3/K18 device is the highest density NOR-based flash component available today, just as it was when Intel introduced the original device in

Notice This document contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.

Order Number 290737-009 February 2005

Information in this document is provided in connection with products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 3 Volt Synchronous Intel Memory may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at

Copyright Intel Corporation,
*Other names and brands may be claimed as the property of others.

Datasheet
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18

Contents

Introduction

Nomenclature Conventions

Functional Overview

High Performance Page/Burst Single Chip Solution Packaging Options Product Highlights K3/K18 Block Diagram Memory Map

Package Information

Easy BGA VF BGA for 64 Mbit and 128 Mbit Package VF BGA for 256 Mbit Package

Ballout and Signal
64-Ball Easy BGA Package for All Densities mm Ball Pitch 56-Ball VF BGA Package for 64- and 128-Mbit Density mm Ball Pitch 79-Ball VF BGA for 256-Mbit Density Signal

Maximum Ratings and Operating Conditions

Absolute Maximum Operating

Electrical

DC Current Characteristics

Read Operations Write Operation Block Erase and Program Operation Performance AC Test Conditions Capacitance

Power and

Power-Up/Down Characteristics Power Supply Decoupling Reset Characteristics Reset Operation

Bus Operations

Bus Operations Read Mode Write/Program

Datasheet
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18

Output Disable 36 Standby 36 Reset 36 Device Commands 37

Read 39

Asynchronous Page-Mode Read 39 Synchronous Burst-Mode Read 40 Read Configuration Register 40

Read 41 Latency Count 41 WAIT Polarity 43 Data Hold 43 WAIT Delay 44 Burst 44 Clock Edge 44 Burst Length 44

Program 45

Word Programming 45 Write-Buffer Programming 45 Program Suspend 46 Program Resume 47 Buffered Enhanced Factory Programming 47

Buffered-EFP Requirements and Considerations 47 Buffered-EFP Setup Phase 48 Buffered-EFP Program and Verify Phase 48 Buffered-EFP Exit Phase 49

Erase Mode 50

Block Erase 50 Erase 50 Erase Resume 51

Security Modes 52

Block Locking Operations 52 Block Lock 53 Block Unlock 53 Block Lock-Down 53 Block Lock During Erase 53 WP# Lock-Down Control 53

Protection Registers 54 Reading the Protection Registers 55 Programming the Protection Registers 55 Locking the Protection Registers 55

Array Protection 55

Special Modes 56

Read Status Register 56 Clear Status Register 57

Read Device Identifier 57
Appendix A Write State Machine 59 Appendix B Common Flash Interface 64 Appendix C 70 Appendix D Additional Information 78 Appendix E Ordering Information 79

Datasheet
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
02/22/02 06/17/02 06/11/03
12/01/03 5/19/04 2/1/05
-001 -002 -003
-004 -005 -006
-007 -008 -009
Datasheet
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18

Introduction

This document contains information pertaining to the Intel Synchronous Memory K3/K18 device. The purpose of this document is to describe the features, operations and specifications of these devices.

Nomenclature
3 Volt core 3 Volt I/O Volt I/O AMIN:

AMAX:

Block Program VPEN CUI OTP PR PLR RFU SR RCR WSM MLC Set Clear:

VCC range of V VCCQ range of V VCCQ range of V For Easy BGA packages AMIN = A1 For VF BGA packages AMIN = A0 For Easy BGA packages:
64 Mbit AMAX = A22 128 Mbit AMAX = A23 256 Mbit AMAX = A24 For VF BGA packages:
64 Mbit AMAX = A21 128 Mbit AMAX = A22 256 Mbit AMAX = A23 A group of flash cells that share common erase circuitry and erase simultaneously

To write data to the flash array

Refers to a signal or package connection name

Refers to timing or voltage levels

Command User Interface

One Time Programmable

Protection Register

Protection Lock Register

Reserved for Future Use

Status Register

Read Configuration Register

Write State Machine

Multi-Level Cell

Indicates a logic one 1

Indicates a logic zero 0

Datasheet
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18

Conventions
0x 0b k noun M noun Byte Word Kword Kb Mb Brackets:

Hexadecimal prefix Binary prefix 1,000 1,000,000 8 bits 16 bits 1,024 words 1,024 bits 1,024 bytes 1,048,576 bits 1,048,576 bytes Square brackets [] will be used to designate group membership or to define a group of signals with similar function i.e. A[21:1], SR[4,1] and D[15:0] .

Datasheet
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18

Functional Overview

This section provides an overview of the K3/K18 device features and architecture.

The K3/K18 device product line adds a high performance burst-mode interface and other additional features to the Intel memory family of products. Just like its J3 counterpart, the K3/K18 utilizes reliable and proven two-bit-per-cell technology to deliver 2x the memory in 1x the space, offering high density flash at low cost. This is the third generation of Intel's multi-level cell MLC technology, manufactured on µm lithography, making it the most widely used and proven MLC product family on the market.

K3/K18 is a 3-volt device core , but it is available with 3-volt K3 or 1.8-volt K18 I/O voltages. These devices are ideal for mainstream applications requiring large storage space for both code and data storage. Advanced system designs will benefit from the high performance page and burst modes for direct execution from the flash memory. Available in densities from 64 Mb to 256 Mbit 32 Mbyte , the K3/K18 device is the highest density NOR-based flash component available today, just as it was when Intel introduced the original device in

High Performance Page/Burst Modes

NOR-based flash is generally preferred over other architectures for its reliability and fast read speeds. Fast reads allow the application to execute code directly out of flash, rather than downloading to RAM for execution, saving the costs of redundant system memory and board space. The K3/K18 device sets the standard for fast read speeds by adding burst mode and utilizing an 8 word page mode. Burst mode increases throughput up to 76MB/s, effectively five times faster than asynchronous reads on standard flash memory, and supports performance up to 66 Mhz with zero wait states. Both page and burst modes also provide a high performance glueless interface to the StrongARM* SA-1110 CPU and future XScale processors and many other microprocessors.

Single Chip Solution

In addition to code execution, many applications also have data storage needs. K3/K18 memory provides a single-chip solution for combined code execution and data storage. A single-chip solution is easy to implement by utilizing a unique hardware and software combination the K3/ K18 device and Persistent Storage Manager PSM . PSM is royalty free when used with Flash, is an installable file system and block device driver for Microsoft Windows* CE OS version and later.

The PSM software is appropriate for any application using the Microsoft Windows CE operating system, including PC Companions, Set-Top Boxes, and other connected appliances and hand-held devices. Other operating system ports are also available. PSM is optimized for the Intel Memory product line.
Table Burst Sequence Word Ordering

Start Addr. DEC
0 1 2 3 4 5 6 7

Burst Addressing Sequence DEC
8-Word Burst BL[2:0] = 010
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
16-Word Burst BL[2:0] = 011

Clock Edge

The Clock Edge CE bit selects either a rising default or falling clock edge for CLK. This is the clock edge that is used at the start of a burst cycle to output synchronous data and to assert/deassert WAIT.

Burst Length

BL[2:0] selects the linear burst length for all synchronous burst reads of the flash memory. The burst length can be configured to be an 8-word or a 16-word burst. Once a burst cycle begins, the device will output synchronous burst data until it reaches the end of the burstable address space.

Datasheet
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18

Program Modes

The device supports three different programming methods Word Programming, Write-Buffer Programming, and Buffered Enhanced Factory Programming or Buffered-EFP. Successful programming requires the addressed block to be unlocked. If the block is locked down, WP# must be de-asserted and the block unlocked before attempting to program the array. An attempt to program a locked block will result in the operation aborting, and SR[1] and SR[4] being set, indicating a programming error. The following sections describe device programming in detail.

Word Programming

Word Programming is performed by executing the Word Program command. Word Programming is a non-buffered operation and programs one word to the flash array based on the initial program address A[AMAX:AMIN]. To determine the status of a word-program operation, poll the status register and analyze the bits. If the flash device is put in standby mode during a program operation, the device will continue to program the word until the operation is complete then the device will enter standby mode. Refer to Figure 26, “Word Programming Flowchart” on page 71 for a detailed flow on how to implement a word program operation.

During programming, the Write State Machine executes a sequence of internally-timed events that program the desired data bits and verifies that the bits are sufficiently programmed. Programming the flash memory array changes “ones” to “zeros.” Memory array bits that are zeros can be changed to ones only by erasing the block.

When programming has finished, Status Register bit SR4 set indicates a programming failure. If SR3 is set, this indicates that the Write State Machine could not perform the Word Programming operation because VPEN was outside of its acceptable limits. If SR1 is set, the Word Programming operation had attempted to program a locked block, causing the operation to abort.

After examining the status register, it should be cleared using the Clear Status Register command before issuing a new command. Any valid command can follow, after Word Programming has completed.

Write-Buffer Programming

The device features a 32-word Write Buffer to allow optimum programming performance. For Write-Buffer Programming, data is first written to an on-chip write buffer, then programmed into the flash memory array in buffer-size increments. Optimal performance is realized when programming is buffer-size aligned to the 32-word write-buffer boundary. The write-buffer is directly mapped to the flash array through A[AMIN+4:AMIN]. Unaligned buffered writes will decrease program performance. Buffered writes can improve system programming performance more than 20X over non write-buffer programming.

To perform Write-Buffer Programming, the Write-to-Buffer Setup command, 0xE8, is issued along with the block address see Section “Device Commands” on page Status Register information is updated, and a read from the block address will return Status Register data showing the write buffer’s availability. Note Do not issue the Read Status Register command during this sequence. SR7 indicates the availability of the write buffer for loading data. If SR7 is set, the write

Datasheet
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
buffer is available if not set, the write buffer is not available. To retry, issue the Write-to-Buffer Setup command again, and re-check SR7. When SR7 is set, the write buffer is available. See Figure 25, “Write to Buffer Flowchart” on page

Next, a word count actual word count - 1 is written to the device at the buffer address. This tells the device how many data words will be written to the write buffer, up to the maximum size of the write buffer. The valid range of values for word count is 0x00 to 0x1F.

On the next write, a device start address is given along with the first data to be written to the flash memory array. Subsequent writes provide additional device addresses and data. All data addresses must lie within the start address plus the word count. Maximum programming performance and lower power are obtained by aligning the starting address at the beginning of a 32 word boundary. A misaligned starting address will result in a doubling of the total program time.

After the last data is written to the write buffer, the Write-to-Buffer Confirm command is issued. The Write State Machine begins to copy the write buffer contents to the flash memory array. If a command other than the Write-to-Buffer Confirm command is written to the device, a command sequence error will occur and Status Register bits SR4, SR5 and SR7 will be set. If an error occurs while writing to the array, the device will stop programming, and Status Register bit SR4 and SR7 will be set, indicating a programming failure.

Additional buffer writes can be initiated by issuing another Write-to-Buffer Setup command and repeating the write-to-buffer sequence.

Anytime SR4 and SR5 are set, the device will not accept Write-to-Buffer commands. If an attempt is made to program past a block boundary using the Write-to-Buffer command, the device will abort the operation. This will generate a command sequence error, and Status Register bits SR4 and SR5 will be set.

If Write-Buffer Programming is attempted while VPEN is below VPENLK, Status Register bits SR3 and SR4 will be set. If any errors are detected that have set Status Register bits, the Status Register should be cleared using the Clear Status Register command.

Program Suspend

To execute a program suspend, execute the Program Suspend command. A suspend operation halts any in-progress programming operation. The Suspend command can be written to any device address. A Suspend command allows data to be accessed from any memory location other than those suspended.

A program operation can be suspended to perform a device read. A program operation nested within an erase suspend operation can be suspended to read the flash device. Once the program process starts, a suspend operation can only occur at certain points in the program algorithm. Erase suspend operations cannot resume until program operations initiated during the erase suspend are complete. All device read functions are permitted during a suspend operation.

During a suspend, VPEN must remain at a valid program level and WP# must not change. Also, a minimum amount of time is required between issuing a Program or Erase command and then issuing a Suspend command.

Datasheet
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18

Program Resume

To resume i.e., continue a program suspend operation, execute the Program Resume command. The Resume command can be written to any device address. When a program operation is nested within an erase suspend operation and the Program Suspend command is issued, the device will suspend the program operation. When the Resume command is issued, the device will resume and complete the program operation. Once the nested program operation is completed, an additional Resume command is required to complete the block erase operation. The device supports a maximum suspend/resume of two nested routines. See Figure 27, “Program Suspend/Resume Flowchart” on page

Buffered Enhanced Factory Programming Buffered-EFP
Appendix E Ordering Information

RC 28F 128 K 18 C 115

Package Designator, Extended Temperature -40C to +85C GE = mm VF BGA RC = Easy BGA PC = 64-ball PB-free Easy BGA

Product line designator for all Flash Products

Density 640 = 64 Mbit 8-MB x16 128 = 128 Mbit 16-MB x16 256 = 256 Mbit 32-MB x16

Access Speed ns 64 Mbit = 110
128 Mbit = 115 256 Mbit = 120

Process Identifier C = 0.18um

Voltage Identifer VCC / V CCQ 3 = - 3.6V / - 3.6V 18 = - 3.6V / 1.65-1.95V

Product Family K = 3 Volt Synchronous Intel

Memory

Table Valid Combinations

Density

VF BGA
64 Mbit 128 Mbit 256 Mbit

GE28F640K3C110 GE28F640K18C110

GE28F128K3C115 GE28F128K18C115

GE28F256K3C120 GE28F256K18C120

Easy BGA

RC28F640K3C110 RC28F640K18C110 RC28F128K3C115 RC28F128K18C115 RC28F256K3C120 RC28F256K18C120

Lead-free Easy BGA

Not Available

PC 28F128K3C115 144 PC Tray

Not Available

Datasheet
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18

Datasheet

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived RC28F256K3C120 Datasheet file may be downloaded here without warranties.

Datasheet ID: RC28F256K3C120 638918