SST39WF1602-90-4I-MBQE

SST39WF1602-90-4I-MBQE Datasheet

SST39WF1601 / SST39WF1602

Part	Datasheet
SST39WF1602-90-4I-MBQE	SST39WF1602-90-4I-MBQE (pdf)

Related Parts	Information
SST39WF1601-90-4C-MBQE	SST39WF1601-90-4C-MBQE
SST39WF1601-90-4I-B3KE-T	SST39WF1601-90-4I-B3KE-T
SST39WF1601-90-4I-MBQE-T	SST39WF1601-90-4I-MBQE-T
SST39WF1602-90-4C-MBQE	SST39WF1602-90-4C-MBQE
SST39WF1602-90-4I-B3KE	SST39WF1602-90-4I-B3KE
SST39WF1601-90-4I-MBQE	SST39WF1601-90-4I-MBQE
SST39WF1602-90-4C-B3KE	SST39WF1602-90-4C-B3KE
SST39WF1601-90-4C-B3KE	SST39WF1601-90-4C-B3KE
SST39WF1601-90-4C-B3KE-T	SST39WF1601-90-4C-B3KE-T
SST39WF1601-90-4I-B3KE	SST39WF1601-90-4I-B3KE

PDF Datasheet Preview
16 Mbit x16 Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 FEATURES: SST39WF160x2.7V 16Mb x16 MPF+ memories Data Sheet • Organized as 1M x16 • Single Voltage Read and Write Operations 1.65-1.95V • Superior Reliability Endurance 100,000 Cycles Typical Greater than 100 years Data Retention • Low Power Consumption typical values at 5 MHz Active Current 5 mA typical Standby Current 5 µA typical Auto Low Power Mode 5 µA typical • Hardware Block-Protection/WP# Input Pin Top Block-Protection top 32 KWord for SST39WF1602 Bottom Block-Protection bottom 32 KWord for SST39WF1601 • Sector-Erase Capability Uniform 2 KWord sectors • Block-Erase Capability Uniform 32 KWord blocks • Chip-Erase Capability • Erase-Suspend/Erase-Resume Capabilities • Hardware Reset Pin RST# • Security-ID Feature SST 128 bits User 128 bits • Fast Read Access Time: 70 ns, 90 ns • Latched Address and Data • Fast Erase and Word-Program: Sector-Erase Time 36 ms typical Block-Erase Time 36 ms typical Chip-Erase Time 140 ms typical Word-Program Time 28 µs typical • Automatic Write Timing Internal VPP Generation • End-of-Write Detection Toggle Bits Data# Polling • CMOS I/O Compatibility • JEDEC Standard Flash EEPROM Pin Assignments and Command Sets • Packages Available 48-ball TFBGA 6mm x 8mm 48-ball WFBGA 5mm x 6mm 48-ball WFBGA 4mm x 6mm • All non-Pb lead-free devices are RoHS compliant PRODUCT DESCRIPTION The SST39WF1601/1602 devices are 1M x16 CMOS Multi-Purpose Flash Plus MPF+ manufactured with SST’s proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39WF1601/ 1602 write Program or Erase with a 1.65-1.95V power supply. These devices conform to JEDEC standard pin assignments for x16 memories. Featuring high performance Word-Program, the SST39WF1601/1602 devices provide a typical Word-Program time of 28 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST39WF1601/1602 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. 2008 Silicon Storage Technology, Inc. S71297-04-000 12/08 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. Data Sheet To meet high density, surface mount requirements, the SST39WF1601/1602 are offered in both 48-ball TFBGA and 48-ball WFBGA packages. See Figures 2 and 3 for pin assignments. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The SST39WF1601/1602 also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 9 mA to typically 5 µA. The Auto Low Power mode reduces the typical IDD active read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high. Read The Read operation of the SST39WF1601/1602 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details Figure 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 Word-Program Operation The SST39WF1601/1602 are programmed on a word-byword basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 40 µs. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 20 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. During the command sequence, WP# should be statically held high or low. PRODUCT ORDERING INFORMATION Data Sheet SST 39 WF 1602 - 70 - 4C - B3K E XX XXXX - XXX - XX - XXX X Environmental Attribute E1 = non-Pb Package Modifier K = 48 balls Q = 48 balls 66 possible positions Package Type B3 = TFBGA 6mm x 8mm MB = WFBGA 5mm x 6mm Y1 = WFBGA 4mm x 6mm Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns 90 = 90 ns Hardware Block Protection 1 = Bottom Boot-Block 2 = Top Boot-Block Device Density 160 = 16 Mbit Voltage W = 1.65-1.95V Product Series 39 = Multi-Purpose Flash Environmental suffix “E” denotes non-Pb solder. SST non-Pb solder devices are “RoHS Compliant”. Valid Combinations for SST39WF1601-70-4C-B3KE SST39WF1601-70-4C-MBQE SST39WF1601-70-4I-B3KE SST39WF1601-70-4I-MBQE SST39WF1601-90-4C-B3KE SST39WF1601-90-4C-MBQE SST39WF1601-90-4I-B3KE SST39WF1601-90-4I-MBQE Valid Combinations for SST39WF1602-70-4C-B3KE SST39WF1602-70-4C-MBQE SST39WF1602-70-4I-B3KE SST39WF1602-70-4I-MBQE SST39WF1602-90-4C-B3KE SST39WF1602-90-4C-MBQE SST39WF1602-90-4I-B3KE SST39WF1602-90-4I-MBQE SST39WF1601-70-4C-Y1QE SST39WF1601-70-4I-Y1QE SST39WF1601-90-4C-Y1QE SST39WF1601-90-4I-Y1QE SST39WF1602-70-4C-Y1QE SST39WF1602-70-4I-Y1QE SST39WF1602-90-4C-Y1QE SST39WF1602-90-4I-Y1QE Note Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. 2008 Silicon Storage Technology, Inc. S71297-04-000 12/08 Data Sheet PACKAGING DIAGRAMS 16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602 TOP VIEW ± 6 5 4 3 2 1 ABCDEFGH A1 CORNER SIDE VIEW ± ± BOTTOM VIEW ± 48X HGFEDCBA A1 CORNER SEATING PLANE Note: Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent. All linear dimensions are in millimeters. Coplanarity mm Ball opening size is mm ± mm 48-tfbga-B3K-6x8-450mic-4 Description Initial release Added MBQ package information including product numbers. Migrated document to Preliminary Specifications Updated Table 10 on page 12 Added 70 ns to Features Fast Read Access Time Added 70 ns columns to Table 14 Edited Product Ordering Information and Valid Combination to include 70 ns and remove leaded parts. Added YIQE package Changed 000010H to 000017H to three places in footnotes of Table 6 on page Date Oct 2005 Jul 2006 Aug 2007 Jul 2008 Dec 2008 Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 or 2008 Silicon Storage Technology, Inc. S71297-04-000 12/08

PDF Datasheet Preview

16 Mbit x16 Multi-Purpose Flash Plus

SST39WF1601 / SST39WF1602

FEATURES:

SST39WF160x2.7V 16Mb x16 MPF+ memories

Data Sheet
• Organized as 1M x16
• Single Voltage Read and Write Operations
1.65-1.95V
• Superior Reliability

Endurance 100,000 Cycles Typical Greater than 100 years Data Retention
• Low Power Consumption typical values at 5 MHz Active Current 5 mA typical Standby Current 5 µA typical Auto Low Power Mode 5 µA typical
• Hardware Block-Protection/WP# Input Pin Top Block-Protection top 32 KWord
for SST39WF1602 Bottom Block-Protection bottom 32 KWord
for SST39WF1601
• Sector-Erase Capability

Uniform 2 KWord sectors
• Block-Erase Capability

Uniform 32 KWord blocks
• Chip-Erase Capability
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin RST#
• Security-ID Feature SST 128 bits User 128 bits
• Fast Read Access Time:
70 ns, 90 ns
• Latched Address and Data
• Fast Erase and Word-Program:

Sector-Erase Time 36 ms typical Block-Erase Time 36 ms typical Chip-Erase Time 140 ms typical Word-Program Time 28 µs typical
• Automatic Write Timing Internal VPP Generation
• End-of-Write Detection Toggle Bits Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard

Flash EEPROM Pin Assignments and Command Sets
• Packages Available 48-ball TFBGA 6mm x 8mm 48-ball WFBGA 5mm x 6mm 48-ball WFBGA 4mm x 6mm
• All non-Pb lead-free devices are RoHS compliant

PRODUCT DESCRIPTION

The SST39WF1601/1602 devices are 1M x16 CMOS Multi-Purpose Flash Plus MPF+ manufactured with SST’s proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39WF1601/ 1602 write Program or Erase with a 1.65-1.95V power supply. These devices conform to JEDEC standard pin assignments for x16 memories.

Featuring high performance Word-Program, the SST39WF1601/1602 devices provide a typical Word-Program time of 28 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years.

The SST39WF1601/1602 devices are suited for applications that require convenient and economical updating of
program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications.

The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.
2008 Silicon Storage Technology, Inc.

S71297-04-000
12/08

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

To meet high density, surface mount requirements, the SST39WF1601/1602 are offered in both 48-ball TFBGA and 48-ball WFBGA packages. See Figures 2 and 3 for pin assignments.

Device Operation

Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

The SST39WF1601/1602 also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 9 mA to typically 5 µA. The Auto Low Power mode reduces the typical IDD active read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high.

Read

The Read operation of the SST39WF1601/1602 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details Figure
16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602

Word-Program Operation

The SST39WF1601/1602 are programmed on a word-byword basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 40 µs. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 20 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. During the command sequence, WP# should be statically held high or low.
PRODUCT ORDERING INFORMATION

Data Sheet

SST 39 WF 1602 - 70 - 4C - B3K E XX XXXX - XXX - XX - XXX X

Environmental Attribute E1 = non-Pb

Package Modifier K = 48 balls Q = 48 balls 66 possible positions

Package Type B3 = TFBGA 6mm x 8mm MB = WFBGA 5mm x 6mm Y1 = WFBGA 4mm x 6mm

Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C

Minimum Endurance 4 = 10,000 cycles

Read Access Speed 70 = 70 ns 90 = 90 ns

Hardware Block Protection 1 = Bottom Boot-Block 2 = Top Boot-Block

Device Density 160 = 16 Mbit

Voltage W = 1.65-1.95V

Product Series 39 = Multi-Purpose Flash

Environmental suffix “E” denotes non-Pb solder. SST non-Pb solder devices are “RoHS Compliant”.

Valid Combinations for SST39WF1601-70-4C-B3KE SST39WF1601-70-4C-MBQE SST39WF1601-70-4I-B3KE SST39WF1601-70-4I-MBQE SST39WF1601-90-4C-B3KE SST39WF1601-90-4C-MBQE SST39WF1601-90-4I-B3KE SST39WF1601-90-4I-MBQE

Valid Combinations for SST39WF1602-70-4C-B3KE SST39WF1602-70-4C-MBQE SST39WF1602-70-4I-B3KE SST39WF1602-70-4I-MBQE SST39WF1602-90-4C-B3KE SST39WF1602-90-4C-MBQE SST39WF1602-90-4I-B3KE SST39WF1602-90-4I-MBQE

SST39WF1601-70-4C-Y1QE SST39WF1601-70-4I-Y1QE SST39WF1601-90-4C-Y1QE SST39WF1601-90-4I-Y1QE

SST39WF1602-70-4C-Y1QE SST39WF1602-70-4I-Y1QE SST39WF1602-90-4C-Y1QE SST39WF1602-90-4I-Y1QE

Note Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
2008 Silicon Storage Technology, Inc.

S71297-04-000
12/08

Data Sheet

PACKAGING DIAGRAMS
16 Mbit Multi-Purpose Flash Plus SST39WF1601 / SST39WF1602

TOP VIEW ±
6 5 4 3 2 1

ABCDEFGH

A1 CORNER SIDE VIEW
± ±

BOTTOM VIEW
± 48X

HGFEDCBA

A1 CORNER

SEATING PLANE

Note:

Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.

All linear dimensions are in millimeters.

Coplanarity mm

Ball opening size is mm ± mm
48-tfbga-B3K-6x8-450mic-4
Description Initial release Added MBQ package information including product numbers. Migrated document to Preliminary Specifications Updated Table 10 on page 12 Added 70 ns to Features Fast Read Access Time Added 70 ns columns to Table 14 Edited Product Ordering Information and Valid Combination to include 70 ns and remove leaded parts. Added YIQE package Changed 000010H to 000017H to three places in footnotes of Table 6 on page

Date Oct 2005 Jul 2006

Aug 2007

Jul 2008 Dec 2008

Silicon Storage Technology, Inc.
• 1171 Sonora Court
• Sunnyvale, CA 94086
• Telephone 408-735-9110
• Fax 408-735-9036 or
2008 Silicon Storage Technology, Inc.

S71297-04-000
12/08

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived SST39WF1602-90-4I-MBQE Datasheet file may be downloaded here without warranties.

Datasheet ID: SST39WF1602-90-4I-MBQE 648212